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1; RUN: llc < %s | FileCheck %s2 3; Derived from 4; #include <arm_sve.h>5 6; void g();7 8; svboolx2_t f0(int64_t i, int64_t n) {9; svboolx2_t r = svwhilelt_b16_x2(i, n);10; g();11; return r;12; }13 14; svboolx2_t f1(svcount_t n) {15; svboolx2_t r = svpext_lane_c8_x2(n, 1);16; g();17; return r;18; }19; 20; Check that predicate register pairs are spilled/filled without an ICE in the backend.21 22target triple = "aarch64-unknown-linux"23 24define <vscale x 32 x i1> @f0(i64 %i, i64 %n) #0 {25entry:26 %0 = tail call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilelt.x2.nxv8i1(i64 %i, i64 %n)27 %1 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %0, 028 %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)29 %3 = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> %2, i64 0)30 %4 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %0, 131 %5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)32 %6 = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> %3, <vscale x 16 x i1> %5, i64 16)33 tail call void @g()34 ret <vscale x 32 x i1> %635}36; CHECK-LABEL: f0:37; CHECK: whilelt { p0.h, p1.h }38; CHECK: str p0, [sp, #6, mul vl]39; CHECK: str p1, [sp, #7, mul vl]40; CHECK: ldr p0, [sp, #6, mul vl]41; CHECK: ldr p1, [sp, #7, mul vl]42 43define <vscale x 32 x i1> @f1(target("aarch64.svcount") %n) #0 {44entry:45 %0 = tail call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.pext.x2.nxv16i1(target("aarch64.svcount") %n, i32 1)46 %1 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, 047 %2 = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> poison, <vscale x 16 x i1> %1, i64 0)48 %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, 149 %4 = tail call <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1> %2, <vscale x 16 x i1> %3, i64 16)50 tail call void @g()51 ret <vscale x 32 x i1> %452}53 54; CHECK-LABEL: f1:55; CHECK: pext { p0.b, p1.b }56; CHECK: str p0, [sp, #6, mul vl]57; CHECK: str p1, [sp, #7, mul vl]58; CHECK: ldr p0, [sp, #6, mul vl]59; CHECK: ldr p1, [sp, #7, mul vl]60 61declare void @g(...)62declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilelt.x2.nxv8i1(i64, i64)63declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>)64declare <vscale x 32 x i1> @llvm.vector.insert.nxv32i1.nxv16i1(<vscale x 32 x i1>, <vscale x 16 x i1>, i64 immarg)65declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.pext.x2.nxv16i1(target("aarch64.svcount"), i32 immarg) #166 67attributes #0 = { nounwind "target-features"="+sve,+sve2,+sve2p1" }68