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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -mattr=+neon,+sve2 -verify-machineinstrs %s -o - | FileCheck %s3 4define <vscale x 4 x i32> @add_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {5; CHECK-LABEL: add_v4i32:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: ptrue p0.s8; CHECK-NEXT: add z1.s, z1.s, z2.s9; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #010; CHECK-NEXT: mov z0.s, p0/m, z1.s11; CHECK-NEXT: ret12entry:13 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer14 %a = add <vscale x 4 x i32> %x, %y15 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z16 ret <vscale x 4 x i32> %b17}18 19define <vscale x 8 x i16> @add_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {20; CHECK-LABEL: add_v8i16:21; CHECK: // %bb.0: // %entry22; CHECK-NEXT: ptrue p0.h23; CHECK-NEXT: add z1.h, z1.h, z2.h24; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #025; CHECK-NEXT: mov z0.h, p0/m, z1.h26; CHECK-NEXT: ret27entry:28 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer29 %a = add <vscale x 8 x i16> %x, %y30 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z31 ret <vscale x 8 x i16> %b32}33 34define <vscale x 16 x i8> @add_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {35; CHECK-LABEL: add_v16i8:36; CHECK: // %bb.0: // %entry37; CHECK-NEXT: ptrue p0.b38; CHECK-NEXT: add z1.b, z1.b, z2.b39; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #040; CHECK-NEXT: mov z0.b, p0/m, z1.b41; CHECK-NEXT: ret42entry:43 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer44 %a = add <vscale x 16 x i8> %x, %y45 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z46 ret <vscale x 16 x i8> %b47}48 49define <vscale x 4 x i32> @sub_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {50; CHECK-LABEL: sub_v4i32:51; CHECK: // %bb.0: // %entry52; CHECK-NEXT: ptrue p0.s53; CHECK-NEXT: sub z1.s, z1.s, z2.s54; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #055; CHECK-NEXT: mov z0.s, p0/m, z1.s56; CHECK-NEXT: ret57entry:58 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer59 %a = sub <vscale x 4 x i32> %x, %y60 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z61 ret <vscale x 4 x i32> %b62}63 64define <vscale x 8 x i16> @sub_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {65; CHECK-LABEL: sub_v8i16:66; CHECK: // %bb.0: // %entry67; CHECK-NEXT: ptrue p0.h68; CHECK-NEXT: sub z1.h, z1.h, z2.h69; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #070; CHECK-NEXT: mov z0.h, p0/m, z1.h71; CHECK-NEXT: ret72entry:73 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer74 %a = sub <vscale x 8 x i16> %x, %y75 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z76 ret <vscale x 8 x i16> %b77}78 79define <vscale x 16 x i8> @sub_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {80; CHECK-LABEL: sub_v16i8:81; CHECK: // %bb.0: // %entry82; CHECK-NEXT: ptrue p0.b83; CHECK-NEXT: sub z1.b, z1.b, z2.b84; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #085; CHECK-NEXT: mov z0.b, p0/m, z1.b86; CHECK-NEXT: ret87entry:88 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer89 %a = sub <vscale x 16 x i8> %x, %y90 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z91 ret <vscale x 16 x i8> %b92}93 94define <vscale x 4 x i32> @mul_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {95; CHECK-LABEL: mul_v4i32:96; CHECK: // %bb.0: // %entry97; CHECK-NEXT: ptrue p0.s98; CHECK-NEXT: mul z1.s, z1.s, z2.s99; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0100; CHECK-NEXT: mov z0.s, p0/m, z1.s101; CHECK-NEXT: ret102entry:103 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer104 %a = mul <vscale x 4 x i32> %x, %y105 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z106 ret <vscale x 4 x i32> %b107}108 109define <vscale x 8 x i16> @mul_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {110; CHECK-LABEL: mul_v8i16:111; CHECK: // %bb.0: // %entry112; CHECK-NEXT: ptrue p0.h113; CHECK-NEXT: mul z1.h, z1.h, z2.h114; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0115; CHECK-NEXT: mov z0.h, p0/m, z1.h116; CHECK-NEXT: ret117entry:118 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer119 %a = mul <vscale x 8 x i16> %x, %y120 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z121 ret <vscale x 8 x i16> %b122}123 124define <vscale x 16 x i8> @mul_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {125; CHECK-LABEL: mul_v16i8:126; CHECK: // %bb.0: // %entry127; CHECK-NEXT: ptrue p0.b128; CHECK-NEXT: mul z1.b, z1.b, z2.b129; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0130; CHECK-NEXT: mov z0.b, p0/m, z1.b131; CHECK-NEXT: ret132entry:133 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer134 %a = mul <vscale x 16 x i8> %x, %y135 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z136 ret <vscale x 16 x i8> %b137}138 139define <vscale x 4 x i32> @and_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {140; CHECK-LABEL: and_v4i32:141; CHECK: // %bb.0: // %entry142; CHECK-NEXT: ptrue p0.s143; CHECK-NEXT: and z1.d, z1.d, z2.d144; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0145; CHECK-NEXT: mov z0.s, p0/m, z1.s146; CHECK-NEXT: ret147entry:148 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer149 %a = and <vscale x 4 x i32> %x, %y150 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z151 ret <vscale x 4 x i32> %b152}153 154define <vscale x 8 x i16> @and_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {155; CHECK-LABEL: and_v8i16:156; CHECK: // %bb.0: // %entry157; CHECK-NEXT: ptrue p0.h158; CHECK-NEXT: and z1.d, z1.d, z2.d159; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0160; CHECK-NEXT: mov z0.h, p0/m, z1.h161; CHECK-NEXT: ret162entry:163 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer164 %a = and <vscale x 8 x i16> %x, %y165 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z166 ret <vscale x 8 x i16> %b167}168 169define <vscale x 16 x i8> @and_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {170; CHECK-LABEL: and_v16i8:171; CHECK: // %bb.0: // %entry172; CHECK-NEXT: ptrue p0.b173; CHECK-NEXT: and z1.d, z1.d, z2.d174; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0175; CHECK-NEXT: mov z0.b, p0/m, z1.b176; CHECK-NEXT: ret177entry:178 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer179 %a = and <vscale x 16 x i8> %x, %y180 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z181 ret <vscale x 16 x i8> %b182}183 184define <vscale x 4 x i32> @or_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {185; CHECK-LABEL: or_v4i32:186; CHECK: // %bb.0: // %entry187; CHECK-NEXT: ptrue p0.s188; CHECK-NEXT: orr z1.d, z1.d, z2.d189; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0190; CHECK-NEXT: mov z0.s, p0/m, z1.s191; CHECK-NEXT: ret192entry:193 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer194 %a = or <vscale x 4 x i32> %x, %y195 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z196 ret <vscale x 4 x i32> %b197}198 199define <vscale x 8 x i16> @or_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {200; CHECK-LABEL: or_v8i16:201; CHECK: // %bb.0: // %entry202; CHECK-NEXT: ptrue p0.h203; CHECK-NEXT: orr z1.d, z1.d, z2.d204; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0205; CHECK-NEXT: mov z0.h, p0/m, z1.h206; CHECK-NEXT: ret207entry:208 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer209 %a = or <vscale x 8 x i16> %x, %y210 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z211 ret <vscale x 8 x i16> %b212}213 214define <vscale x 16 x i8> @or_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {215; CHECK-LABEL: or_v16i8:216; CHECK: // %bb.0: // %entry217; CHECK-NEXT: ptrue p0.b218; CHECK-NEXT: orr z1.d, z1.d, z2.d219; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0220; CHECK-NEXT: mov z0.b, p0/m, z1.b221; CHECK-NEXT: ret222entry:223 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer224 %a = or <vscale x 16 x i8> %x, %y225 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z226 ret <vscale x 16 x i8> %b227}228 229define <vscale x 4 x i32> @xor_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {230; CHECK-LABEL: xor_v4i32:231; CHECK: // %bb.0: // %entry232; CHECK-NEXT: ptrue p0.s233; CHECK-NEXT: eor z1.d, z1.d, z2.d234; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0235; CHECK-NEXT: mov z0.s, p0/m, z1.s236; CHECK-NEXT: ret237entry:238 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer239 %a = xor <vscale x 4 x i32> %x, %y240 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z241 ret <vscale x 4 x i32> %b242}243 244define <vscale x 8 x i16> @xor_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {245; CHECK-LABEL: xor_v8i16:246; CHECK: // %bb.0: // %entry247; CHECK-NEXT: ptrue p0.h248; CHECK-NEXT: eor z1.d, z1.d, z2.d249; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0250; CHECK-NEXT: mov z0.h, p0/m, z1.h251; CHECK-NEXT: ret252entry:253 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer254 %a = xor <vscale x 8 x i16> %x, %y255 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z256 ret <vscale x 8 x i16> %b257}258 259define <vscale x 16 x i8> @xor_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {260; CHECK-LABEL: xor_v16i8:261; CHECK: // %bb.0: // %entry262; CHECK-NEXT: ptrue p0.b263; CHECK-NEXT: eor z1.d, z1.d, z2.d264; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0265; CHECK-NEXT: mov z0.b, p0/m, z1.b266; CHECK-NEXT: ret267entry:268 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer269 %a = xor <vscale x 16 x i8> %x, %y270 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z271 ret <vscale x 16 x i8> %b272}273 274define <vscale x 4 x i32> @andnot_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {275; CHECK-LABEL: andnot_v4i32:276; CHECK: // %bb.0: // %entry277; CHECK-NEXT: ptrue p0.s278; CHECK-NEXT: bic z1.d, z1.d, z2.d279; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0280; CHECK-NEXT: mov z0.s, p0/m, z1.s281; CHECK-NEXT: ret282entry:283 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer284 %y1 = xor <vscale x 4 x i32> %y, splat (i32 -1)285 %a = and <vscale x 4 x i32> %x, %y1286 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z287 ret <vscale x 4 x i32> %b288}289 290define <vscale x 8 x i16> @andnot_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {291; CHECK-LABEL: andnot_v8i16:292; CHECK: // %bb.0: // %entry293; CHECK-NEXT: ptrue p0.h294; CHECK-NEXT: bic z1.d, z1.d, z2.d295; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0296; CHECK-NEXT: mov z0.h, p0/m, z1.h297; CHECK-NEXT: ret298entry:299 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer300 %y1 = xor <vscale x 8 x i16> %y, splat (i16 -1)301 %a = and <vscale x 8 x i16> %x, %y1302 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z303 ret <vscale x 8 x i16> %b304}305 306define <vscale x 16 x i8> @andnot_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {307; CHECK-LABEL: andnot_v16i8:308; CHECK: // %bb.0: // %entry309; CHECK-NEXT: ptrue p0.b310; CHECK-NEXT: bic z1.d, z1.d, z2.d311; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0312; CHECK-NEXT: mov z0.b, p0/m, z1.b313; CHECK-NEXT: ret314entry:315 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer316 %y1 = xor <vscale x 16 x i8> %y, splat (i8 -1)317 %a = and <vscale x 16 x i8> %x, %y1318 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z319 ret <vscale x 16 x i8> %b320}321 322define <vscale x 4 x i32> @ornot_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {323; CHECK-LABEL: ornot_v4i32:324; CHECK: // %bb.0: // %entry325; CHECK-NEXT: ptrue p0.s326; CHECK-NEXT: bsl2n z1.d, z1.d, z2.d, z1.d327; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0328; CHECK-NEXT: mov z0.s, p0/m, z1.s329; CHECK-NEXT: ret330entry:331 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer332 %y1 = xor <vscale x 4 x i32> %y, splat (i32 -1)333 %a = or <vscale x 4 x i32> %x, %y1334 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z335 ret <vscale x 4 x i32> %b336}337 338define <vscale x 8 x i16> @ornot_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {339; CHECK-LABEL: ornot_v8i16:340; CHECK: // %bb.0: // %entry341; CHECK-NEXT: ptrue p0.h342; CHECK-NEXT: bsl2n z1.d, z1.d, z2.d, z1.d343; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0344; CHECK-NEXT: mov z0.h, p0/m, z1.h345; CHECK-NEXT: ret346entry:347 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer348 %y1 = xor <vscale x 8 x i16> %y, splat (i16 -1)349 %a = or <vscale x 8 x i16> %x, %y1350 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z351 ret <vscale x 8 x i16> %b352}353 354define <vscale x 16 x i8> @ornot_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {355; CHECK-LABEL: ornot_v16i8:356; CHECK: // %bb.0: // %entry357; CHECK-NEXT: ptrue p0.b358; CHECK-NEXT: bsl2n z1.d, z1.d, z2.d, z1.d359; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0360; CHECK-NEXT: mov z0.b, p0/m, z1.b361; CHECK-NEXT: ret362entry:363 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer364 %y1 = xor <vscale x 16 x i8> %y, splat (i8 -1)365 %a = or <vscale x 16 x i8> %x, %y1366 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z367 ret <vscale x 16 x i8> %b368}369 370define <vscale x 4 x float> @fadd_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, <vscale x 4 x float> %y) {371; CHECK-LABEL: fadd_v4f32:372; CHECK: // %bb.0: // %entry373; CHECK-NEXT: ptrue p0.s374; CHECK-NEXT: fadd z1.s, z1.s, z2.s375; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0376; CHECK-NEXT: mov z0.s, p0/m, z1.s377; CHECK-NEXT: ret378entry:379 %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer380 %a = fadd <vscale x 4 x float> %x, %y381 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z382 ret <vscale x 4 x float> %b383}384 385define <vscale x 8 x half> @fadd_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, <vscale x 8 x half> %y) {386; CHECK-LABEL: fadd_v8f16:387; CHECK: // %bb.0: // %entry388; CHECK-NEXT: ptrue p0.h389; CHECK-NEXT: fadd z1.h, z1.h, z2.h390; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0391; CHECK-NEXT: mov z0.h, p0/m, z1.h392; CHECK-NEXT: ret393entry:394 %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer395 %a = fadd <vscale x 8 x half> %x, %y396 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z397 ret <vscale x 8 x half> %b398}399 400define <vscale x 4 x float> @fsub_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, <vscale x 4 x float> %y) {401; CHECK-LABEL: fsub_v4f32:402; CHECK: // %bb.0: // %entry403; CHECK-NEXT: ptrue p0.s404; CHECK-NEXT: fsub z1.s, z1.s, z2.s405; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0406; CHECK-NEXT: mov z0.s, p0/m, z1.s407; CHECK-NEXT: ret408entry:409 %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer410 %a = fsub <vscale x 4 x float> %x, %y411 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z412 ret <vscale x 4 x float> %b413}414 415define <vscale x 8 x half> @fsub_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, <vscale x 8 x half> %y) {416; CHECK-LABEL: fsub_v8f16:417; CHECK: // %bb.0: // %entry418; CHECK-NEXT: ptrue p0.h419; CHECK-NEXT: fsub z1.h, z1.h, z2.h420; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0421; CHECK-NEXT: mov z0.h, p0/m, z1.h422; CHECK-NEXT: ret423entry:424 %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer425 %a = fsub <vscale x 8 x half> %x, %y426 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z427 ret <vscale x 8 x half> %b428}429 430define <vscale x 4 x float> @fmul_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, <vscale x 4 x float> %y) {431; CHECK-LABEL: fmul_v4f32:432; CHECK: // %bb.0: // %entry433; CHECK-NEXT: ptrue p0.s434; CHECK-NEXT: fmul z1.s, z1.s, z2.s435; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0436; CHECK-NEXT: mov z0.s, p0/m, z1.s437; CHECK-NEXT: ret438entry:439 %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer440 %a = fmul <vscale x 4 x float> %x, %y441 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z442 ret <vscale x 4 x float> %b443}444 445define <vscale x 8 x half> @fmul_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, <vscale x 8 x half> %y) {446; CHECK-LABEL: fmul_v8f16:447; CHECK: // %bb.0: // %entry448; CHECK-NEXT: ptrue p0.h449; CHECK-NEXT: fmul z1.h, z1.h, z2.h450; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0451; CHECK-NEXT: mov z0.h, p0/m, z1.h452; CHECK-NEXT: ret453entry:454 %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer455 %a = fmul <vscale x 8 x half> %x, %y456 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z457 ret <vscale x 8 x half> %b458}459 460define <vscale x 4 x i32> @icmp_slt_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {461; CHECK-LABEL: icmp_slt_v4i32:462; CHECK: // %bb.0: // %entry463; CHECK-NEXT: ptrue p0.s464; CHECK-NEXT: cmpeq p1.s, p0/z, z0.s, #0465; CHECK-NEXT: smin z1.s, p0/m, z1.s, z2.s466; CHECK-NEXT: mov z0.s, p1/m, z1.s467; CHECK-NEXT: ret468entry:469 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer470 %a1 = icmp slt <vscale x 4 x i32> %x, %y471 %a = select <vscale x 4 x i1> %a1, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y472 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z473 ret <vscale x 4 x i32> %b474}475 476define <vscale x 8 x i16> @icmp_slt_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {477; CHECK-LABEL: icmp_slt_v8i16:478; CHECK: // %bb.0: // %entry479; CHECK-NEXT: ptrue p0.h480; CHECK-NEXT: cmpeq p1.h, p0/z, z0.h, #0481; CHECK-NEXT: smin z1.h, p0/m, z1.h, z2.h482; CHECK-NEXT: mov z0.h, p1/m, z1.h483; CHECK-NEXT: ret484entry:485 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer486 %a1 = icmp slt <vscale x 8 x i16> %x, %y487 %a = select <vscale x 8 x i1> %a1, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y488 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z489 ret <vscale x 8 x i16> %b490}491 492define <vscale x 16 x i8> @icmp_slt_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {493; CHECK-LABEL: icmp_slt_v16i8:494; CHECK: // %bb.0: // %entry495; CHECK-NEXT: ptrue p0.b496; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0497; CHECK-NEXT: smin z1.b, p0/m, z1.b, z2.b498; CHECK-NEXT: mov z0.b, p1/m, z1.b499; CHECK-NEXT: ret500entry:501 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer502 %a1 = icmp slt <vscale x 16 x i8> %x, %y503 %a = select <vscale x 16 x i1> %a1, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y504 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z505 ret <vscale x 16 x i8> %b506}507 508define <vscale x 4 x i32> @icmp_sgt_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {509; CHECK-LABEL: icmp_sgt_v4i32:510; CHECK: // %bb.0: // %entry511; CHECK-NEXT: ptrue p0.s512; CHECK-NEXT: cmpeq p1.s, p0/z, z0.s, #0513; CHECK-NEXT: smax z1.s, p0/m, z1.s, z2.s514; CHECK-NEXT: mov z0.s, p1/m, z1.s515; CHECK-NEXT: ret516entry:517 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer518 %a1 = icmp sgt <vscale x 4 x i32> %x, %y519 %a = select <vscale x 4 x i1> %a1, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y520 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z521 ret <vscale x 4 x i32> %b522}523 524define <vscale x 8 x i16> @icmp_sgt_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {525; CHECK-LABEL: icmp_sgt_v8i16:526; CHECK: // %bb.0: // %entry527; CHECK-NEXT: ptrue p0.h528; CHECK-NEXT: cmpeq p1.h, p0/z, z0.h, #0529; CHECK-NEXT: smax z1.h, p0/m, z1.h, z2.h530; CHECK-NEXT: mov z0.h, p1/m, z1.h531; CHECK-NEXT: ret532entry:533 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer534 %a1 = icmp sgt <vscale x 8 x i16> %x, %y535 %a = select <vscale x 8 x i1> %a1, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y536 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z537 ret <vscale x 8 x i16> %b538}539 540define <vscale x 16 x i8> @icmp_sgt_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {541; CHECK-LABEL: icmp_sgt_v16i8:542; CHECK: // %bb.0: // %entry543; CHECK-NEXT: ptrue p0.b544; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0545; CHECK-NEXT: smax z1.b, p0/m, z1.b, z2.b546; CHECK-NEXT: mov z0.b, p1/m, z1.b547; CHECK-NEXT: ret548entry:549 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer550 %a1 = icmp sgt <vscale x 16 x i8> %x, %y551 %a = select <vscale x 16 x i1> %a1, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y552 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z553 ret <vscale x 16 x i8> %b554}555 556define <vscale x 4 x i32> @icmp_ult_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {557; CHECK-LABEL: icmp_ult_v4i32:558; CHECK: // %bb.0: // %entry559; CHECK-NEXT: ptrue p0.s560; CHECK-NEXT: cmpeq p1.s, p0/z, z0.s, #0561; CHECK-NEXT: umin z1.s, p0/m, z1.s, z2.s562; CHECK-NEXT: mov z0.s, p1/m, z1.s563; CHECK-NEXT: ret564entry:565 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer566 %a1 = icmp ult <vscale x 4 x i32> %x, %y567 %a = select <vscale x 4 x i1> %a1, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y568 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z569 ret <vscale x 4 x i32> %b570}571 572define <vscale x 8 x i16> @icmp_ult_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {573; CHECK-LABEL: icmp_ult_v8i16:574; CHECK: // %bb.0: // %entry575; CHECK-NEXT: ptrue p0.h576; CHECK-NEXT: cmpeq p1.h, p0/z, z0.h, #0577; CHECK-NEXT: umin z1.h, p0/m, z1.h, z2.h578; CHECK-NEXT: mov z0.h, p1/m, z1.h579; CHECK-NEXT: ret580entry:581 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer582 %a1 = icmp ult <vscale x 8 x i16> %x, %y583 %a = select <vscale x 8 x i1> %a1, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y584 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z585 ret <vscale x 8 x i16> %b586}587 588define <vscale x 16 x i8> @icmp_ult_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {589; CHECK-LABEL: icmp_ult_v16i8:590; CHECK: // %bb.0: // %entry591; CHECK-NEXT: ptrue p0.b592; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0593; CHECK-NEXT: umin z1.b, p0/m, z1.b, z2.b594; CHECK-NEXT: mov z0.b, p1/m, z1.b595; CHECK-NEXT: ret596entry:597 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer598 %a1 = icmp ult <vscale x 16 x i8> %x, %y599 %a = select <vscale x 16 x i1> %a1, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y600 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z601 ret <vscale x 16 x i8> %b602}603 604define <vscale x 4 x i32> @icmp_ugt_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {605; CHECK-LABEL: icmp_ugt_v4i32:606; CHECK: // %bb.0: // %entry607; CHECK-NEXT: ptrue p0.s608; CHECK-NEXT: cmpeq p1.s, p0/z, z0.s, #0609; CHECK-NEXT: umax z1.s, p0/m, z1.s, z2.s610; CHECK-NEXT: mov z0.s, p1/m, z1.s611; CHECK-NEXT: ret612entry:613 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer614 %a1 = icmp ugt <vscale x 4 x i32> %x, %y615 %a = select <vscale x 4 x i1> %a1, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y616 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z617 ret <vscale x 4 x i32> %b618}619 620define <vscale x 8 x i16> @icmp_ugt_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {621; CHECK-LABEL: icmp_ugt_v8i16:622; CHECK: // %bb.0: // %entry623; CHECK-NEXT: ptrue p0.h624; CHECK-NEXT: cmpeq p1.h, p0/z, z0.h, #0625; CHECK-NEXT: umax z1.h, p0/m, z1.h, z2.h626; CHECK-NEXT: mov z0.h, p1/m, z1.h627; CHECK-NEXT: ret628entry:629 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer630 %a1 = icmp ugt <vscale x 8 x i16> %x, %y631 %a = select <vscale x 8 x i1> %a1, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y632 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z633 ret <vscale x 8 x i16> %b634}635 636define <vscale x 16 x i8> @icmp_ugt_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {637; CHECK-LABEL: icmp_ugt_v16i8:638; CHECK: // %bb.0: // %entry639; CHECK-NEXT: ptrue p0.b640; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0641; CHECK-NEXT: umax z1.b, p0/m, z1.b, z2.b642; CHECK-NEXT: mov z0.b, p1/m, z1.b643; CHECK-NEXT: ret644entry:645 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer646 %a1 = icmp ugt <vscale x 16 x i8> %x, %y647 %a = select <vscale x 16 x i1> %a1, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y648 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z649 ret <vscale x 16 x i8> %b650}651 652define <vscale x 4 x float> @fcmp_fast_olt_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, <vscale x 4 x float> %y) {653; CHECK-LABEL: fcmp_fast_olt_v4f32:654; CHECK: // %bb.0: // %entry655; CHECK-NEXT: ptrue p0.s656; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, #0.0657; CHECK-NEXT: fminnm z1.s, p0/m, z1.s, z2.s658; CHECK-NEXT: mov z0.s, p1/m, z1.s659; CHECK-NEXT: ret660entry:661 %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer662 %a1 = fcmp fast olt <vscale x 4 x float> %x, %y663 %a = select <vscale x 4 x i1> %a1, <vscale x 4 x float> %x, <vscale x 4 x float> %y664 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z665 ret <vscale x 4 x float> %b666}667 668define <vscale x 8 x half> @fcmp_fast_olt_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, <vscale x 8 x half> %y) {669; CHECK-LABEL: fcmp_fast_olt_v8f16:670; CHECK: // %bb.0: // %entry671; CHECK-NEXT: ptrue p0.h672; CHECK-NEXT: fcmeq p1.h, p0/z, z0.h, #0.0673; CHECK-NEXT: fminnm z1.h, p0/m, z1.h, z2.h674; CHECK-NEXT: mov z0.h, p1/m, z1.h675; CHECK-NEXT: ret676entry:677 %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer678 %a1 = fcmp fast olt <vscale x 8 x half> %x, %y679 %a = select <vscale x 8 x i1> %a1, <vscale x 8 x half> %x, <vscale x 8 x half> %y680 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z681 ret <vscale x 8 x half> %b682}683 684define <vscale x 4 x float> @fcmp_fast_ogt_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, <vscale x 4 x float> %y) {685; CHECK-LABEL: fcmp_fast_ogt_v4f32:686; CHECK: // %bb.0: // %entry687; CHECK-NEXT: ptrue p0.s688; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, #0.0689; CHECK-NEXT: fmaxnm z1.s, p0/m, z1.s, z2.s690; CHECK-NEXT: mov z0.s, p1/m, z1.s691; CHECK-NEXT: ret692entry:693 %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer694 %a1 = fcmp fast ogt <vscale x 4 x float> %x, %y695 %a = select <vscale x 4 x i1> %a1, <vscale x 4 x float> %x, <vscale x 4 x float> %y696 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z697 ret <vscale x 4 x float> %b698}699 700define <vscale x 8 x half> @fcmp_fast_ogt_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, <vscale x 8 x half> %y) {701; CHECK-LABEL: fcmp_fast_ogt_v8f16:702; CHECK: // %bb.0: // %entry703; CHECK-NEXT: ptrue p0.h704; CHECK-NEXT: fcmeq p1.h, p0/z, z0.h, #0.0705; CHECK-NEXT: fmaxnm z1.h, p0/m, z1.h, z2.h706; CHECK-NEXT: mov z0.h, p1/m, z1.h707; CHECK-NEXT: ret708entry:709 %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer710 %a1 = fcmp fast ogt <vscale x 8 x half> %x, %y711 %a = select <vscale x 8 x i1> %a1, <vscale x 8 x half> %x, <vscale x 8 x half> %y712 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z713 ret <vscale x 8 x half> %b714}715 716define <vscale x 4 x i32> @sadd_sat_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {717; CHECK-LABEL: sadd_sat_v4i32:718; CHECK: // %bb.0: // %entry719; CHECK-NEXT: ptrue p0.s720; CHECK-NEXT: sqadd z1.s, z1.s, z2.s721; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0722; CHECK-NEXT: mov z0.s, p0/m, z1.s723; CHECK-NEXT: ret724entry:725 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer726 %a = call <vscale x 4 x i32> @llvm.sadd.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)727 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z728 ret <vscale x 4 x i32> %b729}730 731define <vscale x 8 x i16> @sadd_sat_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {732; CHECK-LABEL: sadd_sat_v8i16:733; CHECK: // %bb.0: // %entry734; CHECK-NEXT: ptrue p0.h735; CHECK-NEXT: sqadd z1.h, z1.h, z2.h736; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0737; CHECK-NEXT: mov z0.h, p0/m, z1.h738; CHECK-NEXT: ret739entry:740 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer741 %a = call <vscale x 8 x i16> @llvm.sadd.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)742 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z743 ret <vscale x 8 x i16> %b744}745 746define <vscale x 16 x i8> @sadd_sat_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {747; CHECK-LABEL: sadd_sat_v16i8:748; CHECK: // %bb.0: // %entry749; CHECK-NEXT: ptrue p0.b750; CHECK-NEXT: sqadd z1.b, z1.b, z2.b751; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0752; CHECK-NEXT: mov z0.b, p0/m, z1.b753; CHECK-NEXT: ret754entry:755 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer756 %a = call <vscale x 16 x i8> @llvm.sadd.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)757 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z758 ret <vscale x 16 x i8> %b759}760 761define <vscale x 4 x i32> @uadd_sat_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {762; CHECK-LABEL: uadd_sat_v4i32:763; CHECK: // %bb.0: // %entry764; CHECK-NEXT: ptrue p0.s765; CHECK-NEXT: uqadd z1.s, z1.s, z2.s766; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0767; CHECK-NEXT: mov z0.s, p0/m, z1.s768; CHECK-NEXT: ret769entry:770 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer771 %a = call <vscale x 4 x i32> @llvm.uadd.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)772 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z773 ret <vscale x 4 x i32> %b774}775 776define <vscale x 8 x i16> @uadd_sat_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {777; CHECK-LABEL: uadd_sat_v8i16:778; CHECK: // %bb.0: // %entry779; CHECK-NEXT: ptrue p0.h780; CHECK-NEXT: uqadd z1.h, z1.h, z2.h781; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0782; CHECK-NEXT: mov z0.h, p0/m, z1.h783; CHECK-NEXT: ret784entry:785 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer786 %a = call <vscale x 8 x i16> @llvm.uadd.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)787 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z788 ret <vscale x 8 x i16> %b789}790 791define <vscale x 16 x i8> @uadd_sat_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {792; CHECK-LABEL: uadd_sat_v16i8:793; CHECK: // %bb.0: // %entry794; CHECK-NEXT: ptrue p0.b795; CHECK-NEXT: uqadd z1.b, z1.b, z2.b796; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0797; CHECK-NEXT: mov z0.b, p0/m, z1.b798; CHECK-NEXT: ret799entry:800 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer801 %a = call <vscale x 16 x i8> @llvm.uadd.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)802 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z803 ret <vscale x 16 x i8> %b804}805 806define <vscale x 4 x i32> @ssub_sat_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {807; CHECK-LABEL: ssub_sat_v4i32:808; CHECK: // %bb.0: // %entry809; CHECK-NEXT: ptrue p0.s810; CHECK-NEXT: sqsub z1.s, z1.s, z2.s811; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0812; CHECK-NEXT: mov z0.s, p0/m, z1.s813; CHECK-NEXT: ret814entry:815 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer816 %a = call <vscale x 4 x i32> @llvm.ssub.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)817 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z818 ret <vscale x 4 x i32> %b819}820 821define <vscale x 8 x i16> @ssub_sat_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {822; CHECK-LABEL: ssub_sat_v8i16:823; CHECK: // %bb.0: // %entry824; CHECK-NEXT: ptrue p0.h825; CHECK-NEXT: sqsub z1.h, z1.h, z2.h826; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0827; CHECK-NEXT: mov z0.h, p0/m, z1.h828; CHECK-NEXT: ret829entry:830 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer831 %a = call <vscale x 8 x i16> @llvm.ssub.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)832 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z833 ret <vscale x 8 x i16> %b834}835 836define <vscale x 16 x i8> @ssub_sat_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {837; CHECK-LABEL: ssub_sat_v16i8:838; CHECK: // %bb.0: // %entry839; CHECK-NEXT: ptrue p0.b840; CHECK-NEXT: sqsub z1.b, z1.b, z2.b841; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0842; CHECK-NEXT: mov z0.b, p0/m, z1.b843; CHECK-NEXT: ret844entry:845 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer846 %a = call <vscale x 16 x i8> @llvm.ssub.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)847 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z848 ret <vscale x 16 x i8> %b849}850 851define <vscale x 4 x i32> @usub_sat_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {852; CHECK-LABEL: usub_sat_v4i32:853; CHECK: // %bb.0: // %entry854; CHECK-NEXT: ptrue p0.s855; CHECK-NEXT: uqsub z1.s, z1.s, z2.s856; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0857; CHECK-NEXT: mov z0.s, p0/m, z1.s858; CHECK-NEXT: ret859entry:860 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer861 %a = call <vscale x 4 x i32> @llvm.usub.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)862 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z863 ret <vscale x 4 x i32> %b864}865 866define <vscale x 8 x i16> @usub_sat_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {867; CHECK-LABEL: usub_sat_v8i16:868; CHECK: // %bb.0: // %entry869; CHECK-NEXT: ptrue p0.h870; CHECK-NEXT: uqsub z1.h, z1.h, z2.h871; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0872; CHECK-NEXT: mov z0.h, p0/m, z1.h873; CHECK-NEXT: ret874entry:875 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer876 %a = call <vscale x 8 x i16> @llvm.usub.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)877 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z878 ret <vscale x 8 x i16> %b879}880 881define <vscale x 16 x i8> @usub_sat_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {882; CHECK-LABEL: usub_sat_v16i8:883; CHECK: // %bb.0: // %entry884; CHECK-NEXT: ptrue p0.b885; CHECK-NEXT: uqsub z1.b, z1.b, z2.b886; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0887; CHECK-NEXT: mov z0.b, p0/m, z1.b888; CHECK-NEXT: ret889entry:890 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer891 %a = call <vscale x 16 x i8> @llvm.usub.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)892 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z893 ret <vscale x 16 x i8> %b894}895 896define <vscale x 4 x i32> @addqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {897; CHECK-LABEL: addqr_v4i32:898; CHECK: // %bb.0: // %entry899; CHECK-NEXT: ptrue p0.s900; CHECK-NEXT: mov z2.s, w0901; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0902; CHECK-NEXT: add z1.s, z1.s, z2.s903; CHECK-NEXT: mov z0.s, p0/m, z1.s904; CHECK-NEXT: ret905entry:906 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer907 %i = insertelement <vscale x 4 x i32> poison, i32 %y, i32 0908 %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer909 %a = add <vscale x 4 x i32> %x, %ys910 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z911 ret <vscale x 4 x i32> %b912}913 914define <vscale x 8 x i16> @addqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {915; CHECK-LABEL: addqr_v8i16:916; CHECK: // %bb.0: // %entry917; CHECK-NEXT: ptrue p0.h918; CHECK-NEXT: mov z2.h, w0919; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0920; CHECK-NEXT: add z1.h, z1.h, z2.h921; CHECK-NEXT: mov z0.h, p0/m, z1.h922; CHECK-NEXT: ret923entry:924 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer925 %i = insertelement <vscale x 8 x i16> poison, i16 %y, i32 0926 %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer927 %a = add <vscale x 8 x i16> %x, %ys928 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z929 ret <vscale x 8 x i16> %b930}931 932define <vscale x 16 x i8> @addqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {933; CHECK-LABEL: addqr_v16i8:934; CHECK: // %bb.0: // %entry935; CHECK-NEXT: ptrue p0.b936; CHECK-NEXT: mov z2.b, w0937; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0938; CHECK-NEXT: add z1.b, z1.b, z2.b939; CHECK-NEXT: mov z0.b, p0/m, z1.b940; CHECK-NEXT: ret941entry:942 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer943 %i = insertelement <vscale x 16 x i8> poison, i8 %y, i32 0944 %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer945 %a = add <vscale x 16 x i8> %x, %ys946 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z947 ret <vscale x 16 x i8> %b948}949 950define <vscale x 4 x i32> @subqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {951; CHECK-LABEL: subqr_v4i32:952; CHECK: // %bb.0: // %entry953; CHECK-NEXT: ptrue p0.s954; CHECK-NEXT: mov z2.s, w0955; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0956; CHECK-NEXT: sub z1.s, z1.s, z2.s957; CHECK-NEXT: mov z0.s, p0/m, z1.s958; CHECK-NEXT: ret959entry:960 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer961 %i = insertelement <vscale x 4 x i32> poison, i32 %y, i32 0962 %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer963 %a = sub <vscale x 4 x i32> %x, %ys964 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z965 ret <vscale x 4 x i32> %b966}967 968define <vscale x 8 x i16> @subqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {969; CHECK-LABEL: subqr_v8i16:970; CHECK: // %bb.0: // %entry971; CHECK-NEXT: ptrue p0.h972; CHECK-NEXT: mov z2.h, w0973; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0974; CHECK-NEXT: sub z1.h, z1.h, z2.h975; CHECK-NEXT: mov z0.h, p0/m, z1.h976; CHECK-NEXT: ret977entry:978 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer979 %i = insertelement <vscale x 8 x i16> poison, i16 %y, i32 0980 %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer981 %a = sub <vscale x 8 x i16> %x, %ys982 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z983 ret <vscale x 8 x i16> %b984}985 986define <vscale x 16 x i8> @subqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {987; CHECK-LABEL: subqr_v16i8:988; CHECK: // %bb.0: // %entry989; CHECK-NEXT: ptrue p0.b990; CHECK-NEXT: mov z2.b, w0991; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0992; CHECK-NEXT: sub z1.b, z1.b, z2.b993; CHECK-NEXT: mov z0.b, p0/m, z1.b994; CHECK-NEXT: ret995entry:996 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer997 %i = insertelement <vscale x 16 x i8> poison, i8 %y, i32 0998 %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer999 %a = sub <vscale x 16 x i8> %x, %ys1000 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z1001 ret <vscale x 16 x i8> %b1002}1003 1004define <vscale x 4 x i32> @mulqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {1005; CHECK-LABEL: mulqr_v4i32:1006; CHECK: // %bb.0: // %entry1007; CHECK-NEXT: mov z2.s, w01008; CHECK-NEXT: ptrue p0.s1009; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #01010; CHECK-NEXT: mul z1.s, z1.s, z2.s1011; CHECK-NEXT: mov z0.s, p0/m, z1.s1012; CHECK-NEXT: ret1013entry:1014 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer1015 %i = insertelement <vscale x 4 x i32> poison, i32 %y, i32 01016 %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1017 %a = mul <vscale x 4 x i32> %x, %ys1018 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z1019 ret <vscale x 4 x i32> %b1020}1021 1022define <vscale x 8 x i16> @mulqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {1023; CHECK-LABEL: mulqr_v8i16:1024; CHECK: // %bb.0: // %entry1025; CHECK-NEXT: mov z2.h, w01026; CHECK-NEXT: ptrue p0.h1027; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #01028; CHECK-NEXT: mul z1.h, z1.h, z2.h1029; CHECK-NEXT: mov z0.h, p0/m, z1.h1030; CHECK-NEXT: ret1031entry:1032 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer1033 %i = insertelement <vscale x 8 x i16> poison, i16 %y, i32 01034 %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1035 %a = mul <vscale x 8 x i16> %x, %ys1036 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z1037 ret <vscale x 8 x i16> %b1038}1039 1040define <vscale x 16 x i8> @mulqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {1041; CHECK-LABEL: mulqr_v16i8:1042; CHECK: // %bb.0: // %entry1043; CHECK-NEXT: mov z2.b, w01044; CHECK-NEXT: ptrue p0.b1045; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #01046; CHECK-NEXT: mul z1.b, z1.b, z2.b1047; CHECK-NEXT: mov z0.b, p0/m, z1.b1048; CHECK-NEXT: ret1049entry:1050 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer1051 %i = insertelement <vscale x 16 x i8> poison, i8 %y, i32 01052 %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer1053 %a = mul <vscale x 16 x i8> %x, %ys1054 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z1055 ret <vscale x 16 x i8> %b1056}1057 1058define <vscale x 4 x float> @faddqr_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, float %y) {1059; CHECK-LABEL: faddqr_v4f32:1060; CHECK: // %bb.0: // %entry1061; CHECK-NEXT: // kill: def $s2 killed $s2 def $z21062; CHECK-NEXT: ptrue p0.s1063; CHECK-NEXT: mov z2.s, s21064; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.01065; CHECK-NEXT: fadd z1.s, z1.s, z2.s1066; CHECK-NEXT: mov z0.s, p0/m, z1.s1067; CHECK-NEXT: ret1068entry:1069 %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer1070 %i = insertelement <vscale x 4 x float> poison, float %y, i32 01071 %ys = shufflevector <vscale x 4 x float> %i, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer1072 %a = fadd <vscale x 4 x float> %x, %ys1073 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z1074 ret <vscale x 4 x float> %b1075}1076 1077define <vscale x 8 x half> @faddqr_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, half %y) {1078; CHECK-LABEL: faddqr_v8f16:1079; CHECK: // %bb.0: // %entry1080; CHECK-NEXT: // kill: def $h2 killed $h2 def $z21081; CHECK-NEXT: ptrue p0.h1082; CHECK-NEXT: mov z2.h, h21083; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.01084; CHECK-NEXT: fadd z1.h, z1.h, z2.h1085; CHECK-NEXT: mov z0.h, p0/m, z1.h1086; CHECK-NEXT: ret1087entry:1088 %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer1089 %i = insertelement <vscale x 8 x half> poison, half %y, i32 01090 %ys = shufflevector <vscale x 8 x half> %i, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer1091 %a = fadd <vscale x 8 x half> %x, %ys1092 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z1093 ret <vscale x 8 x half> %b1094}1095 1096define <vscale x 4 x float> @fsubqr_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, float %y) {1097; CHECK-LABEL: fsubqr_v4f32:1098; CHECK: // %bb.0: // %entry1099; CHECK-NEXT: // kill: def $s2 killed $s2 def $z21100; CHECK-NEXT: ptrue p0.s1101; CHECK-NEXT: mov z2.s, s21102; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.01103; CHECK-NEXT: fsub z1.s, z1.s, z2.s1104; CHECK-NEXT: mov z0.s, p0/m, z1.s1105; CHECK-NEXT: ret1106entry:1107 %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer1108 %i = insertelement <vscale x 4 x float> poison, float %y, i32 01109 %ys = shufflevector <vscale x 4 x float> %i, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer1110 %a = fsub <vscale x 4 x float> %x, %ys1111 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z1112 ret <vscale x 4 x float> %b1113}1114 1115define <vscale x 8 x half> @fsubqr_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, half %y) {1116; CHECK-LABEL: fsubqr_v8f16:1117; CHECK: // %bb.0: // %entry1118; CHECK-NEXT: // kill: def $h2 killed $h2 def $z21119; CHECK-NEXT: ptrue p0.h1120; CHECK-NEXT: mov z2.h, h21121; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.01122; CHECK-NEXT: fsub z1.h, z1.h, z2.h1123; CHECK-NEXT: mov z0.h, p0/m, z1.h1124; CHECK-NEXT: ret1125entry:1126 %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer1127 %i = insertelement <vscale x 8 x half> poison, half %y, i32 01128 %ys = shufflevector <vscale x 8 x half> %i, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer1129 %a = fsub <vscale x 8 x half> %x, %ys1130 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z1131 ret <vscale x 8 x half> %b1132}1133 1134define <vscale x 4 x float> @fmulqr_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, float %y) {1135; CHECK-LABEL: fmulqr_v4f32:1136; CHECK: // %bb.0: // %entry1137; CHECK-NEXT: // kill: def $s2 killed $s2 def $z21138; CHECK-NEXT: ptrue p0.s1139; CHECK-NEXT: mov z2.s, s21140; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.01141; CHECK-NEXT: fmul z1.s, z1.s, z2.s1142; CHECK-NEXT: mov z0.s, p0/m, z1.s1143; CHECK-NEXT: ret1144entry:1145 %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer1146 %i = insertelement <vscale x 4 x float> poison, float %y, i32 01147 %ys = shufflevector <vscale x 4 x float> %i, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer1148 %a = fmul <vscale x 4 x float> %x, %ys1149 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z1150 ret <vscale x 4 x float> %b1151}1152 1153define <vscale x 8 x half> @fmulqr_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, half %y) {1154; CHECK-LABEL: fmulqr_v8f16:1155; CHECK: // %bb.0: // %entry1156; CHECK-NEXT: // kill: def $h2 killed $h2 def $z21157; CHECK-NEXT: ptrue p0.h1158; CHECK-NEXT: mov z2.h, h21159; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.01160; CHECK-NEXT: fmul z1.h, z1.h, z2.h1161; CHECK-NEXT: mov z0.h, p0/m, z1.h1162; CHECK-NEXT: ret1163entry:1164 %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer1165 %i = insertelement <vscale x 8 x half> poison, half %y, i32 01166 %ys = shufflevector <vscale x 8 x half> %i, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer1167 %a = fmul <vscale x 8 x half> %x, %ys1168 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z1169 ret <vscale x 8 x half> %b1170}1171 1172define <vscale x 4 x i32> @sadd_satqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {1173; CHECK-LABEL: sadd_satqr_v4i32:1174; CHECK: // %bb.0: // %entry1175; CHECK-NEXT: mov z2.s, w01176; CHECK-NEXT: ptrue p0.s1177; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #01178; CHECK-NEXT: sqadd z1.s, z1.s, z2.s1179; CHECK-NEXT: mov z0.s, p0/m, z1.s1180; CHECK-NEXT: ret1181entry:1182 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer1183 %i = insertelement <vscale x 4 x i32> poison, i32 %y, i32 01184 %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1185 %a = call <vscale x 4 x i32> @llvm.sadd.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %ys)1186 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z1187 ret <vscale x 4 x i32> %b1188}1189 1190define <vscale x 8 x i16> @sadd_satqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {1191; CHECK-LABEL: sadd_satqr_v8i16:1192; CHECK: // %bb.0: // %entry1193; CHECK-NEXT: mov z2.h, w01194; CHECK-NEXT: ptrue p0.h1195; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #01196; CHECK-NEXT: sqadd z1.h, z1.h, z2.h1197; CHECK-NEXT: mov z0.h, p0/m, z1.h1198; CHECK-NEXT: ret1199entry:1200 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer1201 %i = insertelement <vscale x 8 x i16> poison, i16 %y, i32 01202 %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1203 %a = call <vscale x 8 x i16> @llvm.sadd.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %ys)1204 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z1205 ret <vscale x 8 x i16> %b1206}1207 1208define <vscale x 16 x i8> @sadd_satqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {1209; CHECK-LABEL: sadd_satqr_v16i8:1210; CHECK: // %bb.0: // %entry1211; CHECK-NEXT: mov z2.b, w01212; CHECK-NEXT: ptrue p0.b1213; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #01214; CHECK-NEXT: sqadd z1.b, z1.b, z2.b1215; CHECK-NEXT: mov z0.b, p0/m, z1.b1216; CHECK-NEXT: ret1217entry:1218 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer1219 %i = insertelement <vscale x 16 x i8> poison, i8 %y, i32 01220 %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer1221 %a = call <vscale x 16 x i8> @llvm.sadd.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %ys)1222 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z1223 ret <vscale x 16 x i8> %b1224}1225 1226define <vscale x 4 x i32> @uadd_satqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {1227; CHECK-LABEL: uadd_satqr_v4i32:1228; CHECK: // %bb.0: // %entry1229; CHECK-NEXT: mov z2.s, w01230; CHECK-NEXT: ptrue p0.s1231; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #01232; CHECK-NEXT: uqadd z1.s, z1.s, z2.s1233; CHECK-NEXT: mov z0.s, p0/m, z1.s1234; CHECK-NEXT: ret1235entry:1236 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer1237 %i = insertelement <vscale x 4 x i32> poison, i32 %y, i32 01238 %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1239 %a = call <vscale x 4 x i32> @llvm.uadd.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %ys)1240 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z1241 ret <vscale x 4 x i32> %b1242}1243 1244define <vscale x 8 x i16> @uadd_satqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {1245; CHECK-LABEL: uadd_satqr_v8i16:1246; CHECK: // %bb.0: // %entry1247; CHECK-NEXT: mov z2.h, w01248; CHECK-NEXT: ptrue p0.h1249; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #01250; CHECK-NEXT: uqadd z1.h, z1.h, z2.h1251; CHECK-NEXT: mov z0.h, p0/m, z1.h1252; CHECK-NEXT: ret1253entry:1254 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer1255 %i = insertelement <vscale x 8 x i16> poison, i16 %y, i32 01256 %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1257 %a = call <vscale x 8 x i16> @llvm.uadd.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %ys)1258 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z1259 ret <vscale x 8 x i16> %b1260}1261 1262define <vscale x 16 x i8> @uadd_satqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {1263; CHECK-LABEL: uadd_satqr_v16i8:1264; CHECK: // %bb.0: // %entry1265; CHECK-NEXT: mov z2.b, w01266; CHECK-NEXT: ptrue p0.b1267; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #01268; CHECK-NEXT: uqadd z1.b, z1.b, z2.b1269; CHECK-NEXT: mov z0.b, p0/m, z1.b1270; CHECK-NEXT: ret1271entry:1272 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer1273 %i = insertelement <vscale x 16 x i8> poison, i8 %y, i32 01274 %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer1275 %a = call <vscale x 16 x i8> @llvm.uadd.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %ys)1276 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z1277 ret <vscale x 16 x i8> %b1278}1279 1280define <vscale x 4 x i32> @ssub_satqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {1281; CHECK-LABEL: ssub_satqr_v4i32:1282; CHECK: // %bb.0: // %entry1283; CHECK-NEXT: mov z2.s, w01284; CHECK-NEXT: ptrue p0.s1285; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #01286; CHECK-NEXT: sqsub z1.s, z1.s, z2.s1287; CHECK-NEXT: mov z0.s, p0/m, z1.s1288; CHECK-NEXT: ret1289entry:1290 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer1291 %i = insertelement <vscale x 4 x i32> poison, i32 %y, i32 01292 %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1293 %a = call <vscale x 4 x i32> @llvm.ssub.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %ys)1294 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z1295 ret <vscale x 4 x i32> %b1296}1297 1298define <vscale x 8 x i16> @ssub_satqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {1299; CHECK-LABEL: ssub_satqr_v8i16:1300; CHECK: // %bb.0: // %entry1301; CHECK-NEXT: mov z2.h, w01302; CHECK-NEXT: ptrue p0.h1303; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #01304; CHECK-NEXT: sqsub z1.h, z1.h, z2.h1305; CHECK-NEXT: mov z0.h, p0/m, z1.h1306; CHECK-NEXT: ret1307entry:1308 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer1309 %i = insertelement <vscale x 8 x i16> poison, i16 %y, i32 01310 %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1311 %a = call <vscale x 8 x i16> @llvm.ssub.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %ys)1312 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z1313 ret <vscale x 8 x i16> %b1314}1315 1316define <vscale x 16 x i8> @ssub_satqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {1317; CHECK-LABEL: ssub_satqr_v16i8:1318; CHECK: // %bb.0: // %entry1319; CHECK-NEXT: mov z2.b, w01320; CHECK-NEXT: ptrue p0.b1321; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #01322; CHECK-NEXT: sqsub z1.b, z1.b, z2.b1323; CHECK-NEXT: mov z0.b, p0/m, z1.b1324; CHECK-NEXT: ret1325entry:1326 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer1327 %i = insertelement <vscale x 16 x i8> poison, i8 %y, i32 01328 %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer1329 %a = call <vscale x 16 x i8> @llvm.ssub.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %ys)1330 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z1331 ret <vscale x 16 x i8> %b1332}1333 1334define <vscale x 4 x i32> @usub_satqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {1335; CHECK-LABEL: usub_satqr_v4i32:1336; CHECK: // %bb.0: // %entry1337; CHECK-NEXT: mov z2.s, w01338; CHECK-NEXT: ptrue p0.s1339; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #01340; CHECK-NEXT: uqsub z1.s, z1.s, z2.s1341; CHECK-NEXT: mov z0.s, p0/m, z1.s1342; CHECK-NEXT: ret1343entry:1344 %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer1345 %i = insertelement <vscale x 4 x i32> poison, i32 %y, i32 01346 %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1347 %a = call <vscale x 4 x i32> @llvm.usub.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %ys)1348 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z1349 ret <vscale x 4 x i32> %b1350}1351 1352define <vscale x 8 x i16> @usub_satqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {1353; CHECK-LABEL: usub_satqr_v8i16:1354; CHECK: // %bb.0: // %entry1355; CHECK-NEXT: mov z2.h, w01356; CHECK-NEXT: ptrue p0.h1357; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #01358; CHECK-NEXT: uqsub z1.h, z1.h, z2.h1359; CHECK-NEXT: mov z0.h, p0/m, z1.h1360; CHECK-NEXT: ret1361entry:1362 %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer1363 %i = insertelement <vscale x 8 x i16> poison, i16 %y, i32 01364 %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer1365 %a = call <vscale x 8 x i16> @llvm.usub.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %ys)1366 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z1367 ret <vscale x 8 x i16> %b1368}1369 1370define <vscale x 16 x i8> @usub_satqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {1371; CHECK-LABEL: usub_satqr_v16i8:1372; CHECK: // %bb.0: // %entry1373; CHECK-NEXT: mov z2.b, w01374; CHECK-NEXT: ptrue p0.b1375; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #01376; CHECK-NEXT: uqsub z1.b, z1.b, z2.b1377; CHECK-NEXT: mov z0.b, p0/m, z1.b1378; CHECK-NEXT: ret1379entry:1380 %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer1381 %i = insertelement <vscale x 16 x i8> poison, i8 %y, i32 01382 %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer1383 %a = call <vscale x 16 x i8> @llvm.usub.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %ys)1384 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z1385 ret <vscale x 16 x i8> %b1386}1387 1388declare <vscale x 16 x i8> @llvm.sadd.sat.v16i8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2)1389declare <vscale x 8 x i16> @llvm.sadd.sat.v8i16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2)1390declare <vscale x 4 x i32> @llvm.sadd.sat.v4i32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2)1391declare <vscale x 16 x i8> @llvm.uadd.sat.v16i8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2)1392declare <vscale x 8 x i16> @llvm.uadd.sat.v8i16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2)1393declare <vscale x 4 x i32> @llvm.uadd.sat.v4i32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2)1394declare <vscale x 16 x i8> @llvm.ssub.sat.v16i8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2)1395declare <vscale x 8 x i16> @llvm.ssub.sat.v8i16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2)1396declare <vscale x 4 x i32> @llvm.ssub.sat.v4i32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2)1397declare <vscale x 16 x i8> @llvm.usub.sat.v16i8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2)1398declare <vscale x 8 x i16> @llvm.usub.sat.v8i16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2)1399declare <vscale x 4 x i32> @llvm.usub.sat.v4i32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2)1400