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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64 -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s3 4define <vscale x 2 x i64> @add_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {5; CHECK-LABEL: add_nxv2i64_x:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: ptrue p0.d8; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #09; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d10; CHECK-NEXT: ret11entry:12 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer13 %a = add <vscale x 2 x i64> %x, %y14 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x15 ret <vscale x 2 x i64> %b16}17 18define <vscale x 4 x i32> @add_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {19; CHECK-LABEL: add_nxv4i32_x:20; CHECK: // %bb.0: // %entry21; CHECK-NEXT: ptrue p0.s22; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #023; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s24; CHECK-NEXT: ret25entry:26 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer27 %a = add <vscale x 4 x i32> %x, %y28 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x29 ret <vscale x 4 x i32> %b30}31 32define <vscale x 8 x i16> @add_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {33; CHECK-LABEL: add_nxv8i16_x:34; CHECK: // %bb.0: // %entry35; CHECK-NEXT: ptrue p0.h36; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #037; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h38; CHECK-NEXT: ret39entry:40 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer41 %a = add <vscale x 8 x i16> %x, %y42 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x43 ret <vscale x 8 x i16> %b44}45 46define <vscale x 16 x i8> @add_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {47; CHECK-LABEL: add_nxv16i8_x:48; CHECK: // %bb.0: // %entry49; CHECK-NEXT: ptrue p0.b50; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #051; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b52; CHECK-NEXT: ret53entry:54 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer55 %a = add <vscale x 16 x i8> %x, %y56 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x57 ret <vscale x 16 x i8> %b58}59 60define <vscale x 2 x i64> @sub_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {61; CHECK-LABEL: sub_nxv2i64_x:62; CHECK: // %bb.0: // %entry63; CHECK-NEXT: ptrue p0.d64; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #065; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d66; CHECK-NEXT: ret67entry:68 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer69 %a = sub <vscale x 2 x i64> %x, %y70 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x71 ret <vscale x 2 x i64> %b72}73 74define <vscale x 4 x i32> @sub_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {75; CHECK-LABEL: sub_nxv4i32_x:76; CHECK: // %bb.0: // %entry77; CHECK-NEXT: ptrue p0.s78; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #079; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s80; CHECK-NEXT: ret81entry:82 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer83 %a = sub <vscale x 4 x i32> %x, %y84 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x85 ret <vscale x 4 x i32> %b86}87 88define <vscale x 8 x i16> @sub_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {89; CHECK-LABEL: sub_nxv8i16_x:90; CHECK: // %bb.0: // %entry91; CHECK-NEXT: ptrue p0.h92; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #093; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h94; CHECK-NEXT: ret95entry:96 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer97 %a = sub <vscale x 8 x i16> %x, %y98 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x99 ret <vscale x 8 x i16> %b100}101 102define <vscale x 16 x i8> @sub_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {103; CHECK-LABEL: sub_nxv16i8_x:104; CHECK: // %bb.0: // %entry105; CHECK-NEXT: ptrue p0.b106; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0107; CHECK-NEXT: sub z0.b, p0/m, z0.b, z1.b108; CHECK-NEXT: ret109entry:110 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer111 %a = sub <vscale x 16 x i8> %x, %y112 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x113 ret <vscale x 16 x i8> %b114}115 116define <vscale x 2 x i64> @mul_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {117; CHECK-LABEL: mul_nxv2i64_x:118; CHECK: // %bb.0: // %entry119; CHECK-NEXT: ptrue p0.d120; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0121; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d122; CHECK-NEXT: ret123entry:124 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer125 %a = mul <vscale x 2 x i64> %x, %y126 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x127 ret <vscale x 2 x i64> %b128}129 130define <vscale x 4 x i32> @mul_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {131; CHECK-LABEL: mul_nxv4i32_x:132; CHECK: // %bb.0: // %entry133; CHECK-NEXT: ptrue p0.s134; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0135; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s136; CHECK-NEXT: ret137entry:138 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer139 %a = mul <vscale x 4 x i32> %x, %y140 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x141 ret <vscale x 4 x i32> %b142}143 144define <vscale x 8 x i16> @mul_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {145; CHECK-LABEL: mul_nxv8i16_x:146; CHECK: // %bb.0: // %entry147; CHECK-NEXT: ptrue p0.h148; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0149; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h150; CHECK-NEXT: ret151entry:152 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer153 %a = mul <vscale x 8 x i16> %x, %y154 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x155 ret <vscale x 8 x i16> %b156}157 158define <vscale x 16 x i8> @mul_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {159; CHECK-LABEL: mul_nxv16i8_x:160; CHECK: // %bb.0: // %entry161; CHECK-NEXT: ptrue p0.b162; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0163; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b164; CHECK-NEXT: ret165entry:166 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer167 %a = mul <vscale x 16 x i8> %x, %y168 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x169 ret <vscale x 16 x i8> %b170}171 172define <vscale x 2 x i64> @sdiv_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {173; CHECK-LABEL: sdiv_nxv2i64_x:174; CHECK: // %bb.0: // %entry175; CHECK-NEXT: ptrue p0.d176; CHECK-NEXT: sdivr z1.d, p0/m, z1.d, z0.d177; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0178; CHECK-NEXT: mov z0.d, p0/m, z1.d179; CHECK-NEXT: ret180entry:181 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer182 %a = sdiv <vscale x 2 x i64> %x, %y183 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x184 ret <vscale x 2 x i64> %b185}186 187define <vscale x 4 x i32> @sdiv_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {188; CHECK-LABEL: sdiv_nxv4i32_x:189; CHECK: // %bb.0: // %entry190; CHECK-NEXT: ptrue p0.s191; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z0.s192; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0193; CHECK-NEXT: mov z0.s, p0/m, z1.s194; CHECK-NEXT: ret195entry:196 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer197 %a = sdiv <vscale x 4 x i32> %x, %y198 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x199 ret <vscale x 4 x i32> %b200}201 202define <vscale x 8 x i16> @sdiv_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {203; CHECK-LABEL: sdiv_nxv8i16_x:204; CHECK: // %bb.0: // %entry205; CHECK-NEXT: sunpkhi z3.s, z1.h206; CHECK-NEXT: sunpkhi z4.s, z0.h207; CHECK-NEXT: ptrue p0.s208; CHECK-NEXT: sunpklo z1.s, z1.h209; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s210; CHECK-NEXT: sunpklo z4.s, z0.h211; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z4.s212; CHECK-NEXT: ptrue p0.h213; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0214; CHECK-NEXT: uzp1 z1.h, z1.h, z3.h215; CHECK-NEXT: mov z0.h, p0/m, z1.h216; CHECK-NEXT: ret217entry:218 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer219 %a = sdiv <vscale x 8 x i16> %x, %y220 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x221 ret <vscale x 8 x i16> %b222}223 224define <vscale x 16 x i8> @sdiv_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {225; CHECK-LABEL: sdiv_nxv16i8_x:226; CHECK: // %bb.0: // %entry227; CHECK-NEXT: sunpkhi z3.h, z1.b228; CHECK-NEXT: sunpkhi z4.h, z0.b229; CHECK-NEXT: ptrue p0.s230; CHECK-NEXT: sunpklo z1.h, z1.b231; CHECK-NEXT: sunpkhi z5.s, z3.h232; CHECK-NEXT: sunpkhi z6.s, z4.h233; CHECK-NEXT: sunpklo z3.s, z3.h234; CHECK-NEXT: sunpklo z4.s, z4.h235; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s236; CHECK-NEXT: sunpkhi z6.s, z1.h237; CHECK-NEXT: sunpklo z1.s, z1.h238; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s239; CHECK-NEXT: sunpklo z4.h, z0.b240; CHECK-NEXT: sunpkhi z7.s, z4.h241; CHECK-NEXT: sunpklo z4.s, z4.h242; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s243; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h244; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z4.s245; CHECK-NEXT: ptrue p0.b246; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0247; CHECK-NEXT: uzp1 z1.h, z1.h, z6.h248; CHECK-NEXT: uzp1 z1.b, z1.b, z3.b249; CHECK-NEXT: mov z0.b, p0/m, z1.b250; CHECK-NEXT: ret251entry:252 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer253 %a = sdiv <vscale x 16 x i8> %x, %y254 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x255 ret <vscale x 16 x i8> %b256}257 258define <vscale x 2 x i64> @udiv_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {259; CHECK-LABEL: udiv_nxv2i64_x:260; CHECK: // %bb.0: // %entry261; CHECK-NEXT: ptrue p0.d262; CHECK-NEXT: udivr z1.d, p0/m, z1.d, z0.d263; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0264; CHECK-NEXT: mov z0.d, p0/m, z1.d265; CHECK-NEXT: ret266entry:267 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer268 %a = udiv <vscale x 2 x i64> %x, %y269 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x270 ret <vscale x 2 x i64> %b271}272 273define <vscale x 4 x i32> @udiv_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {274; CHECK-LABEL: udiv_nxv4i32_x:275; CHECK: // %bb.0: // %entry276; CHECK-NEXT: ptrue p0.s277; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z0.s278; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0279; CHECK-NEXT: mov z0.s, p0/m, z1.s280; CHECK-NEXT: ret281entry:282 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer283 %a = udiv <vscale x 4 x i32> %x, %y284 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x285 ret <vscale x 4 x i32> %b286}287 288define <vscale x 8 x i16> @udiv_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {289; CHECK-LABEL: udiv_nxv8i16_x:290; CHECK: // %bb.0: // %entry291; CHECK-NEXT: uunpkhi z3.s, z1.h292; CHECK-NEXT: uunpkhi z4.s, z0.h293; CHECK-NEXT: ptrue p0.s294; CHECK-NEXT: uunpklo z1.s, z1.h295; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s296; CHECK-NEXT: uunpklo z4.s, z0.h297; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z4.s298; CHECK-NEXT: ptrue p0.h299; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0300; CHECK-NEXT: uzp1 z1.h, z1.h, z3.h301; CHECK-NEXT: mov z0.h, p0/m, z1.h302; CHECK-NEXT: ret303entry:304 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer305 %a = udiv <vscale x 8 x i16> %x, %y306 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x307 ret <vscale x 8 x i16> %b308}309 310define <vscale x 16 x i8> @udiv_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {311; CHECK-LABEL: udiv_nxv16i8_x:312; CHECK: // %bb.0: // %entry313; CHECK-NEXT: uunpkhi z3.h, z1.b314; CHECK-NEXT: uunpkhi z4.h, z0.b315; CHECK-NEXT: ptrue p0.s316; CHECK-NEXT: uunpklo z1.h, z1.b317; CHECK-NEXT: uunpkhi z5.s, z3.h318; CHECK-NEXT: uunpkhi z6.s, z4.h319; CHECK-NEXT: uunpklo z3.s, z3.h320; CHECK-NEXT: uunpklo z4.s, z4.h321; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s322; CHECK-NEXT: uunpkhi z6.s, z1.h323; CHECK-NEXT: uunpklo z1.s, z1.h324; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s325; CHECK-NEXT: uunpklo z4.h, z0.b326; CHECK-NEXT: uunpkhi z7.s, z4.h327; CHECK-NEXT: uunpklo z4.s, z4.h328; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s329; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h330; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z4.s331; CHECK-NEXT: ptrue p0.b332; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0333; CHECK-NEXT: uzp1 z1.h, z1.h, z6.h334; CHECK-NEXT: uzp1 z1.b, z1.b, z3.b335; CHECK-NEXT: mov z0.b, p0/m, z1.b336; CHECK-NEXT: ret337entry:338 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer339 %a = udiv <vscale x 16 x i8> %x, %y340 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x341 ret <vscale x 16 x i8> %b342}343 344define <vscale x 2 x i64> @srem_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {345; CHECK-LABEL: srem_nxv2i64_x:346; CHECK: // %bb.0: // %entry347; CHECK-NEXT: ptrue p0.d348; CHECK-NEXT: movprfx z3, z0349; CHECK-NEXT: sdiv z3.d, p0/m, z3.d, z1.d350; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0351; CHECK-NEXT: mls z0.d, p0/m, z3.d, z1.d352; CHECK-NEXT: ret353entry:354 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer355 %a = srem <vscale x 2 x i64> %x, %y356 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x357 ret <vscale x 2 x i64> %b358}359 360define <vscale x 4 x i32> @srem_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {361; CHECK-LABEL: srem_nxv4i32_x:362; CHECK: // %bb.0: // %entry363; CHECK-NEXT: ptrue p0.s364; CHECK-NEXT: movprfx z3, z0365; CHECK-NEXT: sdiv z3.s, p0/m, z3.s, z1.s366; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0367; CHECK-NEXT: mls z0.s, p0/m, z3.s, z1.s368; CHECK-NEXT: ret369entry:370 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer371 %a = srem <vscale x 4 x i32> %x, %y372 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x373 ret <vscale x 4 x i32> %b374}375 376define <vscale x 8 x i16> @srem_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {377; CHECK-LABEL: srem_nxv8i16_x:378; CHECK: // %bb.0: // %entry379; CHECK-NEXT: sunpkhi z3.s, z1.h380; CHECK-NEXT: sunpkhi z4.s, z0.h381; CHECK-NEXT: ptrue p0.s382; CHECK-NEXT: sunpklo z5.s, z0.h383; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s384; CHECK-NEXT: sunpklo z4.s, z1.h385; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s386; CHECK-NEXT: ptrue p0.h387; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0388; CHECK-NEXT: uzp1 z2.h, z4.h, z3.h389; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h390; CHECK-NEXT: ret391entry:392 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer393 %a = srem <vscale x 8 x i16> %x, %y394 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x395 ret <vscale x 8 x i16> %b396}397 398define <vscale x 16 x i8> @srem_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {399; CHECK-LABEL: srem_nxv16i8_x:400; CHECK: // %bb.0: // %entry401; CHECK-NEXT: sunpkhi z3.h, z1.b402; CHECK-NEXT: sunpkhi z4.h, z0.b403; CHECK-NEXT: ptrue p0.s404; CHECK-NEXT: sunpkhi z5.s, z3.h405; CHECK-NEXT: sunpkhi z6.s, z4.h406; CHECK-NEXT: sunpklo z3.s, z3.h407; CHECK-NEXT: sunpklo z4.s, z4.h408; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s409; CHECK-NEXT: sunpklo z6.h, z0.b410; CHECK-NEXT: sunpkhi z24.s, z6.h411; CHECK-NEXT: sunpklo z6.s, z6.h412; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s413; CHECK-NEXT: sunpklo z4.h, z1.b414; CHECK-NEXT: sunpkhi z7.s, z4.h415; CHECK-NEXT: sunpklo z4.s, z4.h416; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z24.s417; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h418; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z6.s419; CHECK-NEXT: ptrue p0.b420; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0421; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h422; CHECK-NEXT: uzp1 z2.b, z4.b, z3.b423; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b424; CHECK-NEXT: ret425entry:426 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer427 %a = srem <vscale x 16 x i8> %x, %y428 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x429 ret <vscale x 16 x i8> %b430}431 432define <vscale x 2 x i64> @urem_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {433; CHECK-LABEL: urem_nxv2i64_x:434; CHECK: // %bb.0: // %entry435; CHECK-NEXT: ptrue p0.d436; CHECK-NEXT: movprfx z3, z0437; CHECK-NEXT: udiv z3.d, p0/m, z3.d, z1.d438; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0439; CHECK-NEXT: mls z0.d, p0/m, z3.d, z1.d440; CHECK-NEXT: ret441entry:442 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer443 %a = urem <vscale x 2 x i64> %x, %y444 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x445 ret <vscale x 2 x i64> %b446}447 448define <vscale x 4 x i32> @urem_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {449; CHECK-LABEL: urem_nxv4i32_x:450; CHECK: // %bb.0: // %entry451; CHECK-NEXT: ptrue p0.s452; CHECK-NEXT: movprfx z3, z0453; CHECK-NEXT: udiv z3.s, p0/m, z3.s, z1.s454; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0455; CHECK-NEXT: mls z0.s, p0/m, z3.s, z1.s456; CHECK-NEXT: ret457entry:458 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer459 %a = urem <vscale x 4 x i32> %x, %y460 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x461 ret <vscale x 4 x i32> %b462}463 464define <vscale x 8 x i16> @urem_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {465; CHECK-LABEL: urem_nxv8i16_x:466; CHECK: // %bb.0: // %entry467; CHECK-NEXT: uunpkhi z3.s, z1.h468; CHECK-NEXT: uunpkhi z4.s, z0.h469; CHECK-NEXT: ptrue p0.s470; CHECK-NEXT: uunpklo z5.s, z0.h471; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s472; CHECK-NEXT: uunpklo z4.s, z1.h473; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s474; CHECK-NEXT: ptrue p0.h475; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0476; CHECK-NEXT: uzp1 z2.h, z4.h, z3.h477; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h478; CHECK-NEXT: ret479entry:480 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer481 %a = urem <vscale x 8 x i16> %x, %y482 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x483 ret <vscale x 8 x i16> %b484}485 486define <vscale x 16 x i8> @urem_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {487; CHECK-LABEL: urem_nxv16i8_x:488; CHECK: // %bb.0: // %entry489; CHECK-NEXT: uunpkhi z3.h, z1.b490; CHECK-NEXT: uunpkhi z4.h, z0.b491; CHECK-NEXT: ptrue p0.s492; CHECK-NEXT: uunpkhi z5.s, z3.h493; CHECK-NEXT: uunpkhi z6.s, z4.h494; CHECK-NEXT: uunpklo z3.s, z3.h495; CHECK-NEXT: uunpklo z4.s, z4.h496; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s497; CHECK-NEXT: uunpklo z6.h, z0.b498; CHECK-NEXT: uunpkhi z24.s, z6.h499; CHECK-NEXT: uunpklo z6.s, z6.h500; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s501; CHECK-NEXT: uunpklo z4.h, z1.b502; CHECK-NEXT: uunpkhi z7.s, z4.h503; CHECK-NEXT: uunpklo z4.s, z4.h504; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z24.s505; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h506; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z6.s507; CHECK-NEXT: ptrue p0.b508; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0509; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h510; CHECK-NEXT: uzp1 z2.b, z4.b, z3.b511; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b512; CHECK-NEXT: ret513entry:514 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer515 %a = urem <vscale x 16 x i8> %x, %y516 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x517 ret <vscale x 16 x i8> %b518}519 520define <vscale x 2 x i64> @and_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {521; CHECK-LABEL: and_nxv2i64_x:522; CHECK: // %bb.0: // %entry523; CHECK-NEXT: ptrue p0.d524; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0525; CHECK-NEXT: and z0.d, p0/m, z0.d, z1.d526; CHECK-NEXT: ret527entry:528 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer529 %a = and <vscale x 2 x i64> %x, %y530 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x531 ret <vscale x 2 x i64> %b532}533 534define <vscale x 4 x i32> @and_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {535; CHECK-LABEL: and_nxv4i32_x:536; CHECK: // %bb.0: // %entry537; CHECK-NEXT: ptrue p0.s538; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0539; CHECK-NEXT: and z0.s, p0/m, z0.s, z1.s540; CHECK-NEXT: ret541entry:542 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer543 %a = and <vscale x 4 x i32> %x, %y544 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x545 ret <vscale x 4 x i32> %b546}547 548define <vscale x 8 x i16> @and_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {549; CHECK-LABEL: and_nxv8i16_x:550; CHECK: // %bb.0: // %entry551; CHECK-NEXT: ptrue p0.h552; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0553; CHECK-NEXT: and z0.h, p0/m, z0.h, z1.h554; CHECK-NEXT: ret555entry:556 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer557 %a = and <vscale x 8 x i16> %x, %y558 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x559 ret <vscale x 8 x i16> %b560}561 562define <vscale x 16 x i8> @and_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {563; CHECK-LABEL: and_nxv16i8_x:564; CHECK: // %bb.0: // %entry565; CHECK-NEXT: ptrue p0.b566; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0567; CHECK-NEXT: and z0.b, p0/m, z0.b, z1.b568; CHECK-NEXT: ret569entry:570 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer571 %a = and <vscale x 16 x i8> %x, %y572 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x573 ret <vscale x 16 x i8> %b574}575 576define <vscale x 2 x i64> @or_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {577; CHECK-LABEL: or_nxv2i64_x:578; CHECK: // %bb.0: // %entry579; CHECK-NEXT: ptrue p0.d580; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0581; CHECK-NEXT: orr z0.d, p0/m, z0.d, z1.d582; CHECK-NEXT: ret583entry:584 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer585 %a = or <vscale x 2 x i64> %x, %y586 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x587 ret <vscale x 2 x i64> %b588}589 590define <vscale x 4 x i32> @or_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {591; CHECK-LABEL: or_nxv4i32_x:592; CHECK: // %bb.0: // %entry593; CHECK-NEXT: ptrue p0.s594; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0595; CHECK-NEXT: orr z0.s, p0/m, z0.s, z1.s596; CHECK-NEXT: ret597entry:598 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer599 %a = or <vscale x 4 x i32> %x, %y600 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x601 ret <vscale x 4 x i32> %b602}603 604define <vscale x 8 x i16> @or_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {605; CHECK-LABEL: or_nxv8i16_x:606; CHECK: // %bb.0: // %entry607; CHECK-NEXT: ptrue p0.h608; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0609; CHECK-NEXT: orr z0.h, p0/m, z0.h, z1.h610; CHECK-NEXT: ret611entry:612 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer613 %a = or <vscale x 8 x i16> %x, %y614 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x615 ret <vscale x 8 x i16> %b616}617 618define <vscale x 16 x i8> @or_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {619; CHECK-LABEL: or_nxv16i8_x:620; CHECK: // %bb.0: // %entry621; CHECK-NEXT: ptrue p0.b622; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0623; CHECK-NEXT: orr z0.b, p0/m, z0.b, z1.b624; CHECK-NEXT: ret625entry:626 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer627 %a = or <vscale x 16 x i8> %x, %y628 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x629 ret <vscale x 16 x i8> %b630}631 632define <vscale x 2 x i64> @xor_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {633; CHECK-LABEL: xor_nxv2i64_x:634; CHECK: // %bb.0: // %entry635; CHECK-NEXT: ptrue p0.d636; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0637; CHECK-NEXT: eor z0.d, p0/m, z0.d, z1.d638; CHECK-NEXT: ret639entry:640 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer641 %a = xor <vscale x 2 x i64> %x, %y642 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x643 ret <vscale x 2 x i64> %b644}645 646define <vscale x 4 x i32> @xor_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {647; CHECK-LABEL: xor_nxv4i32_x:648; CHECK: // %bb.0: // %entry649; CHECK-NEXT: ptrue p0.s650; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0651; CHECK-NEXT: eor z0.s, p0/m, z0.s, z1.s652; CHECK-NEXT: ret653entry:654 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer655 %a = xor <vscale x 4 x i32> %x, %y656 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x657 ret <vscale x 4 x i32> %b658}659 660define <vscale x 8 x i16> @xor_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {661; CHECK-LABEL: xor_nxv8i16_x:662; CHECK: // %bb.0: // %entry663; CHECK-NEXT: ptrue p0.h664; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0665; CHECK-NEXT: eor z0.h, p0/m, z0.h, z1.h666; CHECK-NEXT: ret667entry:668 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer669 %a = xor <vscale x 8 x i16> %x, %y670 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x671 ret <vscale x 8 x i16> %b672}673 674define <vscale x 16 x i8> @xor_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {675; CHECK-LABEL: xor_nxv16i8_x:676; CHECK: // %bb.0: // %entry677; CHECK-NEXT: ptrue p0.b678; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0679; CHECK-NEXT: eor z0.b, p0/m, z0.b, z1.b680; CHECK-NEXT: ret681entry:682 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer683 %a = xor <vscale x 16 x i8> %x, %y684 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x685 ret <vscale x 16 x i8> %b686}687 688define <vscale x 2 x i64> @shl_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {689; CHECK-LABEL: shl_nxv2i64_x:690; CHECK: // %bb.0: // %entry691; CHECK-NEXT: ptrue p0.d692; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0693; CHECK-NEXT: lslr z1.d, p0/m, z1.d, z0.d694; CHECK-NEXT: mov z0.d, p1/m, z1.d695; CHECK-NEXT: ret696entry:697 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer698 %a = shl <vscale x 2 x i64> %x, %y699 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x700 ret <vscale x 2 x i64> %b701}702 703define <vscale x 4 x i32> @shl_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {704; CHECK-LABEL: shl_nxv4i32_x:705; CHECK: // %bb.0: // %entry706; CHECK-NEXT: ptrue p0.s707; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0708; CHECK-NEXT: lslr z1.s, p0/m, z1.s, z0.s709; CHECK-NEXT: mov z0.s, p1/m, z1.s710; CHECK-NEXT: ret711entry:712 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer713 %a = shl <vscale x 4 x i32> %x, %y714 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x715 ret <vscale x 4 x i32> %b716}717 718define <vscale x 8 x i16> @shl_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {719; CHECK-LABEL: shl_nxv8i16_x:720; CHECK: // %bb.0: // %entry721; CHECK-NEXT: ptrue p0.h722; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0723; CHECK-NEXT: lslr z1.h, p0/m, z1.h, z0.h724; CHECK-NEXT: mov z0.h, p1/m, z1.h725; CHECK-NEXT: ret726entry:727 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer728 %a = shl <vscale x 8 x i16> %x, %y729 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x730 ret <vscale x 8 x i16> %b731}732 733define <vscale x 16 x i8> @shl_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {734; CHECK-LABEL: shl_nxv16i8_x:735; CHECK: // %bb.0: // %entry736; CHECK-NEXT: ptrue p0.b737; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0738; CHECK-NEXT: lslr z1.b, p0/m, z1.b, z0.b739; CHECK-NEXT: mov z0.b, p1/m, z1.b740; CHECK-NEXT: ret741entry:742 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer743 %a = shl <vscale x 16 x i8> %x, %y744 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x745 ret <vscale x 16 x i8> %b746}747 748define <vscale x 2 x i64> @ashr_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {749; CHECK-LABEL: ashr_nxv2i64_x:750; CHECK: // %bb.0: // %entry751; CHECK-NEXT: ptrue p0.d752; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0753; CHECK-NEXT: asrr z1.d, p0/m, z1.d, z0.d754; CHECK-NEXT: mov z0.d, p1/m, z1.d755; CHECK-NEXT: ret756entry:757 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer758 %a = ashr <vscale x 2 x i64> %x, %y759 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x760 ret <vscale x 2 x i64> %b761}762 763define <vscale x 4 x i32> @ashr_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {764; CHECK-LABEL: ashr_nxv4i32_x:765; CHECK: // %bb.0: // %entry766; CHECK-NEXT: ptrue p0.s767; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0768; CHECK-NEXT: asrr z1.s, p0/m, z1.s, z0.s769; CHECK-NEXT: mov z0.s, p1/m, z1.s770; CHECK-NEXT: ret771entry:772 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer773 %a = ashr <vscale x 4 x i32> %x, %y774 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x775 ret <vscale x 4 x i32> %b776}777 778define <vscale x 8 x i16> @ashr_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {779; CHECK-LABEL: ashr_nxv8i16_x:780; CHECK: // %bb.0: // %entry781; CHECK-NEXT: ptrue p0.h782; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0783; CHECK-NEXT: asrr z1.h, p0/m, z1.h, z0.h784; CHECK-NEXT: mov z0.h, p1/m, z1.h785; CHECK-NEXT: ret786entry:787 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer788 %a = ashr <vscale x 8 x i16> %x, %y789 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x790 ret <vscale x 8 x i16> %b791}792 793define <vscale x 16 x i8> @ashr_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {794; CHECK-LABEL: ashr_nxv16i8_x:795; CHECK: // %bb.0: // %entry796; CHECK-NEXT: ptrue p0.b797; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0798; CHECK-NEXT: asrr z1.b, p0/m, z1.b, z0.b799; CHECK-NEXT: mov z0.b, p1/m, z1.b800; CHECK-NEXT: ret801entry:802 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer803 %a = ashr <vscale x 16 x i8> %x, %y804 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x805 ret <vscale x 16 x i8> %b806}807 808define <vscale x 2 x i64> @lshr_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {809; CHECK-LABEL: lshr_nxv2i64_x:810; CHECK: // %bb.0: // %entry811; CHECK-NEXT: ptrue p0.d812; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0813; CHECK-NEXT: lsrr z1.d, p0/m, z1.d, z0.d814; CHECK-NEXT: mov z0.d, p1/m, z1.d815; CHECK-NEXT: ret816entry:817 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer818 %a = lshr <vscale x 2 x i64> %x, %y819 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x820 ret <vscale x 2 x i64> %b821}822 823define <vscale x 4 x i32> @lshr_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {824; CHECK-LABEL: lshr_nxv4i32_x:825; CHECK: // %bb.0: // %entry826; CHECK-NEXT: ptrue p0.s827; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0828; CHECK-NEXT: lsrr z1.s, p0/m, z1.s, z0.s829; CHECK-NEXT: mov z0.s, p1/m, z1.s830; CHECK-NEXT: ret831entry:832 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer833 %a = lshr <vscale x 4 x i32> %x, %y834 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x835 ret <vscale x 4 x i32> %b836}837 838define <vscale x 8 x i16> @lshr_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {839; CHECK-LABEL: lshr_nxv8i16_x:840; CHECK: // %bb.0: // %entry841; CHECK-NEXT: ptrue p0.h842; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0843; CHECK-NEXT: lsrr z1.h, p0/m, z1.h, z0.h844; CHECK-NEXT: mov z0.h, p1/m, z1.h845; CHECK-NEXT: ret846entry:847 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer848 %a = lshr <vscale x 8 x i16> %x, %y849 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x850 ret <vscale x 8 x i16> %b851}852 853define <vscale x 16 x i8> @lshr_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {854; CHECK-LABEL: lshr_nxv16i8_x:855; CHECK: // %bb.0: // %entry856; CHECK-NEXT: ptrue p0.b857; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0858; CHECK-NEXT: lsrr z1.b, p0/m, z1.b, z0.b859; CHECK-NEXT: mov z0.b, p1/m, z1.b860; CHECK-NEXT: ret861entry:862 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer863 %a = lshr <vscale x 16 x i8> %x, %y864 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x865 ret <vscale x 16 x i8> %b866}867 868define <vscale x 2 x i64> @mla_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {869; CHECK-LABEL: mla_nxv2i64_x:870; CHECK: // %bb.0: // %entry871; CHECK-NEXT: ptrue p0.d872; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, #0873; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d874; CHECK-NEXT: ret875entry:876 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer877 %m = mul <vscale x 2 x i64> %y, %z878 %a = add <vscale x 2 x i64> %x, %m879 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x880 ret <vscale x 2 x i64> %b881}882 883define <vscale x 4 x i32> @mla_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {884; CHECK-LABEL: mla_nxv4i32_x:885; CHECK: // %bb.0: // %entry886; CHECK-NEXT: ptrue p0.s887; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, #0888; CHECK-NEXT: mla z0.s, p0/m, z1.s, z2.s889; CHECK-NEXT: ret890entry:891 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer892 %m = mul <vscale x 4 x i32> %y, %z893 %a = add <vscale x 4 x i32> %x, %m894 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x895 ret <vscale x 4 x i32> %b896}897 898define <vscale x 8 x i16> @mla_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {899; CHECK-LABEL: mla_nxv8i16_x:900; CHECK: // %bb.0: // %entry901; CHECK-NEXT: ptrue p0.h902; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, #0903; CHECK-NEXT: mla z0.h, p0/m, z1.h, z2.h904; CHECK-NEXT: ret905entry:906 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer907 %m = mul <vscale x 8 x i16> %y, %z908 %a = add <vscale x 8 x i16> %x, %m909 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x910 ret <vscale x 8 x i16> %b911}912 913define <vscale x 16 x i8> @mla_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {914; CHECK-LABEL: mla_nxv16i8_x:915; CHECK: // %bb.0: // %entry916; CHECK-NEXT: ptrue p0.b917; CHECK-NEXT: cmpgt p0.b, p0/z, z3.b, #0918; CHECK-NEXT: mla z0.b, p0/m, z1.b, z2.b919; CHECK-NEXT: ret920entry:921 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer922 %m = mul <vscale x 16 x i8> %y, %z923 %a = add <vscale x 16 x i8> %x, %m924 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x925 ret <vscale x 16 x i8> %b926}927 928define <vscale x 2 x i64> @mls_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {929; CHECK-LABEL: mls_nxv2i64_x:930; CHECK: // %bb.0: // %entry931; CHECK-NEXT: ptrue p0.d932; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, #0933; CHECK-NEXT: msb z0.d, p0/m, z1.d, z2.d934; CHECK-NEXT: ret935entry:936 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer937 %m = mul <vscale x 2 x i64> %x, %y938 %a = sub <vscale x 2 x i64> %z, %m939 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x940 ret <vscale x 2 x i64> %b941}942 943define <vscale x 4 x i32> @mls_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {944; CHECK-LABEL: mls_nxv4i32_x:945; CHECK: // %bb.0: // %entry946; CHECK-NEXT: ptrue p0.s947; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, #0948; CHECK-NEXT: msb z0.s, p0/m, z1.s, z2.s949; CHECK-NEXT: ret950entry:951 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer952 %m = mul <vscale x 4 x i32> %x, %y953 %a = sub <vscale x 4 x i32> %z, %m954 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x955 ret <vscale x 4 x i32> %b956}957 958define <vscale x 8 x i16> @mls_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {959; CHECK-LABEL: mls_nxv8i16_x:960; CHECK: // %bb.0: // %entry961; CHECK-NEXT: ptrue p0.h962; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, #0963; CHECK-NEXT: msb z0.h, p0/m, z1.h, z2.h964; CHECK-NEXT: ret965entry:966 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer967 %m = mul <vscale x 8 x i16> %x, %y968 %a = sub <vscale x 8 x i16> %z, %m969 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x970 ret <vscale x 8 x i16> %b971}972 973define <vscale x 16 x i8> @mls_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {974; CHECK-LABEL: mls_nxv16i8_x:975; CHECK: // %bb.0: // %entry976; CHECK-NEXT: ptrue p0.b977; CHECK-NEXT: cmpgt p0.b, p0/z, z3.b, #0978; CHECK-NEXT: msb z0.b, p0/m, z1.b, z2.b979; CHECK-NEXT: ret980entry:981 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer982 %m = mul <vscale x 16 x i8> %x, %y983 %a = sub <vscale x 16 x i8> %z, %m984 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x985 ret <vscale x 16 x i8> %b986}987 988define <vscale x 4 x float> @fadd_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {989; CHECK-LABEL: fadd_nxv4f32_x:990; CHECK: // %bb.0: // %entry991; CHECK-NEXT: ptrue p0.s992; CHECK-NEXT: fadd z1.s, z0.s, z1.s993; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.0994; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s995; CHECK-NEXT: ret996entry:997 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer998 %a = fadd <vscale x 4 x float> %x, %y999 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x1000 ret <vscale x 4 x float> %b1001}1002 1003define <vscale x 8 x half> @fadd_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1004; CHECK-LABEL: fadd_nxv8f16_x:1005; CHECK: // %bb.0: // %entry1006; CHECK-NEXT: ptrue p0.h1007; CHECK-NEXT: fadd z1.h, z0.h, z1.h1008; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.01009; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h1010; CHECK-NEXT: ret1011entry:1012 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1013 %a = fadd <vscale x 8 x half> %x, %y1014 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x1015 ret <vscale x 8 x half> %b1016}1017 1018define <vscale x 2 x double> @fadd_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1019; CHECK-LABEL: fadd_nxv2f64_x:1020; CHECK: // %bb.0: // %entry1021; CHECK-NEXT: ptrue p0.d1022; CHECK-NEXT: fadd z1.d, z0.d, z1.d1023; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.01024; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d1025; CHECK-NEXT: ret1026entry:1027 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1028 %a = fadd <vscale x 2 x double> %x, %y1029 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x1030 ret <vscale x 2 x double> %b1031}1032 1033define <vscale x 4 x float> @fsub_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1034; CHECK-LABEL: fsub_nxv4f32_x:1035; CHECK: // %bb.0: // %entry1036; CHECK-NEXT: ptrue p0.s1037; CHECK-NEXT: fsub z1.s, z0.s, z1.s1038; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.01039; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s1040; CHECK-NEXT: ret1041entry:1042 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1043 %a = fsub <vscale x 4 x float> %x, %y1044 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x1045 ret <vscale x 4 x float> %b1046}1047 1048define <vscale x 8 x half> @fsub_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1049; CHECK-LABEL: fsub_nxv8f16_x:1050; CHECK: // %bb.0: // %entry1051; CHECK-NEXT: ptrue p0.h1052; CHECK-NEXT: fsub z1.h, z0.h, z1.h1053; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.01054; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h1055; CHECK-NEXT: ret1056entry:1057 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1058 %a = fsub <vscale x 8 x half> %x, %y1059 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x1060 ret <vscale x 8 x half> %b1061}1062 1063define <vscale x 2 x double> @fsub_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1064; CHECK-LABEL: fsub_nxv2f64_x:1065; CHECK: // %bb.0: // %entry1066; CHECK-NEXT: ptrue p0.d1067; CHECK-NEXT: fsub z1.d, z0.d, z1.d1068; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.01069; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d1070; CHECK-NEXT: ret1071entry:1072 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1073 %a = fsub <vscale x 2 x double> %x, %y1074 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x1075 ret <vscale x 2 x double> %b1076}1077 1078define <vscale x 4 x float> @fmul_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1079; CHECK-LABEL: fmul_nxv4f32_x:1080; CHECK: // %bb.0: // %entry1081; CHECK-NEXT: ptrue p0.s1082; CHECK-NEXT: fmul z1.s, z0.s, z1.s1083; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.01084; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s1085; CHECK-NEXT: ret1086entry:1087 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1088 %a = fmul <vscale x 4 x float> %x, %y1089 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x1090 ret <vscale x 4 x float> %b1091}1092 1093define <vscale x 8 x half> @fmul_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1094; CHECK-LABEL: fmul_nxv8f16_x:1095; CHECK: // %bb.0: // %entry1096; CHECK-NEXT: ptrue p0.h1097; CHECK-NEXT: fmul z1.h, z0.h, z1.h1098; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.01099; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h1100; CHECK-NEXT: ret1101entry:1102 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1103 %a = fmul <vscale x 8 x half> %x, %y1104 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x1105 ret <vscale x 8 x half> %b1106}1107 1108define <vscale x 2 x double> @fmul_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1109; CHECK-LABEL: fmul_nxv2f64_x:1110; CHECK: // %bb.0: // %entry1111; CHECK-NEXT: ptrue p0.d1112; CHECK-NEXT: fmul z1.d, z0.d, z1.d1113; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.01114; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d1115; CHECK-NEXT: ret1116entry:1117 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1118 %a = fmul <vscale x 2 x double> %x, %y1119 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x1120 ret <vscale x 2 x double> %b1121}1122 1123define <vscale x 4 x float> @fdiv_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1124; CHECK-LABEL: fdiv_nxv4f32_x:1125; CHECK: // %bb.0: // %entry1126; CHECK-NEXT: ptrue p0.s1127; CHECK-NEXT: fdivr z1.s, p0/m, z1.s, z0.s1128; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.01129; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s1130; CHECK-NEXT: ret1131entry:1132 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1133 %a = fdiv <vscale x 4 x float> %x, %y1134 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x1135 ret <vscale x 4 x float> %b1136}1137 1138define <vscale x 8 x half> @fdiv_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1139; CHECK-LABEL: fdiv_nxv8f16_x:1140; CHECK: // %bb.0: // %entry1141; CHECK-NEXT: ptrue p0.h1142; CHECK-NEXT: fdivr z1.h, p0/m, z1.h, z0.h1143; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.01144; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h1145; CHECK-NEXT: ret1146entry:1147 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1148 %a = fdiv <vscale x 8 x half> %x, %y1149 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x1150 ret <vscale x 8 x half> %b1151}1152 1153define <vscale x 2 x double> @fdiv_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1154; CHECK-LABEL: fdiv_nxv2f64_x:1155; CHECK: // %bb.0: // %entry1156; CHECK-NEXT: ptrue p0.d1157; CHECK-NEXT: fdivr z1.d, p0/m, z1.d, z0.d1158; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.01159; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d1160; CHECK-NEXT: ret1161entry:1162 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1163 %a = fdiv <vscale x 2 x double> %x, %y1164 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x1165 ret <vscale x 2 x double> %b1166}1167 1168define <vscale x 4 x float> @minnum_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1169; CHECK-LABEL: minnum_nxv4f32_x:1170; CHECK: // %bb.0: // %entry1171; CHECK-NEXT: ptrue p0.s1172; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.01173; CHECK-NEXT: fminnm z1.s, p0/m, z1.s, z0.s1174; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s1175; CHECK-NEXT: ret1176entry:1177 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1178 %a = call <vscale x 4 x float> @llvm.minnum.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y)1179 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x1180 ret <vscale x 4 x float> %b1181}1182 1183define <vscale x 8 x half> @minnum_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1184; CHECK-LABEL: minnum_nxv8f16_x:1185; CHECK: // %bb.0: // %entry1186; CHECK-NEXT: ptrue p0.h1187; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.01188; CHECK-NEXT: fminnm z1.h, p0/m, z1.h, z0.h1189; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h1190; CHECK-NEXT: ret1191entry:1192 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1193 %a = call <vscale x 8 x half> @llvm.minnum.nxv8f16(<vscale x 8 x half> %x, <vscale x 8 x half> %y)1194 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x1195 ret <vscale x 8 x half> %b1196}1197 1198define <vscale x 2 x double> @minnum_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1199; CHECK-LABEL: minnum_nxv2f64_x:1200; CHECK: // %bb.0: // %entry1201; CHECK-NEXT: ptrue p0.d1202; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.01203; CHECK-NEXT: fminnm z1.d, p0/m, z1.d, z0.d1204; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d1205; CHECK-NEXT: ret1206entry:1207 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1208 %a = call <vscale x 2 x double> @llvm.minnum.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y)1209 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x1210 ret <vscale x 2 x double> %b1211}1212 1213define <vscale x 4 x float> @maxnum_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1214; CHECK-LABEL: maxnum_nxv4f32_x:1215; CHECK: // %bb.0: // %entry1216; CHECK-NEXT: ptrue p0.s1217; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.01218; CHECK-NEXT: fmaxnm z1.s, p0/m, z1.s, z0.s1219; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s1220; CHECK-NEXT: ret1221entry:1222 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1223 %a = call <vscale x 4 x float> @llvm.maxnum.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y)1224 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x1225 ret <vscale x 4 x float> %b1226}1227 1228define <vscale x 8 x half> @maxnum_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1229; CHECK-LABEL: maxnum_nxv8f16_x:1230; CHECK: // %bb.0: // %entry1231; CHECK-NEXT: ptrue p0.h1232; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.01233; CHECK-NEXT: fmaxnm z1.h, p0/m, z1.h, z0.h1234; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h1235; CHECK-NEXT: ret1236entry:1237 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1238 %a = call <vscale x 8 x half> @llvm.maxnum.nxv8f16(<vscale x 8 x half> %x, <vscale x 8 x half> %y)1239 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x1240 ret <vscale x 8 x half> %b1241}1242 1243define <vscale x 2 x double> @maxnum_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1244; CHECK-LABEL: maxnum_nxv2f64_x:1245; CHECK: // %bb.0: // %entry1246; CHECK-NEXT: ptrue p0.d1247; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.01248; CHECK-NEXT: fmaxnm z1.d, p0/m, z1.d, z0.d1249; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d1250; CHECK-NEXT: ret1251entry:1252 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1253 %a = call <vscale x 2 x double> @llvm.maxnum.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y)1254 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x1255 ret <vscale x 2 x double> %b1256}1257 1258define <vscale x 4 x float> @minimum_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1259; CHECK-LABEL: minimum_nxv4f32_x:1260; CHECK: // %bb.0: // %entry1261; CHECK-NEXT: ptrue p0.s1262; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.01263; CHECK-NEXT: fmin z1.s, p0/m, z1.s, z0.s1264; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s1265; CHECK-NEXT: ret1266entry:1267 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1268 %a = call <vscale x 4 x float> @llvm.minimum.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y)1269 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x1270 ret <vscale x 4 x float> %b1271}1272 1273define <vscale x 8 x half> @minimum_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1274; CHECK-LABEL: minimum_nxv8f16_x:1275; CHECK: // %bb.0: // %entry1276; CHECK-NEXT: ptrue p0.h1277; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.01278; CHECK-NEXT: fmin z1.h, p0/m, z1.h, z0.h1279; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h1280; CHECK-NEXT: ret1281entry:1282 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1283 %a = call <vscale x 8 x half> @llvm.minimum.nxv8f16(<vscale x 8 x half> %x, <vscale x 8 x half> %y)1284 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x1285 ret <vscale x 8 x half> %b1286}1287 1288define <vscale x 2 x double> @minimum_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1289; CHECK-LABEL: minimum_nxv2f64_x:1290; CHECK: // %bb.0: // %entry1291; CHECK-NEXT: ptrue p0.d1292; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.01293; CHECK-NEXT: fmin z1.d, p0/m, z1.d, z0.d1294; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d1295; CHECK-NEXT: ret1296entry:1297 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1298 %a = call <vscale x 2 x double> @llvm.minimum.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y)1299 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x1300 ret <vscale x 2 x double> %b1301}1302 1303define <vscale x 4 x float> @maximum_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1304; CHECK-LABEL: maximum_nxv4f32_x:1305; CHECK: // %bb.0: // %entry1306; CHECK-NEXT: ptrue p0.s1307; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.01308; CHECK-NEXT: fmax z1.s, p0/m, z1.s, z0.s1309; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s1310; CHECK-NEXT: ret1311entry:1312 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1313 %a = call <vscale x 4 x float> @llvm.maximum.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y)1314 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x1315 ret <vscale x 4 x float> %b1316}1317 1318define <vscale x 8 x half> @maximum_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1319; CHECK-LABEL: maximum_nxv8f16_x:1320; CHECK: // %bb.0: // %entry1321; CHECK-NEXT: ptrue p0.h1322; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.01323; CHECK-NEXT: fmax z1.h, p0/m, z1.h, z0.h1324; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h1325; CHECK-NEXT: ret1326entry:1327 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1328 %a = call <vscale x 8 x half> @llvm.maximum.nxv8f16(<vscale x 8 x half> %x, <vscale x 8 x half> %y)1329 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x1330 ret <vscale x 8 x half> %b1331}1332 1333define <vscale x 2 x double> @maximum_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1334; CHECK-LABEL: maximum_nxv2f64_x:1335; CHECK: // %bb.0: // %entry1336; CHECK-NEXT: ptrue p0.d1337; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.01338; CHECK-NEXT: fmax z1.d, p0/m, z1.d, z0.d1339; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d1340; CHECK-NEXT: ret1341entry:1342 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1343 %a = call <vscale x 2 x double> @llvm.maximum.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y)1344 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x1345 ret <vscale x 2 x double> %b1346}1347 1348define <vscale x 4 x float> @fmai_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {1349; CHECK-LABEL: fmai_nxv4f32_x:1350; CHECK: // %bb.0: // %entry1351; CHECK-NEXT: ptrue p0.s1352; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.01353; CHECK-NEXT: fmad z1.s, p0/m, z2.s, z0.s1354; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s1355; CHECK-NEXT: ret1356entry:1357 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1358 %a = call <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %x)1359 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x1360 ret <vscale x 4 x float> %b1361}1362 1363define <vscale x 8 x half> @fmai_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {1364; CHECK-LABEL: fmai_nxv8f16_x:1365; CHECK: // %bb.0: // %entry1366; CHECK-NEXT: ptrue p0.h1367; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.01368; CHECK-NEXT: fmad z1.h, p0/m, z2.h, z0.h1369; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h1370; CHECK-NEXT: ret1371entry:1372 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1373 %a = call <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %x)1374 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x1375 ret <vscale x 8 x half> %b1376}1377 1378define <vscale x 2 x double> @fmai_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {1379; CHECK-LABEL: fmai_nxv2f64_x:1380; CHECK: // %bb.0: // %entry1381; CHECK-NEXT: ptrue p0.d1382; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.01383; CHECK-NEXT: fmad z1.d, p0/m, z2.d, z0.d1384; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d1385; CHECK-NEXT: ret1386entry:1387 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1388 %a = call <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %x)1389 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x1390 ret <vscale x 2 x double> %b1391}1392 1393define <vscale x 4 x float> @fma_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {1394; CHECK-LABEL: fma_nxv4f32_x:1395; CHECK: // %bb.0: // %entry1396; CHECK-NEXT: ptrue p0.s1397; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.01398; CHECK-NEXT: fmad z1.s, p0/m, z2.s, z0.s1399; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s1400; CHECK-NEXT: ret1401entry:1402 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1403 %m = fmul fast <vscale x 4 x float> %y, %z1404 %a = fadd fast <vscale x 4 x float> %m, %x1405 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x1406 ret <vscale x 4 x float> %b1407}1408 1409define <vscale x 8 x half> @fma_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {1410; CHECK-LABEL: fma_nxv8f16_x:1411; CHECK: // %bb.0: // %entry1412; CHECK-NEXT: ptrue p0.h1413; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.01414; CHECK-NEXT: fmad z1.h, p0/m, z2.h, z0.h1415; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h1416; CHECK-NEXT: ret1417entry:1418 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1419 %m = fmul fast <vscale x 8 x half> %y, %z1420 %a = fadd fast <vscale x 8 x half> %m, %x1421 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x1422 ret <vscale x 8 x half> %b1423}1424 1425define <vscale x 2 x double> @fma_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {1426; CHECK-LABEL: fma_nxv2f64_x:1427; CHECK: // %bb.0: // %entry1428; CHECK-NEXT: ptrue p0.d1429; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.01430; CHECK-NEXT: fmad z1.d, p0/m, z2.d, z0.d1431; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d1432; CHECK-NEXT: ret1433entry:1434 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1435 %m = fmul fast <vscale x 2 x double> %y, %z1436 %a = fadd fast <vscale x 2 x double> %m, %x1437 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x1438 ret <vscale x 2 x double> %b1439}1440 1441define <vscale x 2 x i64> @add_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1442; CHECK-LABEL: add_nxv2i64_y:1443; CHECK: // %bb.0: // %entry1444; CHECK-NEXT: ptrue p0.d1445; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01446; CHECK-NEXT: add z1.d, p0/m, z1.d, z0.d1447; CHECK-NEXT: mov z0.d, z1.d1448; CHECK-NEXT: ret1449entry:1450 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1451 %a = add <vscale x 2 x i64> %x, %y1452 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1453 ret <vscale x 2 x i64> %b1454}1455 1456define <vscale x 4 x i32> @add_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1457; CHECK-LABEL: add_nxv4i32_y:1458; CHECK: // %bb.0: // %entry1459; CHECK-NEXT: ptrue p0.s1460; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01461; CHECK-NEXT: add z1.s, p0/m, z1.s, z0.s1462; CHECK-NEXT: mov z0.d, z1.d1463; CHECK-NEXT: ret1464entry:1465 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1466 %a = add <vscale x 4 x i32> %x, %y1467 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1468 ret <vscale x 4 x i32> %b1469}1470 1471define <vscale x 8 x i16> @add_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1472; CHECK-LABEL: add_nxv8i16_y:1473; CHECK: // %bb.0: // %entry1474; CHECK-NEXT: ptrue p0.h1475; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01476; CHECK-NEXT: add z1.h, p0/m, z1.h, z0.h1477; CHECK-NEXT: mov z0.d, z1.d1478; CHECK-NEXT: ret1479entry:1480 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1481 %a = add <vscale x 8 x i16> %x, %y1482 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1483 ret <vscale x 8 x i16> %b1484}1485 1486define <vscale x 16 x i8> @add_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1487; CHECK-LABEL: add_nxv16i8_y:1488; CHECK: // %bb.0: // %entry1489; CHECK-NEXT: ptrue p0.b1490; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01491; CHECK-NEXT: add z1.b, p0/m, z1.b, z0.b1492; CHECK-NEXT: mov z0.d, z1.d1493; CHECK-NEXT: ret1494entry:1495 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1496 %a = add <vscale x 16 x i8> %x, %y1497 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1498 ret <vscale x 16 x i8> %b1499}1500 1501define <vscale x 2 x i64> @sub_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1502; CHECK-LABEL: sub_nxv2i64_y:1503; CHECK: // %bb.0: // %entry1504; CHECK-NEXT: ptrue p0.d1505; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01506; CHECK-NEXT: subr z1.d, p0/m, z1.d, z0.d1507; CHECK-NEXT: mov z0.d, z1.d1508; CHECK-NEXT: ret1509entry:1510 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1511 %a = sub <vscale x 2 x i64> %x, %y1512 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1513 ret <vscale x 2 x i64> %b1514}1515 1516define <vscale x 4 x i32> @sub_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1517; CHECK-LABEL: sub_nxv4i32_y:1518; CHECK: // %bb.0: // %entry1519; CHECK-NEXT: ptrue p0.s1520; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01521; CHECK-NEXT: subr z1.s, p0/m, z1.s, z0.s1522; CHECK-NEXT: mov z0.d, z1.d1523; CHECK-NEXT: ret1524entry:1525 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1526 %a = sub <vscale x 4 x i32> %x, %y1527 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1528 ret <vscale x 4 x i32> %b1529}1530 1531define <vscale x 8 x i16> @sub_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1532; CHECK-LABEL: sub_nxv8i16_y:1533; CHECK: // %bb.0: // %entry1534; CHECK-NEXT: ptrue p0.h1535; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01536; CHECK-NEXT: subr z1.h, p0/m, z1.h, z0.h1537; CHECK-NEXT: mov z0.d, z1.d1538; CHECK-NEXT: ret1539entry:1540 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1541 %a = sub <vscale x 8 x i16> %x, %y1542 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1543 ret <vscale x 8 x i16> %b1544}1545 1546define <vscale x 16 x i8> @sub_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1547; CHECK-LABEL: sub_nxv16i8_y:1548; CHECK: // %bb.0: // %entry1549; CHECK-NEXT: ptrue p0.b1550; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01551; CHECK-NEXT: subr z1.b, p0/m, z1.b, z0.b1552; CHECK-NEXT: mov z0.d, z1.d1553; CHECK-NEXT: ret1554entry:1555 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1556 %a = sub <vscale x 16 x i8> %x, %y1557 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1558 ret <vscale x 16 x i8> %b1559}1560 1561define <vscale x 2 x i64> @mul_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1562; CHECK-LABEL: mul_nxv2i64_y:1563; CHECK: // %bb.0: // %entry1564; CHECK-NEXT: ptrue p0.d1565; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01566; CHECK-NEXT: mul z1.d, p0/m, z1.d, z0.d1567; CHECK-NEXT: mov z0.d, z1.d1568; CHECK-NEXT: ret1569entry:1570 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1571 %a = mul <vscale x 2 x i64> %x, %y1572 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1573 ret <vscale x 2 x i64> %b1574}1575 1576define <vscale x 4 x i32> @mul_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1577; CHECK-LABEL: mul_nxv4i32_y:1578; CHECK: // %bb.0: // %entry1579; CHECK-NEXT: ptrue p0.s1580; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01581; CHECK-NEXT: mul z1.s, p0/m, z1.s, z0.s1582; CHECK-NEXT: mov z0.d, z1.d1583; CHECK-NEXT: ret1584entry:1585 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1586 %a = mul <vscale x 4 x i32> %x, %y1587 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1588 ret <vscale x 4 x i32> %b1589}1590 1591define <vscale x 8 x i16> @mul_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1592; CHECK-LABEL: mul_nxv8i16_y:1593; CHECK: // %bb.0: // %entry1594; CHECK-NEXT: ptrue p0.h1595; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01596; CHECK-NEXT: mul z1.h, p0/m, z1.h, z0.h1597; CHECK-NEXT: mov z0.d, z1.d1598; CHECK-NEXT: ret1599entry:1600 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1601 %a = mul <vscale x 8 x i16> %x, %y1602 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1603 ret <vscale x 8 x i16> %b1604}1605 1606define <vscale x 16 x i8> @mul_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1607; CHECK-LABEL: mul_nxv16i8_y:1608; CHECK: // %bb.0: // %entry1609; CHECK-NEXT: ptrue p0.b1610; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01611; CHECK-NEXT: mul z1.b, p0/m, z1.b, z0.b1612; CHECK-NEXT: mov z0.d, z1.d1613; CHECK-NEXT: ret1614entry:1615 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1616 %a = mul <vscale x 16 x i8> %x, %y1617 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1618 ret <vscale x 16 x i8> %b1619}1620 1621define <vscale x 2 x i64> @sdiv_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1622; CHECK-LABEL: sdiv_nxv2i64_y:1623; CHECK: // %bb.0: // %entry1624; CHECK-NEXT: ptrue p0.d1625; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d1626; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01627; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d1628; CHECK-NEXT: ret1629entry:1630 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1631 %a = sdiv <vscale x 2 x i64> %x, %y1632 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1633 ret <vscale x 2 x i64> %b1634}1635 1636define <vscale x 4 x i32> @sdiv_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1637; CHECK-LABEL: sdiv_nxv4i32_y:1638; CHECK: // %bb.0: // %entry1639; CHECK-NEXT: ptrue p0.s1640; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s1641; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01642; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s1643; CHECK-NEXT: ret1644entry:1645 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1646 %a = sdiv <vscale x 4 x i32> %x, %y1647 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1648 ret <vscale x 4 x i32> %b1649}1650 1651define <vscale x 8 x i16> @sdiv_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1652; CHECK-LABEL: sdiv_nxv8i16_y:1653; CHECK: // %bb.0: // %entry1654; CHECK-NEXT: sunpkhi z3.s, z1.h1655; CHECK-NEXT: sunpkhi z4.s, z0.h1656; CHECK-NEXT: ptrue p0.s1657; CHECK-NEXT: sunpklo z0.s, z0.h1658; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s1659; CHECK-NEXT: sunpklo z4.s, z1.h1660; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z4.s1661; CHECK-NEXT: ptrue p0.h1662; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01663; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h1664; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h1665; CHECK-NEXT: ret1666entry:1667 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1668 %a = sdiv <vscale x 8 x i16> %x, %y1669 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1670 ret <vscale x 8 x i16> %b1671}1672 1673define <vscale x 16 x i8> @sdiv_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1674; CHECK-LABEL: sdiv_nxv16i8_y:1675; CHECK: // %bb.0: // %entry1676; CHECK-NEXT: sunpkhi z3.h, z1.b1677; CHECK-NEXT: sunpkhi z4.h, z0.b1678; CHECK-NEXT: ptrue p0.s1679; CHECK-NEXT: sunpklo z0.h, z0.b1680; CHECK-NEXT: sunpkhi z5.s, z3.h1681; CHECK-NEXT: sunpkhi z6.s, z4.h1682; CHECK-NEXT: sunpklo z3.s, z3.h1683; CHECK-NEXT: sunpklo z4.s, z4.h1684; CHECK-NEXT: sunpkhi z7.s, z0.h1685; CHECK-NEXT: sunpklo z0.s, z0.h1686; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s1687; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s1688; CHECK-NEXT: sunpklo z4.h, z1.b1689; CHECK-NEXT: sunpkhi z6.s, z4.h1690; CHECK-NEXT: sunpklo z4.s, z4.h1691; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s1692; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h1693; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z4.s1694; CHECK-NEXT: ptrue p0.b1695; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01696; CHECK-NEXT: uzp1 z0.h, z0.h, z6.h1697; CHECK-NEXT: uzp1 z0.b, z0.b, z3.b1698; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b1699; CHECK-NEXT: ret1700entry:1701 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1702 %a = sdiv <vscale x 16 x i8> %x, %y1703 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1704 ret <vscale x 16 x i8> %b1705}1706 1707define <vscale x 2 x i64> @udiv_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1708; CHECK-LABEL: udiv_nxv2i64_y:1709; CHECK: // %bb.0: // %entry1710; CHECK-NEXT: ptrue p0.d1711; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d1712; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01713; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d1714; CHECK-NEXT: ret1715entry:1716 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1717 %a = udiv <vscale x 2 x i64> %x, %y1718 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1719 ret <vscale x 2 x i64> %b1720}1721 1722define <vscale x 4 x i32> @udiv_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1723; CHECK-LABEL: udiv_nxv4i32_y:1724; CHECK: // %bb.0: // %entry1725; CHECK-NEXT: ptrue p0.s1726; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s1727; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01728; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s1729; CHECK-NEXT: ret1730entry:1731 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1732 %a = udiv <vscale x 4 x i32> %x, %y1733 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1734 ret <vscale x 4 x i32> %b1735}1736 1737define <vscale x 8 x i16> @udiv_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1738; CHECK-LABEL: udiv_nxv8i16_y:1739; CHECK: // %bb.0: // %entry1740; CHECK-NEXT: uunpkhi z3.s, z1.h1741; CHECK-NEXT: uunpkhi z4.s, z0.h1742; CHECK-NEXT: ptrue p0.s1743; CHECK-NEXT: uunpklo z0.s, z0.h1744; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s1745; CHECK-NEXT: uunpklo z4.s, z1.h1746; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z4.s1747; CHECK-NEXT: ptrue p0.h1748; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01749; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h1750; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h1751; CHECK-NEXT: ret1752entry:1753 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1754 %a = udiv <vscale x 8 x i16> %x, %y1755 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1756 ret <vscale x 8 x i16> %b1757}1758 1759define <vscale x 16 x i8> @udiv_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1760; CHECK-LABEL: udiv_nxv16i8_y:1761; CHECK: // %bb.0: // %entry1762; CHECK-NEXT: uunpkhi z3.h, z1.b1763; CHECK-NEXT: uunpkhi z4.h, z0.b1764; CHECK-NEXT: ptrue p0.s1765; CHECK-NEXT: uunpklo z0.h, z0.b1766; CHECK-NEXT: uunpkhi z5.s, z3.h1767; CHECK-NEXT: uunpkhi z6.s, z4.h1768; CHECK-NEXT: uunpklo z3.s, z3.h1769; CHECK-NEXT: uunpklo z4.s, z4.h1770; CHECK-NEXT: uunpkhi z7.s, z0.h1771; CHECK-NEXT: uunpklo z0.s, z0.h1772; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s1773; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s1774; CHECK-NEXT: uunpklo z4.h, z1.b1775; CHECK-NEXT: uunpkhi z6.s, z4.h1776; CHECK-NEXT: uunpklo z4.s, z4.h1777; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s1778; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h1779; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z4.s1780; CHECK-NEXT: ptrue p0.b1781; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01782; CHECK-NEXT: uzp1 z0.h, z0.h, z6.h1783; CHECK-NEXT: uzp1 z0.b, z0.b, z3.b1784; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b1785; CHECK-NEXT: ret1786entry:1787 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1788 %a = udiv <vscale x 16 x i8> %x, %y1789 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1790 ret <vscale x 16 x i8> %b1791}1792 1793define <vscale x 2 x i64> @srem_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1794; CHECK-LABEL: srem_nxv2i64_y:1795; CHECK: // %bb.0: // %entry1796; CHECK-NEXT: ptrue p0.d1797; CHECK-NEXT: movprfx z3, z01798; CHECK-NEXT: sdiv z3.d, p0/m, z3.d, z1.d1799; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01800; CHECK-NEXT: msb z1.d, p0/m, z3.d, z0.d1801; CHECK-NEXT: mov z0.d, z1.d1802; CHECK-NEXT: ret1803entry:1804 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1805 %a = srem <vscale x 2 x i64> %x, %y1806 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1807 ret <vscale x 2 x i64> %b1808}1809 1810define <vscale x 4 x i32> @srem_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1811; CHECK-LABEL: srem_nxv4i32_y:1812; CHECK: // %bb.0: // %entry1813; CHECK-NEXT: ptrue p0.s1814; CHECK-NEXT: movprfx z3, z01815; CHECK-NEXT: sdiv z3.s, p0/m, z3.s, z1.s1816; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01817; CHECK-NEXT: msb z1.s, p0/m, z3.s, z0.s1818; CHECK-NEXT: mov z0.d, z1.d1819; CHECK-NEXT: ret1820entry:1821 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1822 %a = srem <vscale x 4 x i32> %x, %y1823 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1824 ret <vscale x 4 x i32> %b1825}1826 1827define <vscale x 8 x i16> @srem_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1828; CHECK-LABEL: srem_nxv8i16_y:1829; CHECK: // %bb.0: // %entry1830; CHECK-NEXT: sunpkhi z3.s, z1.h1831; CHECK-NEXT: sunpkhi z4.s, z0.h1832; CHECK-NEXT: ptrue p0.s1833; CHECK-NEXT: sunpklo z5.s, z0.h1834; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s1835; CHECK-NEXT: sunpklo z4.s, z1.h1836; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s1837; CHECK-NEXT: ptrue p0.h1838; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01839; CHECK-NEXT: uzp1 z2.h, z4.h, z3.h1840; CHECK-NEXT: msb z1.h, p0/m, z2.h, z0.h1841; CHECK-NEXT: mov z0.d, z1.d1842; CHECK-NEXT: ret1843entry:1844 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1845 %a = srem <vscale x 8 x i16> %x, %y1846 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1847 ret <vscale x 8 x i16> %b1848}1849 1850define <vscale x 16 x i8> @srem_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1851; CHECK-LABEL: srem_nxv16i8_y:1852; CHECK: // %bb.0: // %entry1853; CHECK-NEXT: sunpkhi z3.h, z1.b1854; CHECK-NEXT: sunpkhi z4.h, z0.b1855; CHECK-NEXT: ptrue p0.s1856; CHECK-NEXT: sunpkhi z5.s, z3.h1857; CHECK-NEXT: sunpkhi z6.s, z4.h1858; CHECK-NEXT: sunpklo z3.s, z3.h1859; CHECK-NEXT: sunpklo z4.s, z4.h1860; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s1861; CHECK-NEXT: sunpklo z6.h, z0.b1862; CHECK-NEXT: sunpkhi z24.s, z6.h1863; CHECK-NEXT: sunpklo z6.s, z6.h1864; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s1865; CHECK-NEXT: sunpklo z4.h, z1.b1866; CHECK-NEXT: sunpkhi z7.s, z4.h1867; CHECK-NEXT: sunpklo z4.s, z4.h1868; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z24.s1869; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h1870; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z6.s1871; CHECK-NEXT: ptrue p0.b1872; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01873; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h1874; CHECK-NEXT: uzp1 z2.b, z4.b, z3.b1875; CHECK-NEXT: msb z1.b, p0/m, z2.b, z0.b1876; CHECK-NEXT: mov z0.d, z1.d1877; CHECK-NEXT: ret1878entry:1879 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1880 %a = srem <vscale x 16 x i8> %x, %y1881 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1882 ret <vscale x 16 x i8> %b1883}1884 1885define <vscale x 2 x i64> @urem_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1886; CHECK-LABEL: urem_nxv2i64_y:1887; CHECK: // %bb.0: // %entry1888; CHECK-NEXT: ptrue p0.d1889; CHECK-NEXT: movprfx z3, z01890; CHECK-NEXT: udiv z3.d, p0/m, z3.d, z1.d1891; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01892; CHECK-NEXT: msb z1.d, p0/m, z3.d, z0.d1893; CHECK-NEXT: mov z0.d, z1.d1894; CHECK-NEXT: ret1895entry:1896 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1897 %a = urem <vscale x 2 x i64> %x, %y1898 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1899 ret <vscale x 2 x i64> %b1900}1901 1902define <vscale x 4 x i32> @urem_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1903; CHECK-LABEL: urem_nxv4i32_y:1904; CHECK: // %bb.0: // %entry1905; CHECK-NEXT: ptrue p0.s1906; CHECK-NEXT: movprfx z3, z01907; CHECK-NEXT: udiv z3.s, p0/m, z3.s, z1.s1908; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01909; CHECK-NEXT: msb z1.s, p0/m, z3.s, z0.s1910; CHECK-NEXT: mov z0.d, z1.d1911; CHECK-NEXT: ret1912entry:1913 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1914 %a = urem <vscale x 4 x i32> %x, %y1915 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1916 ret <vscale x 4 x i32> %b1917}1918 1919define <vscale x 8 x i16> @urem_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1920; CHECK-LABEL: urem_nxv8i16_y:1921; CHECK: // %bb.0: // %entry1922; CHECK-NEXT: uunpkhi z3.s, z1.h1923; CHECK-NEXT: uunpkhi z4.s, z0.h1924; CHECK-NEXT: ptrue p0.s1925; CHECK-NEXT: uunpklo z5.s, z0.h1926; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s1927; CHECK-NEXT: uunpklo z4.s, z1.h1928; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s1929; CHECK-NEXT: ptrue p0.h1930; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01931; CHECK-NEXT: uzp1 z2.h, z4.h, z3.h1932; CHECK-NEXT: msb z1.h, p0/m, z2.h, z0.h1933; CHECK-NEXT: mov z0.d, z1.d1934; CHECK-NEXT: ret1935entry:1936 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1937 %a = urem <vscale x 8 x i16> %x, %y1938 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1939 ret <vscale x 8 x i16> %b1940}1941 1942define <vscale x 16 x i8> @urem_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1943; CHECK-LABEL: urem_nxv16i8_y:1944; CHECK: // %bb.0: // %entry1945; CHECK-NEXT: uunpkhi z3.h, z1.b1946; CHECK-NEXT: uunpkhi z4.h, z0.b1947; CHECK-NEXT: ptrue p0.s1948; CHECK-NEXT: uunpkhi z5.s, z3.h1949; CHECK-NEXT: uunpkhi z6.s, z4.h1950; CHECK-NEXT: uunpklo z3.s, z3.h1951; CHECK-NEXT: uunpklo z4.s, z4.h1952; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s1953; CHECK-NEXT: uunpklo z6.h, z0.b1954; CHECK-NEXT: uunpkhi z24.s, z6.h1955; CHECK-NEXT: uunpklo z6.s, z6.h1956; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s1957; CHECK-NEXT: uunpklo z4.h, z1.b1958; CHECK-NEXT: uunpkhi z7.s, z4.h1959; CHECK-NEXT: uunpklo z4.s, z4.h1960; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z24.s1961; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h1962; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z6.s1963; CHECK-NEXT: ptrue p0.b1964; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01965; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h1966; CHECK-NEXT: uzp1 z2.b, z4.b, z3.b1967; CHECK-NEXT: msb z1.b, p0/m, z2.b, z0.b1968; CHECK-NEXT: mov z0.d, z1.d1969; CHECK-NEXT: ret1970entry:1971 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1972 %a = urem <vscale x 16 x i8> %x, %y1973 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1974 ret <vscale x 16 x i8> %b1975}1976 1977define <vscale x 2 x i64> @and_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1978; CHECK-LABEL: and_nxv2i64_y:1979; CHECK: // %bb.0: // %entry1980; CHECK-NEXT: ptrue p0.d1981; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01982; CHECK-NEXT: and z1.d, p0/m, z1.d, z0.d1983; CHECK-NEXT: mov z0.d, z1.d1984; CHECK-NEXT: ret1985entry:1986 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1987 %a = and <vscale x 2 x i64> %x, %y1988 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1989 ret <vscale x 2 x i64> %b1990}1991 1992define <vscale x 4 x i32> @and_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1993; CHECK-LABEL: and_nxv4i32_y:1994; CHECK: // %bb.0: // %entry1995; CHECK-NEXT: ptrue p0.s1996; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01997; CHECK-NEXT: and z1.s, p0/m, z1.s, z0.s1998; CHECK-NEXT: mov z0.d, z1.d1999; CHECK-NEXT: ret2000entry:2001 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer2002 %a = and <vscale x 4 x i32> %x, %y2003 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y2004 ret <vscale x 4 x i32> %b2005}2006 2007define <vscale x 8 x i16> @and_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {2008; CHECK-LABEL: and_nxv8i16_y:2009; CHECK: // %bb.0: // %entry2010; CHECK-NEXT: ptrue p0.h2011; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #02012; CHECK-NEXT: and z1.h, p0/m, z1.h, z0.h2013; CHECK-NEXT: mov z0.d, z1.d2014; CHECK-NEXT: ret2015entry:2016 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer2017 %a = and <vscale x 8 x i16> %x, %y2018 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y2019 ret <vscale x 8 x i16> %b2020}2021 2022define <vscale x 16 x i8> @and_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {2023; CHECK-LABEL: and_nxv16i8_y:2024; CHECK: // %bb.0: // %entry2025; CHECK-NEXT: ptrue p0.b2026; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #02027; CHECK-NEXT: and z1.b, p0/m, z1.b, z0.b2028; CHECK-NEXT: mov z0.d, z1.d2029; CHECK-NEXT: ret2030entry:2031 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer2032 %a = and <vscale x 16 x i8> %x, %y2033 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y2034 ret <vscale x 16 x i8> %b2035}2036 2037define <vscale x 2 x i64> @or_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {2038; CHECK-LABEL: or_nxv2i64_y:2039; CHECK: // %bb.0: // %entry2040; CHECK-NEXT: ptrue p0.d2041; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #02042; CHECK-NEXT: orr z1.d, p0/m, z1.d, z0.d2043; CHECK-NEXT: mov z0.d, z1.d2044; CHECK-NEXT: ret2045entry:2046 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer2047 %a = or <vscale x 2 x i64> %x, %y2048 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y2049 ret <vscale x 2 x i64> %b2050}2051 2052define <vscale x 4 x i32> @or_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {2053; CHECK-LABEL: or_nxv4i32_y:2054; CHECK: // %bb.0: // %entry2055; CHECK-NEXT: ptrue p0.s2056; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #02057; CHECK-NEXT: orr z1.s, p0/m, z1.s, z0.s2058; CHECK-NEXT: mov z0.d, z1.d2059; CHECK-NEXT: ret2060entry:2061 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer2062 %a = or <vscale x 4 x i32> %x, %y2063 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y2064 ret <vscale x 4 x i32> %b2065}2066 2067define <vscale x 8 x i16> @or_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {2068; CHECK-LABEL: or_nxv8i16_y:2069; CHECK: // %bb.0: // %entry2070; CHECK-NEXT: ptrue p0.h2071; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #02072; CHECK-NEXT: orr z1.h, p0/m, z1.h, z0.h2073; CHECK-NEXT: mov z0.d, z1.d2074; CHECK-NEXT: ret2075entry:2076 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer2077 %a = or <vscale x 8 x i16> %x, %y2078 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y2079 ret <vscale x 8 x i16> %b2080}2081 2082define <vscale x 16 x i8> @or_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {2083; CHECK-LABEL: or_nxv16i8_y:2084; CHECK: // %bb.0: // %entry2085; CHECK-NEXT: ptrue p0.b2086; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #02087; CHECK-NEXT: orr z1.b, p0/m, z1.b, z0.b2088; CHECK-NEXT: mov z0.d, z1.d2089; CHECK-NEXT: ret2090entry:2091 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer2092 %a = or <vscale x 16 x i8> %x, %y2093 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y2094 ret <vscale x 16 x i8> %b2095}2096 2097define <vscale x 2 x i64> @xor_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {2098; CHECK-LABEL: xor_nxv2i64_y:2099; CHECK: // %bb.0: // %entry2100; CHECK-NEXT: ptrue p0.d2101; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #02102; CHECK-NEXT: eor z1.d, p0/m, z1.d, z0.d2103; CHECK-NEXT: mov z0.d, z1.d2104; CHECK-NEXT: ret2105entry:2106 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer2107 %a = xor <vscale x 2 x i64> %x, %y2108 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y2109 ret <vscale x 2 x i64> %b2110}2111 2112define <vscale x 4 x i32> @xor_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {2113; CHECK-LABEL: xor_nxv4i32_y:2114; CHECK: // %bb.0: // %entry2115; CHECK-NEXT: ptrue p0.s2116; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #02117; CHECK-NEXT: eor z1.s, p0/m, z1.s, z0.s2118; CHECK-NEXT: mov z0.d, z1.d2119; CHECK-NEXT: ret2120entry:2121 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer2122 %a = xor <vscale x 4 x i32> %x, %y2123 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y2124 ret <vscale x 4 x i32> %b2125}2126 2127define <vscale x 8 x i16> @xor_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {2128; CHECK-LABEL: xor_nxv8i16_y:2129; CHECK: // %bb.0: // %entry2130; CHECK-NEXT: ptrue p0.h2131; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #02132; CHECK-NEXT: eor z1.h, p0/m, z1.h, z0.h2133; CHECK-NEXT: mov z0.d, z1.d2134; CHECK-NEXT: ret2135entry:2136 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer2137 %a = xor <vscale x 8 x i16> %x, %y2138 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y2139 ret <vscale x 8 x i16> %b2140}2141 2142define <vscale x 16 x i8> @xor_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {2143; CHECK-LABEL: xor_nxv16i8_y:2144; CHECK: // %bb.0: // %entry2145; CHECK-NEXT: ptrue p0.b2146; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #02147; CHECK-NEXT: eor z1.b, p0/m, z1.b, z0.b2148; CHECK-NEXT: mov z0.d, z1.d2149; CHECK-NEXT: ret2150entry:2151 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer2152 %a = xor <vscale x 16 x i8> %x, %y2153 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y2154 ret <vscale x 16 x i8> %b2155}2156 2157define <vscale x 2 x i64> @shl_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {2158; CHECK-LABEL: shl_nxv2i64_y:2159; CHECK: // %bb.0: // %entry2160; CHECK-NEXT: ptrue p0.d2161; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #02162; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d2163; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d2164; CHECK-NEXT: ret2165entry:2166 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer2167 %a = shl <vscale x 2 x i64> %x, %y2168 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y2169 ret <vscale x 2 x i64> %b2170}2171 2172define <vscale x 4 x i32> @shl_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {2173; CHECK-LABEL: shl_nxv4i32_y:2174; CHECK: // %bb.0: // %entry2175; CHECK-NEXT: ptrue p0.s2176; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #02177; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s2178; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s2179; CHECK-NEXT: ret2180entry:2181 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer2182 %a = shl <vscale x 4 x i32> %x, %y2183 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y2184 ret <vscale x 4 x i32> %b2185}2186 2187define <vscale x 8 x i16> @shl_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {2188; CHECK-LABEL: shl_nxv8i16_y:2189; CHECK: // %bb.0: // %entry2190; CHECK-NEXT: ptrue p0.h2191; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #02192; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h2193; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h2194; CHECK-NEXT: ret2195entry:2196 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer2197 %a = shl <vscale x 8 x i16> %x, %y2198 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y2199 ret <vscale x 8 x i16> %b2200}2201 2202define <vscale x 16 x i8> @shl_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {2203; CHECK-LABEL: shl_nxv16i8_y:2204; CHECK: // %bb.0: // %entry2205; CHECK-NEXT: ptrue p0.b2206; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #02207; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b2208; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b2209; CHECK-NEXT: ret2210entry:2211 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer2212 %a = shl <vscale x 16 x i8> %x, %y2213 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y2214 ret <vscale x 16 x i8> %b2215}2216 2217define <vscale x 2 x i64> @ashr_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {2218; CHECK-LABEL: ashr_nxv2i64_y:2219; CHECK: // %bb.0: // %entry2220; CHECK-NEXT: ptrue p0.d2221; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #02222; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d2223; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d2224; CHECK-NEXT: ret2225entry:2226 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer2227 %a = ashr <vscale x 2 x i64> %x, %y2228 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y2229 ret <vscale x 2 x i64> %b2230}2231 2232define <vscale x 4 x i32> @ashr_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {2233; CHECK-LABEL: ashr_nxv4i32_y:2234; CHECK: // %bb.0: // %entry2235; CHECK-NEXT: ptrue p0.s2236; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #02237; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s2238; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s2239; CHECK-NEXT: ret2240entry:2241 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer2242 %a = ashr <vscale x 4 x i32> %x, %y2243 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y2244 ret <vscale x 4 x i32> %b2245}2246 2247define <vscale x 8 x i16> @ashr_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {2248; CHECK-LABEL: ashr_nxv8i16_y:2249; CHECK: // %bb.0: // %entry2250; CHECK-NEXT: ptrue p0.h2251; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #02252; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h2253; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h2254; CHECK-NEXT: ret2255entry:2256 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer2257 %a = ashr <vscale x 8 x i16> %x, %y2258 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y2259 ret <vscale x 8 x i16> %b2260}2261 2262define <vscale x 16 x i8> @ashr_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {2263; CHECK-LABEL: ashr_nxv16i8_y:2264; CHECK: // %bb.0: // %entry2265; CHECK-NEXT: ptrue p0.b2266; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #02267; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b2268; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b2269; CHECK-NEXT: ret2270entry:2271 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer2272 %a = ashr <vscale x 16 x i8> %x, %y2273 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y2274 ret <vscale x 16 x i8> %b2275}2276 2277define <vscale x 2 x i64> @lshr_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {2278; CHECK-LABEL: lshr_nxv2i64_y:2279; CHECK: // %bb.0: // %entry2280; CHECK-NEXT: ptrue p0.d2281; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #02282; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d2283; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d2284; CHECK-NEXT: ret2285entry:2286 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer2287 %a = lshr <vscale x 2 x i64> %x, %y2288 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y2289 ret <vscale x 2 x i64> %b2290}2291 2292define <vscale x 4 x i32> @lshr_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {2293; CHECK-LABEL: lshr_nxv4i32_y:2294; CHECK: // %bb.0: // %entry2295; CHECK-NEXT: ptrue p0.s2296; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #02297; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s2298; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s2299; CHECK-NEXT: ret2300entry:2301 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer2302 %a = lshr <vscale x 4 x i32> %x, %y2303 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y2304 ret <vscale x 4 x i32> %b2305}2306 2307define <vscale x 8 x i16> @lshr_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {2308; CHECK-LABEL: lshr_nxv8i16_y:2309; CHECK: // %bb.0: // %entry2310; CHECK-NEXT: ptrue p0.h2311; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #02312; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h2313; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h2314; CHECK-NEXT: ret2315entry:2316 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer2317 %a = lshr <vscale x 8 x i16> %x, %y2318 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y2319 ret <vscale x 8 x i16> %b2320}2321 2322define <vscale x 16 x i8> @lshr_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {2323; CHECK-LABEL: lshr_nxv16i8_y:2324; CHECK: // %bb.0: // %entry2325; CHECK-NEXT: ptrue p0.b2326; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #02327; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b2328; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b2329; CHECK-NEXT: ret2330entry:2331 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer2332 %a = lshr <vscale x 16 x i8> %x, %y2333 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y2334 ret <vscale x 16 x i8> %b2335}2336 2337define <vscale x 2 x i64> @mla_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {2338; CHECK-LABEL: mla_nxv2i64_y:2339; CHECK: // %bb.0: // %entry2340; CHECK-NEXT: ptrue p0.d2341; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, #02342; CHECK-NEXT: mad z1.d, p0/m, z2.d, z0.d2343; CHECK-NEXT: mov z0.d, z1.d2344; CHECK-NEXT: ret2345entry:2346 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer2347 %m = mul <vscale x 2 x i64> %y, %z2348 %a = add <vscale x 2 x i64> %x, %m2349 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y2350 ret <vscale x 2 x i64> %b2351}2352 2353define <vscale x 4 x i32> @mla_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {2354; CHECK-LABEL: mla_nxv4i32_y:2355; CHECK: // %bb.0: // %entry2356; CHECK-NEXT: ptrue p0.s2357; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, #02358; CHECK-NEXT: mad z1.s, p0/m, z2.s, z0.s2359; CHECK-NEXT: mov z0.d, z1.d2360; CHECK-NEXT: ret2361entry:2362 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer2363 %m = mul <vscale x 4 x i32> %y, %z2364 %a = add <vscale x 4 x i32> %x, %m2365 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y2366 ret <vscale x 4 x i32> %b2367}2368 2369define <vscale x 8 x i16> @mla_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {2370; CHECK-LABEL: mla_nxv8i16_y:2371; CHECK: // %bb.0: // %entry2372; CHECK-NEXT: ptrue p0.h2373; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, #02374; CHECK-NEXT: mad z1.h, p0/m, z2.h, z0.h2375; CHECK-NEXT: mov z0.d, z1.d2376; CHECK-NEXT: ret2377entry:2378 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer2379 %m = mul <vscale x 8 x i16> %y, %z2380 %a = add <vscale x 8 x i16> %x, %m2381 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y2382 ret <vscale x 8 x i16> %b2383}2384 2385define <vscale x 16 x i8> @mla_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {2386; CHECK-LABEL: mla_nxv16i8_y:2387; CHECK: // %bb.0: // %entry2388; CHECK-NEXT: ptrue p0.b2389; CHECK-NEXT: cmpgt p0.b, p0/z, z3.b, #02390; CHECK-NEXT: mad z1.b, p0/m, z2.b, z0.b2391; CHECK-NEXT: mov z0.d, z1.d2392; CHECK-NEXT: ret2393entry:2394 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer2395 %m = mul <vscale x 16 x i8> %y, %z2396 %a = add <vscale x 16 x i8> %x, %m2397 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y2398 ret <vscale x 16 x i8> %b2399}2400 2401define <vscale x 2 x i64> @mls_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {2402; CHECK-LABEL: mls_nxv2i64_y:2403; CHECK: // %bb.0: // %entry2404; CHECK-NEXT: ptrue p0.d2405; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, #02406; CHECK-NEXT: msb z1.d, p0/m, z0.d, z2.d2407; CHECK-NEXT: mov z0.d, z1.d2408; CHECK-NEXT: ret2409entry:2410 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer2411 %m = mul <vscale x 2 x i64> %x, %y2412 %a = sub <vscale x 2 x i64> %z, %m2413 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y2414 ret <vscale x 2 x i64> %b2415}2416 2417define <vscale x 4 x i32> @mls_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {2418; CHECK-LABEL: mls_nxv4i32_y:2419; CHECK: // %bb.0: // %entry2420; CHECK-NEXT: ptrue p0.s2421; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, #02422; CHECK-NEXT: msb z1.s, p0/m, z0.s, z2.s2423; CHECK-NEXT: mov z0.d, z1.d2424; CHECK-NEXT: ret2425entry:2426 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer2427 %m = mul <vscale x 4 x i32> %x, %y2428 %a = sub <vscale x 4 x i32> %z, %m2429 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y2430 ret <vscale x 4 x i32> %b2431}2432 2433define <vscale x 8 x i16> @mls_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {2434; CHECK-LABEL: mls_nxv8i16_y:2435; CHECK: // %bb.0: // %entry2436; CHECK-NEXT: ptrue p0.h2437; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, #02438; CHECK-NEXT: msb z1.h, p0/m, z0.h, z2.h2439; CHECK-NEXT: mov z0.d, z1.d2440; CHECK-NEXT: ret2441entry:2442 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer2443 %m = mul <vscale x 8 x i16> %x, %y2444 %a = sub <vscale x 8 x i16> %z, %m2445 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y2446 ret <vscale x 8 x i16> %b2447}2448 2449define <vscale x 16 x i8> @mls_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {2450; CHECK-LABEL: mls_nxv16i8_y:2451; CHECK: // %bb.0: // %entry2452; CHECK-NEXT: ptrue p0.b2453; CHECK-NEXT: cmpgt p0.b, p0/z, z3.b, #02454; CHECK-NEXT: msb z1.b, p0/m, z0.b, z2.b2455; CHECK-NEXT: mov z0.d, z1.d2456; CHECK-NEXT: ret2457entry:2458 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer2459 %m = mul <vscale x 16 x i8> %x, %y2460 %a = sub <vscale x 16 x i8> %z, %m2461 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y2462 ret <vscale x 16 x i8> %b2463}2464 2465define <vscale x 4 x float> @fadd_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {2466; CHECK-LABEL: fadd_nxv4f32_y:2467; CHECK: // %bb.0: // %entry2468; CHECK-NEXT: ptrue p0.s2469; CHECK-NEXT: fadd z0.s, z0.s, z1.s2470; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.02471; CHECK-NEXT: mov z0.s, p0/m, z1.s2472; CHECK-NEXT: ret2473entry:2474 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer2475 %a = fadd <vscale x 4 x float> %x, %y2476 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y2477 ret <vscale x 4 x float> %b2478}2479 2480define <vscale x 8 x half> @fadd_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {2481; CHECK-LABEL: fadd_nxv8f16_y:2482; CHECK: // %bb.0: // %entry2483; CHECK-NEXT: ptrue p0.h2484; CHECK-NEXT: fadd z0.h, z0.h, z1.h2485; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.02486; CHECK-NEXT: mov z0.h, p0/m, z1.h2487; CHECK-NEXT: ret2488entry:2489 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer2490 %a = fadd <vscale x 8 x half> %x, %y2491 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y2492 ret <vscale x 8 x half> %b2493}2494 2495define <vscale x 2 x double> @fadd_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {2496; CHECK-LABEL: fadd_nxv2f64_y:2497; CHECK: // %bb.0: // %entry2498; CHECK-NEXT: ptrue p0.d2499; CHECK-NEXT: fadd z0.d, z0.d, z1.d2500; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.02501; CHECK-NEXT: mov z0.d, p0/m, z1.d2502; CHECK-NEXT: ret2503entry:2504 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer2505 %a = fadd <vscale x 2 x double> %x, %y2506 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y2507 ret <vscale x 2 x double> %b2508}2509 2510define <vscale x 4 x float> @fsub_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {2511; CHECK-LABEL: fsub_nxv4f32_y:2512; CHECK: // %bb.0: // %entry2513; CHECK-NEXT: ptrue p0.s2514; CHECK-NEXT: fsub z0.s, z0.s, z1.s2515; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.02516; CHECK-NEXT: mov z0.s, p0/m, z1.s2517; CHECK-NEXT: ret2518entry:2519 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer2520 %a = fsub <vscale x 4 x float> %x, %y2521 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y2522 ret <vscale x 4 x float> %b2523}2524 2525define <vscale x 8 x half> @fsub_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {2526; CHECK-LABEL: fsub_nxv8f16_y:2527; CHECK: // %bb.0: // %entry2528; CHECK-NEXT: ptrue p0.h2529; CHECK-NEXT: fsub z0.h, z0.h, z1.h2530; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.02531; CHECK-NEXT: mov z0.h, p0/m, z1.h2532; CHECK-NEXT: ret2533entry:2534 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer2535 %a = fsub <vscale x 8 x half> %x, %y2536 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y2537 ret <vscale x 8 x half> %b2538}2539 2540define <vscale x 2 x double> @fsub_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {2541; CHECK-LABEL: fsub_nxv2f64_y:2542; CHECK: // %bb.0: // %entry2543; CHECK-NEXT: ptrue p0.d2544; CHECK-NEXT: fsub z0.d, z0.d, z1.d2545; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.02546; CHECK-NEXT: mov z0.d, p0/m, z1.d2547; CHECK-NEXT: ret2548entry:2549 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer2550 %a = fsub <vscale x 2 x double> %x, %y2551 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y2552 ret <vscale x 2 x double> %b2553}2554 2555define <vscale x 4 x float> @fmul_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {2556; CHECK-LABEL: fmul_nxv4f32_y:2557; CHECK: // %bb.0: // %entry2558; CHECK-NEXT: ptrue p0.s2559; CHECK-NEXT: fmul z0.s, z0.s, z1.s2560; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.02561; CHECK-NEXT: mov z0.s, p0/m, z1.s2562; CHECK-NEXT: ret2563entry:2564 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer2565 %a = fmul <vscale x 4 x float> %x, %y2566 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y2567 ret <vscale x 4 x float> %b2568}2569 2570define <vscale x 8 x half> @fmul_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {2571; CHECK-LABEL: fmul_nxv8f16_y:2572; CHECK: // %bb.0: // %entry2573; CHECK-NEXT: ptrue p0.h2574; CHECK-NEXT: fmul z0.h, z0.h, z1.h2575; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.02576; CHECK-NEXT: mov z0.h, p0/m, z1.h2577; CHECK-NEXT: ret2578entry:2579 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer2580 %a = fmul <vscale x 8 x half> %x, %y2581 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y2582 ret <vscale x 8 x half> %b2583}2584 2585define <vscale x 2 x double> @fmul_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {2586; CHECK-LABEL: fmul_nxv2f64_y:2587; CHECK: // %bb.0: // %entry2588; CHECK-NEXT: ptrue p0.d2589; CHECK-NEXT: fmul z0.d, z0.d, z1.d2590; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.02591; CHECK-NEXT: mov z0.d, p0/m, z1.d2592; CHECK-NEXT: ret2593entry:2594 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer2595 %a = fmul <vscale x 2 x double> %x, %y2596 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y2597 ret <vscale x 2 x double> %b2598}2599 2600define <vscale x 4 x float> @fdiv_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {2601; CHECK-LABEL: fdiv_nxv4f32_y:2602; CHECK: // %bb.0: // %entry2603; CHECK-NEXT: ptrue p0.s2604; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s2605; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.02606; CHECK-NEXT: mov z0.s, p0/m, z1.s2607; CHECK-NEXT: ret2608entry:2609 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer2610 %a = fdiv <vscale x 4 x float> %x, %y2611 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y2612 ret <vscale x 4 x float> %b2613}2614 2615define <vscale x 8 x half> @fdiv_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {2616; CHECK-LABEL: fdiv_nxv8f16_y:2617; CHECK: // %bb.0: // %entry2618; CHECK-NEXT: ptrue p0.h2619; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h2620; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.02621; CHECK-NEXT: mov z0.h, p0/m, z1.h2622; CHECK-NEXT: ret2623entry:2624 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer2625 %a = fdiv <vscale x 8 x half> %x, %y2626 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y2627 ret <vscale x 8 x half> %b2628}2629 2630define <vscale x 2 x double> @fdiv_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {2631; CHECK-LABEL: fdiv_nxv2f64_y:2632; CHECK: // %bb.0: // %entry2633; CHECK-NEXT: ptrue p0.d2634; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d2635; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.02636; CHECK-NEXT: mov z0.d, p0/m, z1.d2637; CHECK-NEXT: ret2638entry:2639 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer2640 %a = fdiv <vscale x 2 x double> %x, %y2641 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y2642 ret <vscale x 2 x double> %b2643}2644 2645define <vscale x 4 x float> @minnum_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {2646; CHECK-LABEL: minnum_nxv4f32_y:2647; CHECK: // %bb.0: // %entry2648; CHECK-NEXT: ptrue p0.s2649; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.02650; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s2651; CHECK-NEXT: mov z0.s, p1/m, z1.s2652; CHECK-NEXT: ret2653entry:2654 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer2655 %a = call <vscale x 4 x float> @llvm.minnum.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y)2656 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y2657 ret <vscale x 4 x float> %b2658}2659 2660define <vscale x 8 x half> @minnum_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {2661; CHECK-LABEL: minnum_nxv8f16_y:2662; CHECK: // %bb.0: // %entry2663; CHECK-NEXT: ptrue p0.h2664; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.02665; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h2666; CHECK-NEXT: mov z0.h, p1/m, z1.h2667; CHECK-NEXT: ret2668entry:2669 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer2670 %a = call <vscale x 8 x half> @llvm.minnum.nxv8f16(<vscale x 8 x half> %x, <vscale x 8 x half> %y)2671 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y2672 ret <vscale x 8 x half> %b2673}2674 2675define <vscale x 2 x double> @minnum_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {2676; CHECK-LABEL: minnum_nxv2f64_y:2677; CHECK: // %bb.0: // %entry2678; CHECK-NEXT: ptrue p0.d2679; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.02680; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d2681; CHECK-NEXT: mov z0.d, p1/m, z1.d2682; CHECK-NEXT: ret2683entry:2684 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer2685 %a = call <vscale x 2 x double> @llvm.minnum.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y)2686 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y2687 ret <vscale x 2 x double> %b2688}2689 2690define <vscale x 4 x float> @maxnum_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {2691; CHECK-LABEL: maxnum_nxv4f32_y:2692; CHECK: // %bb.0: // %entry2693; CHECK-NEXT: ptrue p0.s2694; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.02695; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s2696; CHECK-NEXT: mov z0.s, p1/m, z1.s2697; CHECK-NEXT: ret2698entry:2699 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer2700 %a = call <vscale x 4 x float> @llvm.maxnum.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y)2701 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y2702 ret <vscale x 4 x float> %b2703}2704 2705define <vscale x 8 x half> @maxnum_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {2706; CHECK-LABEL: maxnum_nxv8f16_y:2707; CHECK: // %bb.0: // %entry2708; CHECK-NEXT: ptrue p0.h2709; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.02710; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h2711; CHECK-NEXT: mov z0.h, p1/m, z1.h2712; CHECK-NEXT: ret2713entry:2714 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer2715 %a = call <vscale x 8 x half> @llvm.maxnum.nxv8f16(<vscale x 8 x half> %x, <vscale x 8 x half> %y)2716 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y2717 ret <vscale x 8 x half> %b2718}2719 2720define <vscale x 2 x double> @maxnum_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {2721; CHECK-LABEL: maxnum_nxv2f64_y:2722; CHECK: // %bb.0: // %entry2723; CHECK-NEXT: ptrue p0.d2724; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.02725; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d2726; CHECK-NEXT: mov z0.d, p1/m, z1.d2727; CHECK-NEXT: ret2728entry:2729 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer2730 %a = call <vscale x 2 x double> @llvm.maxnum.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y)2731 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y2732 ret <vscale x 2 x double> %b2733}2734 2735define <vscale x 4 x float> @minimum_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {2736; CHECK-LABEL: minimum_nxv4f32_y:2737; CHECK: // %bb.0: // %entry2738; CHECK-NEXT: ptrue p0.s2739; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.02740; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s2741; CHECK-NEXT: mov z0.s, p1/m, z1.s2742; CHECK-NEXT: ret2743entry:2744 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer2745 %a = call <vscale x 4 x float> @llvm.minimum.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y)2746 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y2747 ret <vscale x 4 x float> %b2748}2749 2750define <vscale x 8 x half> @minimum_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {2751; CHECK-LABEL: minimum_nxv8f16_y:2752; CHECK: // %bb.0: // %entry2753; CHECK-NEXT: ptrue p0.h2754; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.02755; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h2756; CHECK-NEXT: mov z0.h, p1/m, z1.h2757; CHECK-NEXT: ret2758entry:2759 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer2760 %a = call <vscale x 8 x half> @llvm.minimum.nxv8f16(<vscale x 8 x half> %x, <vscale x 8 x half> %y)2761 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y2762 ret <vscale x 8 x half> %b2763}2764 2765define <vscale x 2 x double> @minimum_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {2766; CHECK-LABEL: minimum_nxv2f64_y:2767; CHECK: // %bb.0: // %entry2768; CHECK-NEXT: ptrue p0.d2769; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.02770; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d2771; CHECK-NEXT: mov z0.d, p1/m, z1.d2772; CHECK-NEXT: ret2773entry:2774 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer2775 %a = call <vscale x 2 x double> @llvm.minimum.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y)2776 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y2777 ret <vscale x 2 x double> %b2778}2779 2780define <vscale x 4 x float> @maximum_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {2781; CHECK-LABEL: maximum_nxv4f32_y:2782; CHECK: // %bb.0: // %entry2783; CHECK-NEXT: ptrue p0.s2784; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.02785; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s2786; CHECK-NEXT: mov z0.s, p1/m, z1.s2787; CHECK-NEXT: ret2788entry:2789 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer2790 %a = call <vscale x 4 x float> @llvm.maximum.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y)2791 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y2792 ret <vscale x 4 x float> %b2793}2794 2795define <vscale x 8 x half> @maximum_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {2796; CHECK-LABEL: maximum_nxv8f16_y:2797; CHECK: // %bb.0: // %entry2798; CHECK-NEXT: ptrue p0.h2799; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.02800; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h2801; CHECK-NEXT: mov z0.h, p1/m, z1.h2802; CHECK-NEXT: ret2803entry:2804 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer2805 %a = call <vscale x 8 x half> @llvm.maximum.nxv8f16(<vscale x 8 x half> %x, <vscale x 8 x half> %y)2806 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y2807 ret <vscale x 8 x half> %b2808}2809 2810define <vscale x 2 x double> @maximum_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {2811; CHECK-LABEL: maximum_nxv2f64_y:2812; CHECK: // %bb.0: // %entry2813; CHECK-NEXT: ptrue p0.d2814; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.02815; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d2816; CHECK-NEXT: mov z0.d, p1/m, z1.d2817; CHECK-NEXT: ret2818entry:2819 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer2820 %a = call <vscale x 2 x double> @llvm.maximum.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y)2821 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y2822 ret <vscale x 2 x double> %b2823}2824 2825define <vscale x 4 x float> @fmai_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {2826; CHECK-LABEL: fmai_nxv4f32_y:2827; CHECK: // %bb.0: // %entry2828; CHECK-NEXT: ptrue p0.s2829; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.02830; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s2831; CHECK-NEXT: mov z0.s, p1/m, z1.s2832; CHECK-NEXT: ret2833entry:2834 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer2835 %a = call <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %x)2836 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y2837 ret <vscale x 4 x float> %b2838}2839 2840define <vscale x 8 x half> @fmai_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {2841; CHECK-LABEL: fmai_nxv8f16_y:2842; CHECK: // %bb.0: // %entry2843; CHECK-NEXT: ptrue p0.h2844; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.02845; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h2846; CHECK-NEXT: mov z0.h, p1/m, z1.h2847; CHECK-NEXT: ret2848entry:2849 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer2850 %a = call <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %x)2851 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y2852 ret <vscale x 8 x half> %b2853}2854 2855define <vscale x 2 x double> @fmai_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {2856; CHECK-LABEL: fmai_nxv2f64_y:2857; CHECK: // %bb.0: // %entry2858; CHECK-NEXT: ptrue p0.d2859; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.02860; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d2861; CHECK-NEXT: mov z0.d, p1/m, z1.d2862; CHECK-NEXT: ret2863entry:2864 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer2865 %a = call <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %x)2866 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y2867 ret <vscale x 2 x double> %b2868}2869 2870define <vscale x 4 x float> @fma_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {2871; CHECK-LABEL: fma_nxv4f32_y:2872; CHECK: // %bb.0: // %entry2873; CHECK-NEXT: ptrue p0.s2874; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.02875; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s2876; CHECK-NEXT: mov z0.s, p1/m, z1.s2877; CHECK-NEXT: ret2878entry:2879 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer2880 %m = fmul fast <vscale x 4 x float> %y, %z2881 %a = fadd fast <vscale x 4 x float> %m, %x2882 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y2883 ret <vscale x 4 x float> %b2884}2885 2886define <vscale x 8 x half> @fma_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {2887; CHECK-LABEL: fma_nxv8f16_y:2888; CHECK: // %bb.0: // %entry2889; CHECK-NEXT: ptrue p0.h2890; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.02891; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h2892; CHECK-NEXT: mov z0.h, p1/m, z1.h2893; CHECK-NEXT: ret2894entry:2895 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer2896 %m = fmul fast <vscale x 8 x half> %y, %z2897 %a = fadd fast <vscale x 8 x half> %m, %x2898 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y2899 ret <vscale x 8 x half> %b2900}2901 2902define <vscale x 2 x double> @fma_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {2903; CHECK-LABEL: fma_nxv2f64_y:2904; CHECK: // %bb.0: // %entry2905; CHECK-NEXT: ptrue p0.d2906; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.02907; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d2908; CHECK-NEXT: mov z0.d, p1/m, z1.d2909; CHECK-NEXT: ret2910entry:2911 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer2912 %m = fmul fast <vscale x 2 x double> %y, %z2913 %a = fadd fast <vscale x 2 x double> %m, %x2914 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y2915 ret <vscale x 2 x double> %b2916}2917 2918 2919define <vscale x 4 x i32> @mul_use_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n, ptr %p) {2920; CHECK-LABEL: mul_use_nxv4i32_x:2921; CHECK: // %bb.0: // %entry2922; CHECK-NEXT: ptrue p0.s2923; CHECK-NEXT: mul z1.s, z0.s, z1.s2924; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #02925; CHECK-NEXT: str z1, [x0]2926; CHECK-NEXT: mov z0.s, p0/m, z1.s2927; CHECK-NEXT: ret2928entry:2929 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer2930 %a = mul <vscale x 4 x i32> %x, %y2931 store <vscale x 4 x i32> %a, ptr %p2932 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x2933 ret <vscale x 4 x i32> %b2934}2935 2936declare <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)2937declare <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)2938declare <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)2939declare <vscale x 2 x double> @llvm.minnum.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>)2940declare <vscale x 4 x float> @llvm.minnum.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)2941declare <vscale x 8 x half> @llvm.minnum.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>)2942declare <vscale x 2 x double> @llvm.maxnum.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>)2943declare <vscale x 4 x float> @llvm.maxnum.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)2944declare <vscale x 8 x half> @llvm.maxnum.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>)2945declare <vscale x 2 x double> @llvm.minimum.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>)2946declare <vscale x 4 x float> @llvm.minimum.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)2947declare <vscale x 8 x half> @llvm.minimum.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>)2948declare <vscale x 2 x double> @llvm.maximum.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>)2949declare <vscale x 4 x float> @llvm.maximum.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)2950declare <vscale x 8 x half> @llvm.maximum.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>)2951