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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64 -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s3 4define <vscale x 2 x i64> @add_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {5; CHECK-LABEL: add_nxv2i64_x:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: ptrue p0.d8; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #09; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d10; CHECK-NEXT: ret11entry:12 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer13 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer14 %b = add <vscale x 2 x i64> %a, %x15 ret <vscale x 2 x i64> %b16}17 18define <vscale x 4 x i32> @add_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {19; CHECK-LABEL: add_nxv4i32_x:20; CHECK: // %bb.0: // %entry21; CHECK-NEXT: ptrue p0.s22; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #023; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s24; CHECK-NEXT: ret25entry:26 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer27 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer28 %b = add <vscale x 4 x i32> %a, %x29 ret <vscale x 4 x i32> %b30}31 32define <vscale x 8 x i16> @add_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {33; CHECK-LABEL: add_nxv8i16_x:34; CHECK: // %bb.0: // %entry35; CHECK-NEXT: ptrue p0.h36; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #037; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h38; CHECK-NEXT: ret39entry:40 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer41 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer42 %b = add <vscale x 8 x i16> %a, %x43 ret <vscale x 8 x i16> %b44}45 46define <vscale x 16 x i8> @add_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {47; CHECK-LABEL: add_nxv16i8_x:48; CHECK: // %bb.0: // %entry49; CHECK-NEXT: ptrue p0.b50; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #051; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b52; CHECK-NEXT: ret53entry:54 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer55 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer56 %b = add <vscale x 16 x i8> %a, %x57 ret <vscale x 16 x i8> %b58}59 60define <vscale x 2 x i64> @sub_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {61; CHECK-LABEL: sub_nxv2i64_x:62; CHECK: // %bb.0: // %entry63; CHECK-NEXT: ptrue p0.d64; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #065; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d66; CHECK-NEXT: ret67entry:68 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer69 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer70 %b = sub <vscale x 2 x i64> %x, %a71 ret <vscale x 2 x i64> %b72}73 74define <vscale x 4 x i32> @sub_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {75; CHECK-LABEL: sub_nxv4i32_x:76; CHECK: // %bb.0: // %entry77; CHECK-NEXT: ptrue p0.s78; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #079; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s80; CHECK-NEXT: ret81entry:82 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer83 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer84 %b = sub <vscale x 4 x i32> %x, %a85 ret <vscale x 4 x i32> %b86}87 88define <vscale x 8 x i16> @sub_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {89; CHECK-LABEL: sub_nxv8i16_x:90; CHECK: // %bb.0: // %entry91; CHECK-NEXT: ptrue p0.h92; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #093; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h94; CHECK-NEXT: ret95entry:96 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer97 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer98 %b = sub <vscale x 8 x i16> %x, %a99 ret <vscale x 8 x i16> %b100}101 102define <vscale x 16 x i8> @sub_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {103; CHECK-LABEL: sub_nxv16i8_x:104; CHECK: // %bb.0: // %entry105; CHECK-NEXT: ptrue p0.b106; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0107; CHECK-NEXT: sub z0.b, p0/m, z0.b, z1.b108; CHECK-NEXT: ret109entry:110 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer111 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer112 %b = sub <vscale x 16 x i8> %x, %a113 ret <vscale x 16 x i8> %b114}115 116define <vscale x 2 x i64> @mul_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {117; CHECK-LABEL: mul_nxv2i64_x:118; CHECK: // %bb.0: // %entry119; CHECK-NEXT: ptrue p0.d120; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0121; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d122; CHECK-NEXT: ret123entry:124 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer125 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> splat (i64 1)126 %b = mul <vscale x 2 x i64> %a, %x127 ret <vscale x 2 x i64> %b128}129 130define <vscale x 4 x i32> @mul_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {131; CHECK-LABEL: mul_nxv4i32_x:132; CHECK: // %bb.0: // %entry133; CHECK-NEXT: ptrue p0.s134; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0135; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s136; CHECK-NEXT: ret137entry:138 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer139 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> splat (i32 1)140 %b = mul <vscale x 4 x i32> %a, %x141 ret <vscale x 4 x i32> %b142}143 144define <vscale x 8 x i16> @mul_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {145; CHECK-LABEL: mul_nxv8i16_x:146; CHECK: // %bb.0: // %entry147; CHECK-NEXT: ptrue p0.h148; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0149; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h150; CHECK-NEXT: ret151entry:152 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer153 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> splat (i16 1)154 %b = mul <vscale x 8 x i16> %a, %x155 ret <vscale x 8 x i16> %b156}157 158define <vscale x 16 x i8> @mul_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {159; CHECK-LABEL: mul_nxv16i8_x:160; CHECK: // %bb.0: // %entry161; CHECK-NEXT: ptrue p0.b162; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0163; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b164; CHECK-NEXT: ret165entry:166 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer167 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> splat (i8 1)168 %b = mul <vscale x 16 x i8> %a, %x169 ret <vscale x 16 x i8> %b170}171 172define <vscale x 2 x i64> @and_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {173; CHECK-LABEL: and_nxv2i64_x:174; CHECK: // %bb.0: // %entry175; CHECK-NEXT: ptrue p0.d176; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0177; CHECK-NEXT: and z0.d, p0/m, z0.d, z1.d178; CHECK-NEXT: ret179entry:180 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer181 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> splat (i64 -1)182 %b = and <vscale x 2 x i64> %a, %x183 ret <vscale x 2 x i64> %b184}185 186define <vscale x 4 x i32> @and_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {187; CHECK-LABEL: and_nxv4i32_x:188; CHECK: // %bb.0: // %entry189; CHECK-NEXT: ptrue p0.s190; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0191; CHECK-NEXT: and z0.s, p0/m, z0.s, z1.s192; CHECK-NEXT: ret193entry:194 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer195 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> splat (i32 -1)196 %b = and <vscale x 4 x i32> %a, %x197 ret <vscale x 4 x i32> %b198}199 200define <vscale x 8 x i16> @and_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {201; CHECK-LABEL: and_nxv8i16_x:202; CHECK: // %bb.0: // %entry203; CHECK-NEXT: ptrue p0.h204; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0205; CHECK-NEXT: and z0.h, p0/m, z0.h, z1.h206; CHECK-NEXT: ret207entry:208 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer209 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> splat (i16 -1)210 %b = and <vscale x 8 x i16> %a, %x211 ret <vscale x 8 x i16> %b212}213 214define <vscale x 16 x i8> @and_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {215; CHECK-LABEL: and_nxv16i8_x:216; CHECK: // %bb.0: // %entry217; CHECK-NEXT: ptrue p0.b218; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0219; CHECK-NEXT: and z0.b, p0/m, z0.b, z1.b220; CHECK-NEXT: ret221entry:222 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer223 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> splat (i8 -1)224 %b = and <vscale x 16 x i8> %a, %x225 ret <vscale x 16 x i8> %b226}227 228define <vscale x 2 x i64> @or_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {229; CHECK-LABEL: or_nxv2i64_x:230; CHECK: // %bb.0: // %entry231; CHECK-NEXT: ptrue p0.d232; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0233; CHECK-NEXT: orr z0.d, p0/m, z0.d, z1.d234; CHECK-NEXT: ret235entry:236 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer237 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer238 %b = or <vscale x 2 x i64> %a, %x239 ret <vscale x 2 x i64> %b240}241 242define <vscale x 4 x i32> @or_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {243; CHECK-LABEL: or_nxv4i32_x:244; CHECK: // %bb.0: // %entry245; CHECK-NEXT: ptrue p0.s246; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0247; CHECK-NEXT: orr z0.s, p0/m, z0.s, z1.s248; CHECK-NEXT: ret249entry:250 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer251 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer252 %b = or <vscale x 4 x i32> %a, %x253 ret <vscale x 4 x i32> %b254}255 256define <vscale x 8 x i16> @or_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {257; CHECK-LABEL: or_nxv8i16_x:258; CHECK: // %bb.0: // %entry259; CHECK-NEXT: ptrue p0.h260; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0261; CHECK-NEXT: orr z0.h, p0/m, z0.h, z1.h262; CHECK-NEXT: ret263entry:264 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer265 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer266 %b = or <vscale x 8 x i16> %a, %x267 ret <vscale x 8 x i16> %b268}269 270define <vscale x 16 x i8> @or_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {271; CHECK-LABEL: or_nxv16i8_x:272; CHECK: // %bb.0: // %entry273; CHECK-NEXT: ptrue p0.b274; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0275; CHECK-NEXT: orr z0.b, p0/m, z0.b, z1.b276; CHECK-NEXT: ret277entry:278 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer279 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer280 %b = or <vscale x 16 x i8> %a, %x281 ret <vscale x 16 x i8> %b282}283 284define <vscale x 2 x i64> @xor_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {285; CHECK-LABEL: xor_nxv2i64_x:286; CHECK: // %bb.0: // %entry287; CHECK-NEXT: ptrue p0.d288; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0289; CHECK-NEXT: eor z0.d, p0/m, z0.d, z1.d290; CHECK-NEXT: ret291entry:292 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer293 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer294 %b = xor <vscale x 2 x i64> %a, %x295 ret <vscale x 2 x i64> %b296}297 298define <vscale x 4 x i32> @xor_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {299; CHECK-LABEL: xor_nxv4i32_x:300; CHECK: // %bb.0: // %entry301; CHECK-NEXT: ptrue p0.s302; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0303; CHECK-NEXT: eor z0.s, p0/m, z0.s, z1.s304; CHECK-NEXT: ret305entry:306 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer307 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer308 %b = xor <vscale x 4 x i32> %a, %x309 ret <vscale x 4 x i32> %b310}311 312define <vscale x 8 x i16> @xor_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {313; CHECK-LABEL: xor_nxv8i16_x:314; CHECK: // %bb.0: // %entry315; CHECK-NEXT: ptrue p0.h316; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0317; CHECK-NEXT: eor z0.h, p0/m, z0.h, z1.h318; CHECK-NEXT: ret319entry:320 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer321 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer322 %b = xor <vscale x 8 x i16> %a, %x323 ret <vscale x 8 x i16> %b324}325 326define <vscale x 16 x i8> @xor_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {327; CHECK-LABEL: xor_nxv16i8_x:328; CHECK: // %bb.0: // %entry329; CHECK-NEXT: ptrue p0.b330; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0331; CHECK-NEXT: eor z0.b, p0/m, z0.b, z1.b332; CHECK-NEXT: ret333entry:334 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer335 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer336 %b = xor <vscale x 16 x i8> %a, %x337 ret <vscale x 16 x i8> %b338}339 340define <vscale x 2 x i64> @shl_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {341; CHECK-LABEL: shl_nxv2i64_x:342; CHECK: // %bb.0: // %entry343; CHECK-NEXT: ptrue p0.d344; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0345; CHECK-NEXT: lslr z1.d, p0/m, z1.d, z0.d346; CHECK-NEXT: mov z0.d, p1/m, z1.d347; CHECK-NEXT: ret348entry:349 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer350 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer351 %b = shl <vscale x 2 x i64> %x, %a352 ret <vscale x 2 x i64> %b353}354 355define <vscale x 4 x i32> @shl_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {356; CHECK-LABEL: shl_nxv4i32_x:357; CHECK: // %bb.0: // %entry358; CHECK-NEXT: ptrue p0.s359; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0360; CHECK-NEXT: lslr z1.s, p0/m, z1.s, z0.s361; CHECK-NEXT: mov z0.s, p1/m, z1.s362; CHECK-NEXT: ret363entry:364 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer365 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer366 %b = shl <vscale x 4 x i32> %x, %a367 ret <vscale x 4 x i32> %b368}369 370define <vscale x 8 x i16> @shl_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {371; CHECK-LABEL: shl_nxv8i16_x:372; CHECK: // %bb.0: // %entry373; CHECK-NEXT: ptrue p0.h374; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0375; CHECK-NEXT: lslr z1.h, p0/m, z1.h, z0.h376; CHECK-NEXT: mov z0.h, p1/m, z1.h377; CHECK-NEXT: ret378entry:379 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer380 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer381 %b = shl <vscale x 8 x i16> %x, %a382 ret <vscale x 8 x i16> %b383}384 385define <vscale x 16 x i8> @shl_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {386; CHECK-LABEL: shl_nxv16i8_x:387; CHECK: // %bb.0: // %entry388; CHECK-NEXT: ptrue p0.b389; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0390; CHECK-NEXT: lslr z1.b, p0/m, z1.b, z0.b391; CHECK-NEXT: mov z0.b, p1/m, z1.b392; CHECK-NEXT: ret393entry:394 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer395 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer396 %b = shl <vscale x 16 x i8> %x, %a397 ret <vscale x 16 x i8> %b398}399 400define <vscale x 2 x i64> @ashr_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {401; CHECK-LABEL: ashr_nxv2i64_x:402; CHECK: // %bb.0: // %entry403; CHECK-NEXT: ptrue p0.d404; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0405; CHECK-NEXT: asrr z1.d, p0/m, z1.d, z0.d406; CHECK-NEXT: mov z0.d, p1/m, z1.d407; CHECK-NEXT: ret408entry:409 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer410 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer411 %b = ashr <vscale x 2 x i64> %x, %a412 ret <vscale x 2 x i64> %b413}414 415define <vscale x 4 x i32> @ashr_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {416; CHECK-LABEL: ashr_nxv4i32_x:417; CHECK: // %bb.0: // %entry418; CHECK-NEXT: ptrue p0.s419; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0420; CHECK-NEXT: asrr z1.s, p0/m, z1.s, z0.s421; CHECK-NEXT: mov z0.s, p1/m, z1.s422; CHECK-NEXT: ret423entry:424 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer425 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer426 %b = ashr <vscale x 4 x i32> %x, %a427 ret <vscale x 4 x i32> %b428}429 430define <vscale x 8 x i16> @ashr_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {431; CHECK-LABEL: ashr_nxv8i16_x:432; CHECK: // %bb.0: // %entry433; CHECK-NEXT: ptrue p0.h434; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0435; CHECK-NEXT: asrr z1.h, p0/m, z1.h, z0.h436; CHECK-NEXT: mov z0.h, p1/m, z1.h437; CHECK-NEXT: ret438entry:439 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer440 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer441 %b = ashr <vscale x 8 x i16> %x, %a442 ret <vscale x 8 x i16> %b443}444 445define <vscale x 16 x i8> @ashr_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {446; CHECK-LABEL: ashr_nxv16i8_x:447; CHECK: // %bb.0: // %entry448; CHECK-NEXT: ptrue p0.b449; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0450; CHECK-NEXT: asrr z1.b, p0/m, z1.b, z0.b451; CHECK-NEXT: mov z0.b, p1/m, z1.b452; CHECK-NEXT: ret453entry:454 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer455 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer456 %b = ashr <vscale x 16 x i8> %x, %a457 ret <vscale x 16 x i8> %b458}459 460define <vscale x 2 x i64> @lshr_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {461; CHECK-LABEL: lshr_nxv2i64_x:462; CHECK: // %bb.0: // %entry463; CHECK-NEXT: ptrue p0.d464; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0465; CHECK-NEXT: lsrr z1.d, p0/m, z1.d, z0.d466; CHECK-NEXT: mov z0.d, p1/m, z1.d467; CHECK-NEXT: ret468entry:469 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer470 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer471 %b = lshr <vscale x 2 x i64> %x, %a472 ret <vscale x 2 x i64> %b473}474 475define <vscale x 4 x i32> @lshr_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {476; CHECK-LABEL: lshr_nxv4i32_x:477; CHECK: // %bb.0: // %entry478; CHECK-NEXT: ptrue p0.s479; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0480; CHECK-NEXT: lsrr z1.s, p0/m, z1.s, z0.s481; CHECK-NEXT: mov z0.s, p1/m, z1.s482; CHECK-NEXT: ret483entry:484 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer485 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer486 %b = lshr <vscale x 4 x i32> %x, %a487 ret <vscale x 4 x i32> %b488}489 490define <vscale x 8 x i16> @lshr_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {491; CHECK-LABEL: lshr_nxv8i16_x:492; CHECK: // %bb.0: // %entry493; CHECK-NEXT: ptrue p0.h494; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0495; CHECK-NEXT: lsrr z1.h, p0/m, z1.h, z0.h496; CHECK-NEXT: mov z0.h, p1/m, z1.h497; CHECK-NEXT: ret498entry:499 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer500 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer501 %b = lshr <vscale x 8 x i16> %x, %a502 ret <vscale x 8 x i16> %b503}504 505define <vscale x 16 x i8> @lshr_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {506; CHECK-LABEL: lshr_nxv16i8_x:507; CHECK: // %bb.0: // %entry508; CHECK-NEXT: ptrue p0.b509; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0510; CHECK-NEXT: lsrr z1.b, p0/m, z1.b, z0.b511; CHECK-NEXT: mov z0.b, p1/m, z1.b512; CHECK-NEXT: ret513entry:514 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer515 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer516 %b = lshr <vscale x 16 x i8> %x, %a517 ret <vscale x 16 x i8> %b518}519 520define <vscale x 2 x i64> @mla_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {521; CHECK-LABEL: mla_nxv2i64_x:522; CHECK: // %bb.0: // %entry523; CHECK-NEXT: ptrue p0.d524; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, #0525; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d526; CHECK-NEXT: ret527entry:528 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer529 %m = mul <vscale x 2 x i64> %y, %z530 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %m, <vscale x 2 x i64> zeroinitializer531 %b = add <vscale x 2 x i64> %a, %x532 ret <vscale x 2 x i64> %b533}534 535define <vscale x 4 x i32> @mla_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {536; CHECK-LABEL: mla_nxv4i32_x:537; CHECK: // %bb.0: // %entry538; CHECK-NEXT: ptrue p0.s539; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, #0540; CHECK-NEXT: mla z0.s, p0/m, z1.s, z2.s541; CHECK-NEXT: ret542entry:543 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer544 %m = mul <vscale x 4 x i32> %y, %z545 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %m, <vscale x 4 x i32> zeroinitializer546 %b = add <vscale x 4 x i32> %a, %x547 ret <vscale x 4 x i32> %b548}549 550define <vscale x 8 x i16> @mla_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {551; CHECK-LABEL: mla_nxv8i16_x:552; CHECK: // %bb.0: // %entry553; CHECK-NEXT: ptrue p0.h554; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, #0555; CHECK-NEXT: mla z0.h, p0/m, z1.h, z2.h556; CHECK-NEXT: ret557entry:558 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer559 %m = mul <vscale x 8 x i16> %y, %z560 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %m, <vscale x 8 x i16> zeroinitializer561 %b = add <vscale x 8 x i16> %a, %x562 ret <vscale x 8 x i16> %b563}564 565define <vscale x 16 x i8> @mla_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {566; CHECK-LABEL: mla_nxv16i8_x:567; CHECK: // %bb.0: // %entry568; CHECK-NEXT: ptrue p0.b569; CHECK-NEXT: cmpgt p0.b, p0/z, z3.b, #0570; CHECK-NEXT: mla z0.b, p0/m, z1.b, z2.b571; CHECK-NEXT: ret572entry:573 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer574 %m = mul <vscale x 16 x i8> %y, %z575 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %m, <vscale x 16 x i8> zeroinitializer576 %b = add <vscale x 16 x i8> %a, %x577 ret <vscale x 16 x i8> %b578}579 580define <vscale x 2 x i64> @mls_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {581; CHECK-LABEL: mls_nxv2i64_x:582; CHECK: // %bb.0: // %entry583; CHECK-NEXT: ptrue p0.d584; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, #0585; CHECK-NEXT: msb z0.d, p0/m, z1.d, z2.d586; CHECK-NEXT: ret587entry:588 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer589 %m = mul <vscale x 2 x i64> %x, %y590 %a = sub <vscale x 2 x i64> %z, %m591 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x592 ret <vscale x 2 x i64> %b593}594 595define <vscale x 4 x i32> @mls_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {596; CHECK-LABEL: mls_nxv4i32_x:597; CHECK: // %bb.0: // %entry598; CHECK-NEXT: ptrue p0.s599; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, #0600; CHECK-NEXT: msb z0.s, p0/m, z1.s, z2.s601; CHECK-NEXT: ret602entry:603 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer604 %m = mul <vscale x 4 x i32> %x, %y605 %a = sub <vscale x 4 x i32> %z, %m606 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x607 ret <vscale x 4 x i32> %b608}609 610define <vscale x 8 x i16> @mls_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {611; CHECK-LABEL: mls_nxv8i16_x:612; CHECK: // %bb.0: // %entry613; CHECK-NEXT: ptrue p0.h614; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, #0615; CHECK-NEXT: msb z0.h, p0/m, z1.h, z2.h616; CHECK-NEXT: ret617entry:618 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer619 %m = mul <vscale x 8 x i16> %x, %y620 %a = sub <vscale x 8 x i16> %z, %m621 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x622 ret <vscale x 8 x i16> %b623}624 625define <vscale x 16 x i8> @mls_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {626; CHECK-LABEL: mls_nxv16i8_x:627; CHECK: // %bb.0: // %entry628; CHECK-NEXT: ptrue p0.b629; CHECK-NEXT: cmpgt p0.b, p0/z, z3.b, #0630; CHECK-NEXT: msb z0.b, p0/m, z1.b, z2.b631; CHECK-NEXT: ret632entry:633 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer634 %m = mul <vscale x 16 x i8> %x, %y635 %a = sub <vscale x 16 x i8> %z, %m636 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x637 ret <vscale x 16 x i8> %b638}639 640define <vscale x 4 x float> @fadd_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {641; CHECK-LABEL: fadd_nxv4f32_x:642; CHECK: // %bb.0: // %entry643; CHECK-NEXT: ptrue p0.s644; CHECK-NEXT: fadd z1.s, z0.s, z1.s645; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.0646; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s647; CHECK-NEXT: ret648entry:649 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer650 %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %y, <vscale x 4 x float> splat (float -0.000000e+00)651 %b = fadd <vscale x 4 x float> %a, %x652 ret <vscale x 4 x float> %b653}654 655define <vscale x 8 x half> @fadd_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {656; CHECK-LABEL: fadd_nxv8f16_x:657; CHECK: // %bb.0: // %entry658; CHECK-NEXT: ptrue p0.h659; CHECK-NEXT: fadd z1.h, z0.h, z1.h660; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.0661; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h662; CHECK-NEXT: ret663entry:664 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer665 %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %y, <vscale x 8 x half> splat (half 0xH8000)666 %b = fadd <vscale x 8 x half> %a, %x667 ret <vscale x 8 x half> %b668}669 670define <vscale x 2 x double> @fadd_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {671; CHECK-LABEL: fadd_nxv2f64_x:672; CHECK: // %bb.0: // %entry673; CHECK-NEXT: ptrue p0.d674; CHECK-NEXT: fadd z1.d, z0.d, z1.d675; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.0676; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d677; CHECK-NEXT: ret678entry:679 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer680 %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %y, <vscale x 2 x double> splat (double -0.000000e+00)681 %b = fadd <vscale x 2 x double> %a, %x682 ret <vscale x 2 x double> %b683}684 685define <vscale x 4 x float> @fsub_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {686; CHECK-LABEL: fsub_nxv4f32_x:687; CHECK: // %bb.0: // %entry688; CHECK-NEXT: ptrue p0.s689; CHECK-NEXT: fsub z1.s, z0.s, z1.s690; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.0691; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s692; CHECK-NEXT: ret693entry:694 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer695 %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %y, <vscale x 4 x float> zeroinitializer696 %b = fsub <vscale x 4 x float> %x, %a697 ret <vscale x 4 x float> %b698}699 700define <vscale x 8 x half> @fsub_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {701; CHECK-LABEL: fsub_nxv8f16_x:702; CHECK: // %bb.0: // %entry703; CHECK-NEXT: ptrue p0.h704; CHECK-NEXT: fsub z1.h, z0.h, z1.h705; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.0706; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h707; CHECK-NEXT: ret708entry:709 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer710 %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %y, <vscale x 8 x half> zeroinitializer711 %b = fsub <vscale x 8 x half> %x, %a712 ret <vscale x 8 x half> %b713}714 715define <vscale x 2 x double> @fsub_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {716; CHECK-LABEL: fsub_nxv2f64_x:717; CHECK: // %bb.0: // %entry718; CHECK-NEXT: ptrue p0.d719; CHECK-NEXT: fsub z1.d, z0.d, z1.d720; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.0721; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d722; CHECK-NEXT: ret723entry:724 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer725 %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %y, <vscale x 2 x double> zeroinitializer726 %b = fsub <vscale x 2 x double> %x, %a727 ret <vscale x 2 x double> %b728}729 730define <vscale x 4 x float> @fmul_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {731; CHECK-LABEL: fmul_nxv4f32_x:732; CHECK: // %bb.0: // %entry733; CHECK-NEXT: ptrue p0.s734; CHECK-NEXT: fmul z1.s, z0.s, z1.s735; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.0736; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s737; CHECK-NEXT: ret738entry:739 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer740 %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %y, <vscale x 4 x float> splat (float 1.000000e+00)741 %b = fmul <vscale x 4 x float> %a, %x742 ret <vscale x 4 x float> %b743}744 745define <vscale x 8 x half> @fmul_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {746; CHECK-LABEL: fmul_nxv8f16_x:747; CHECK: // %bb.0: // %entry748; CHECK-NEXT: ptrue p0.h749; CHECK-NEXT: fmul z1.h, z0.h, z1.h750; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.0751; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h752; CHECK-NEXT: ret753entry:754 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer755 %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %y, <vscale x 8 x half> splat (half 0xH3C00)756 %b = fmul <vscale x 8 x half> %a, %x757 ret <vscale x 8 x half> %b758}759 760define <vscale x 2 x double> @fmul_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {761; CHECK-LABEL: fmul_nxv2f64_x:762; CHECK: // %bb.0: // %entry763; CHECK-NEXT: ptrue p0.d764; CHECK-NEXT: fmul z1.d, z0.d, z1.d765; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.0766; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d767; CHECK-NEXT: ret768entry:769 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer770 %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %y, <vscale x 2 x double> splat (double 1.000000e+00)771 %b = fmul <vscale x 2 x double> %a, %x772 ret <vscale x 2 x double> %b773}774 775define <vscale x 4 x float> @fdiv_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {776; CHECK-LABEL: fdiv_nxv4f32_x:777; CHECK: // %bb.0: // %entry778; CHECK-NEXT: ptrue p0.s779; CHECK-NEXT: fdivr z1.s, p0/m, z1.s, z0.s780; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.0781; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s782; CHECK-NEXT: ret783entry:784 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer785 %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %y, <vscale x 4 x float> splat (float 1.000000e+00)786 %b = fdiv <vscale x 4 x float> %x, %a787 ret <vscale x 4 x float> %b788}789 790define <vscale x 8 x half> @fdiv_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {791; CHECK-LABEL: fdiv_nxv8f16_x:792; CHECK: // %bb.0: // %entry793; CHECK-NEXT: ptrue p0.h794; CHECK-NEXT: fdivr z1.h, p0/m, z1.h, z0.h795; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.0796; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h797; CHECK-NEXT: ret798entry:799 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer800 %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %y, <vscale x 8 x half> splat (half 0xH3C00)801 %b = fdiv <vscale x 8 x half> %x, %a802 ret <vscale x 8 x half> %b803}804 805define <vscale x 2 x double> @fdiv_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {806; CHECK-LABEL: fdiv_nxv2f64_x:807; CHECK: // %bb.0: // %entry808; CHECK-NEXT: ptrue p0.d809; CHECK-NEXT: fdivr z1.d, p0/m, z1.d, z0.d810; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.0811; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d812; CHECK-NEXT: ret813entry:814 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer815 %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %y, <vscale x 2 x double> splat (double 1.000000e+00)816 %b = fdiv <vscale x 2 x double> %x, %a817 ret <vscale x 2 x double> %b818}819 820define <vscale x 4 x float> @fma_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {821; CHECK-LABEL: fma_nxv4f32_x:822; CHECK: // %bb.0: // %entry823; CHECK-NEXT: ptrue p0.s824; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.0825; CHECK-NEXT: fmad z1.s, p0/m, z2.s, z0.s826; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s827; CHECK-NEXT: ret828entry:829 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer830 %m = fmul fast <vscale x 4 x float> %y, %z831 %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %m, <vscale x 4 x float> splat (float -0.000000e+00)832 %b = fadd fast <vscale x 4 x float> %a, %x833 ret <vscale x 4 x float> %b834}835 836define <vscale x 8 x half> @fma_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {837; CHECK-LABEL: fma_nxv8f16_x:838; CHECK: // %bb.0: // %entry839; CHECK-NEXT: ptrue p0.h840; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.0841; CHECK-NEXT: fmad z1.h, p0/m, z2.h, z0.h842; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h843; CHECK-NEXT: ret844entry:845 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer846 %m = fmul fast <vscale x 8 x half> %y, %z847 %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %m, <vscale x 8 x half> splat (half 0xH8000)848 %b = fadd fast <vscale x 8 x half> %a, %x849 ret <vscale x 8 x half> %b850}851 852define <vscale x 2 x double> @fma_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {853; CHECK-LABEL: fma_nxv2f64_x:854; CHECK: // %bb.0: // %entry855; CHECK-NEXT: ptrue p0.d856; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.0857; CHECK-NEXT: fmad z1.d, p0/m, z2.d, z0.d858; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d859; CHECK-NEXT: ret860entry:861 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer862 %m = fmul fast <vscale x 2 x double> %y, %z863 %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %m, <vscale x 2 x double> splat (double -0.000000e+00)864 %b = fadd fast <vscale x 2 x double> %a, %x865 ret <vscale x 2 x double> %b866}867 868define <vscale x 2 x i64> @add_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {869; CHECK-LABEL: add_nxv2i64_y:870; CHECK: // %bb.0: // %entry871; CHECK-NEXT: ptrue p0.d872; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0873; CHECK-NEXT: add z1.d, p0/m, z1.d, z0.d874; CHECK-NEXT: mov z0.d, z1.d875; CHECK-NEXT: ret876entry:877 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer878 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %x, <vscale x 2 x i64> zeroinitializer879 %b = add <vscale x 2 x i64> %a, %y880 ret <vscale x 2 x i64> %b881}882 883define <vscale x 4 x i32> @add_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {884; CHECK-LABEL: add_nxv4i32_y:885; CHECK: // %bb.0: // %entry886; CHECK-NEXT: ptrue p0.s887; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0888; CHECK-NEXT: add z1.s, p0/m, z1.s, z0.s889; CHECK-NEXT: mov z0.d, z1.d890; CHECK-NEXT: ret891entry:892 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer893 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> zeroinitializer894 %b = add <vscale x 4 x i32> %a, %y895 ret <vscale x 4 x i32> %b896}897 898define <vscale x 8 x i16> @add_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {899; CHECK-LABEL: add_nxv8i16_y:900; CHECK: // %bb.0: // %entry901; CHECK-NEXT: ptrue p0.h902; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0903; CHECK-NEXT: add z1.h, p0/m, z1.h, z0.h904; CHECK-NEXT: mov z0.d, z1.d905; CHECK-NEXT: ret906entry:907 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer908 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %x, <vscale x 8 x i16> zeroinitializer909 %b = add <vscale x 8 x i16> %a, %y910 ret <vscale x 8 x i16> %b911}912 913define <vscale x 16 x i8> @add_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {914; CHECK-LABEL: add_nxv16i8_y:915; CHECK: // %bb.0: // %entry916; CHECK-NEXT: ptrue p0.b917; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0918; CHECK-NEXT: add z1.b, p0/m, z1.b, z0.b919; CHECK-NEXT: mov z0.d, z1.d920; CHECK-NEXT: ret921entry:922 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer923 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %x, <vscale x 16 x i8> zeroinitializer924 %b = add <vscale x 16 x i8> %a, %y925 ret <vscale x 16 x i8> %b926}927 928define <vscale x 2 x i64> @sub_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {929; CHECK-LABEL: sub_nxv2i64_y:930; CHECK: // %bb.0: // %entry931; CHECK-NEXT: ptrue p0.d932; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0933; CHECK-NEXT: subr z1.d, p0/m, z1.d, z0.d934; CHECK-NEXT: mov z0.d, z1.d935; CHECK-NEXT: ret936entry:937 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer938 %a = sub <vscale x 2 x i64> %x, %y939 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y940 ret <vscale x 2 x i64> %b941}942 943define <vscale x 4 x i32> @sub_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {944; CHECK-LABEL: sub_nxv4i32_y:945; CHECK: // %bb.0: // %entry946; CHECK-NEXT: ptrue p0.s947; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0948; CHECK-NEXT: subr z1.s, p0/m, z1.s, z0.s949; CHECK-NEXT: mov z0.d, z1.d950; CHECK-NEXT: ret951entry:952 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer953 %a = sub <vscale x 4 x i32> %x, %y954 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y955 ret <vscale x 4 x i32> %b956}957 958define <vscale x 8 x i16> @sub_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {959; CHECK-LABEL: sub_nxv8i16_y:960; CHECK: // %bb.0: // %entry961; CHECK-NEXT: ptrue p0.h962; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0963; CHECK-NEXT: subr z1.h, p0/m, z1.h, z0.h964; CHECK-NEXT: mov z0.d, z1.d965; CHECK-NEXT: ret966entry:967 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer968 %a = sub <vscale x 8 x i16> %x, %y969 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y970 ret <vscale x 8 x i16> %b971}972 973define <vscale x 16 x i8> @sub_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {974; CHECK-LABEL: sub_nxv16i8_y:975; CHECK: // %bb.0: // %entry976; CHECK-NEXT: ptrue p0.b977; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0978; CHECK-NEXT: subr z1.b, p0/m, z1.b, z0.b979; CHECK-NEXT: mov z0.d, z1.d980; CHECK-NEXT: ret981entry:982 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer983 %a = sub <vscale x 16 x i8> %x, %y984 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y985 ret <vscale x 16 x i8> %b986}987 988define <vscale x 2 x i64> @mul_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {989; CHECK-LABEL: mul_nxv2i64_y:990; CHECK: // %bb.0: // %entry991; CHECK-NEXT: ptrue p0.d992; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0993; CHECK-NEXT: mul z1.d, p0/m, z1.d, z0.d994; CHECK-NEXT: mov z0.d, z1.d995; CHECK-NEXT: ret996entry:997 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer998 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %x, <vscale x 2 x i64> splat (i64 1)999 %b = mul <vscale x 2 x i64> %a, %y1000 ret <vscale x 2 x i64> %b1001}1002 1003define <vscale x 4 x i32> @mul_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1004; CHECK-LABEL: mul_nxv4i32_y:1005; CHECK: // %bb.0: // %entry1006; CHECK-NEXT: ptrue p0.s1007; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01008; CHECK-NEXT: mul z1.s, p0/m, z1.s, z0.s1009; CHECK-NEXT: mov z0.d, z1.d1010; CHECK-NEXT: ret1011entry:1012 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1013 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> splat (i32 1)1014 %b = mul <vscale x 4 x i32> %a, %y1015 ret <vscale x 4 x i32> %b1016}1017 1018define <vscale x 8 x i16> @mul_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1019; CHECK-LABEL: mul_nxv8i16_y:1020; CHECK: // %bb.0: // %entry1021; CHECK-NEXT: ptrue p0.h1022; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01023; CHECK-NEXT: mul z1.h, p0/m, z1.h, z0.h1024; CHECK-NEXT: mov z0.d, z1.d1025; CHECK-NEXT: ret1026entry:1027 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1028 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %x, <vscale x 8 x i16> splat (i16 1)1029 %b = mul <vscale x 8 x i16> %a, %y1030 ret <vscale x 8 x i16> %b1031}1032 1033define <vscale x 16 x i8> @mul_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1034; CHECK-LABEL: mul_nxv16i8_y:1035; CHECK: // %bb.0: // %entry1036; CHECK-NEXT: ptrue p0.b1037; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01038; CHECK-NEXT: mul z1.b, p0/m, z1.b, z0.b1039; CHECK-NEXT: mov z0.d, z1.d1040; CHECK-NEXT: ret1041entry:1042 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1043 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %x, <vscale x 16 x i8> splat (i8 1)1044 %b = mul <vscale x 16 x i8> %a, %y1045 ret <vscale x 16 x i8> %b1046}1047 1048define <vscale x 2 x i64> @and_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1049; CHECK-LABEL: and_nxv2i64_y:1050; CHECK: // %bb.0: // %entry1051; CHECK-NEXT: ptrue p0.d1052; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01053; CHECK-NEXT: and z1.d, p0/m, z1.d, z0.d1054; CHECK-NEXT: mov z0.d, z1.d1055; CHECK-NEXT: ret1056entry:1057 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1058 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %x, <vscale x 2 x i64> splat (i64 -1)1059 %b = and <vscale x 2 x i64> %a, %y1060 ret <vscale x 2 x i64> %b1061}1062 1063define <vscale x 4 x i32> @and_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1064; CHECK-LABEL: and_nxv4i32_y:1065; CHECK: // %bb.0: // %entry1066; CHECK-NEXT: ptrue p0.s1067; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01068; CHECK-NEXT: and z1.s, p0/m, z1.s, z0.s1069; CHECK-NEXT: mov z0.d, z1.d1070; CHECK-NEXT: ret1071entry:1072 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1073 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> splat (i32 -1)1074 %b = and <vscale x 4 x i32> %a, %y1075 ret <vscale x 4 x i32> %b1076}1077 1078define <vscale x 8 x i16> @and_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1079; CHECK-LABEL: and_nxv8i16_y:1080; CHECK: // %bb.0: // %entry1081; CHECK-NEXT: ptrue p0.h1082; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01083; CHECK-NEXT: and z1.h, p0/m, z1.h, z0.h1084; CHECK-NEXT: mov z0.d, z1.d1085; CHECK-NEXT: ret1086entry:1087 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1088 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %x, <vscale x 8 x i16> splat (i16 -1)1089 %b = and <vscale x 8 x i16> %a, %y1090 ret <vscale x 8 x i16> %b1091}1092 1093define <vscale x 16 x i8> @and_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1094; CHECK-LABEL: and_nxv16i8_y:1095; CHECK: // %bb.0: // %entry1096; CHECK-NEXT: ptrue p0.b1097; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01098; CHECK-NEXT: and z1.b, p0/m, z1.b, z0.b1099; CHECK-NEXT: mov z0.d, z1.d1100; CHECK-NEXT: ret1101entry:1102 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1103 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %x, <vscale x 16 x i8> splat (i8 -1)1104 %b = and <vscale x 16 x i8> %a, %y1105 ret <vscale x 16 x i8> %b1106}1107 1108define <vscale x 2 x i64> @or_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1109; CHECK-LABEL: or_nxv2i64_y:1110; CHECK: // %bb.0: // %entry1111; CHECK-NEXT: ptrue p0.d1112; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01113; CHECK-NEXT: orr z1.d, p0/m, z1.d, z0.d1114; CHECK-NEXT: mov z0.d, z1.d1115; CHECK-NEXT: ret1116entry:1117 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1118 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %x, <vscale x 2 x i64> zeroinitializer1119 %b = or <vscale x 2 x i64> %a, %y1120 ret <vscale x 2 x i64> %b1121}1122 1123define <vscale x 4 x i32> @or_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1124; CHECK-LABEL: or_nxv4i32_y:1125; CHECK: // %bb.0: // %entry1126; CHECK-NEXT: ptrue p0.s1127; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01128; CHECK-NEXT: orr z1.s, p0/m, z1.s, z0.s1129; CHECK-NEXT: mov z0.d, z1.d1130; CHECK-NEXT: ret1131entry:1132 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1133 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> zeroinitializer1134 %b = or <vscale x 4 x i32> %a, %y1135 ret <vscale x 4 x i32> %b1136}1137 1138define <vscale x 8 x i16> @or_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1139; CHECK-LABEL: or_nxv8i16_y:1140; CHECK: // %bb.0: // %entry1141; CHECK-NEXT: ptrue p0.h1142; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01143; CHECK-NEXT: orr z1.h, p0/m, z1.h, z0.h1144; CHECK-NEXT: mov z0.d, z1.d1145; CHECK-NEXT: ret1146entry:1147 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1148 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %x, <vscale x 8 x i16> zeroinitializer1149 %b = or <vscale x 8 x i16> %a, %y1150 ret <vscale x 8 x i16> %b1151}1152 1153define <vscale x 16 x i8> @or_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1154; CHECK-LABEL: or_nxv16i8_y:1155; CHECK: // %bb.0: // %entry1156; CHECK-NEXT: ptrue p0.b1157; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01158; CHECK-NEXT: orr z1.b, p0/m, z1.b, z0.b1159; CHECK-NEXT: mov z0.d, z1.d1160; CHECK-NEXT: ret1161entry:1162 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1163 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %x, <vscale x 16 x i8> zeroinitializer1164 %b = or <vscale x 16 x i8> %a, %y1165 ret <vscale x 16 x i8> %b1166}1167 1168define <vscale x 2 x i64> @xor_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1169; CHECK-LABEL: xor_nxv2i64_y:1170; CHECK: // %bb.0: // %entry1171; CHECK-NEXT: ptrue p0.d1172; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #01173; CHECK-NEXT: eor z1.d, p0/m, z1.d, z0.d1174; CHECK-NEXT: mov z0.d, z1.d1175; CHECK-NEXT: ret1176entry:1177 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1178 %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %x, <vscale x 2 x i64> zeroinitializer1179 %b = xor <vscale x 2 x i64> %a, %y1180 ret <vscale x 2 x i64> %b1181}1182 1183define <vscale x 4 x i32> @xor_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1184; CHECK-LABEL: xor_nxv4i32_y:1185; CHECK: // %bb.0: // %entry1186; CHECK-NEXT: ptrue p0.s1187; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01188; CHECK-NEXT: eor z1.s, p0/m, z1.s, z0.s1189; CHECK-NEXT: mov z0.d, z1.d1190; CHECK-NEXT: ret1191entry:1192 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1193 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> zeroinitializer1194 %b = xor <vscale x 4 x i32> %a, %y1195 ret <vscale x 4 x i32> %b1196}1197 1198define <vscale x 8 x i16> @xor_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1199; CHECK-LABEL: xor_nxv8i16_y:1200; CHECK: // %bb.0: // %entry1201; CHECK-NEXT: ptrue p0.h1202; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #01203; CHECK-NEXT: eor z1.h, p0/m, z1.h, z0.h1204; CHECK-NEXT: mov z0.d, z1.d1205; CHECK-NEXT: ret1206entry:1207 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1208 %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %x, <vscale x 8 x i16> zeroinitializer1209 %b = xor <vscale x 8 x i16> %a, %y1210 ret <vscale x 8 x i16> %b1211}1212 1213define <vscale x 16 x i8> @xor_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1214; CHECK-LABEL: xor_nxv16i8_y:1215; CHECK: // %bb.0: // %entry1216; CHECK-NEXT: ptrue p0.b1217; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #01218; CHECK-NEXT: eor z1.b, p0/m, z1.b, z0.b1219; CHECK-NEXT: mov z0.d, z1.d1220; CHECK-NEXT: ret1221entry:1222 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1223 %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %x, <vscale x 16 x i8> zeroinitializer1224 %b = xor <vscale x 16 x i8> %a, %y1225 ret <vscale x 16 x i8> %b1226}1227 1228define <vscale x 2 x i64> @shl_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1229; CHECK-LABEL: shl_nxv2i64_y:1230; CHECK: // %bb.0: // %entry1231; CHECK-NEXT: ptrue p0.d1232; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #01233; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d1234; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d1235; CHECK-NEXT: ret1236entry:1237 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1238 %a = shl <vscale x 2 x i64> %x, %y1239 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1240 ret <vscale x 2 x i64> %b1241}1242 1243define <vscale x 4 x i32> @shl_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1244; CHECK-LABEL: shl_nxv4i32_y:1245; CHECK: // %bb.0: // %entry1246; CHECK-NEXT: ptrue p0.s1247; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #01248; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s1249; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s1250; CHECK-NEXT: ret1251entry:1252 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1253 %a = shl <vscale x 4 x i32> %x, %y1254 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1255 ret <vscale x 4 x i32> %b1256}1257 1258define <vscale x 8 x i16> @shl_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1259; CHECK-LABEL: shl_nxv8i16_y:1260; CHECK: // %bb.0: // %entry1261; CHECK-NEXT: ptrue p0.h1262; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #01263; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h1264; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h1265; CHECK-NEXT: ret1266entry:1267 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1268 %a = shl <vscale x 8 x i16> %x, %y1269 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1270 ret <vscale x 8 x i16> %b1271}1272 1273define <vscale x 16 x i8> @shl_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1274; CHECK-LABEL: shl_nxv16i8_y:1275; CHECK: // %bb.0: // %entry1276; CHECK-NEXT: ptrue p0.b1277; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #01278; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b1279; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b1280; CHECK-NEXT: ret1281entry:1282 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1283 %a = shl <vscale x 16 x i8> %x, %y1284 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1285 ret <vscale x 16 x i8> %b1286}1287 1288define <vscale x 2 x i64> @ashr_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1289; CHECK-LABEL: ashr_nxv2i64_y:1290; CHECK: // %bb.0: // %entry1291; CHECK-NEXT: ptrue p0.d1292; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #01293; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d1294; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d1295; CHECK-NEXT: ret1296entry:1297 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1298 %a = ashr <vscale x 2 x i64> %x, %y1299 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1300 ret <vscale x 2 x i64> %b1301}1302 1303define <vscale x 4 x i32> @ashr_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1304; CHECK-LABEL: ashr_nxv4i32_y:1305; CHECK: // %bb.0: // %entry1306; CHECK-NEXT: ptrue p0.s1307; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #01308; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s1309; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s1310; CHECK-NEXT: ret1311entry:1312 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1313 %a = ashr <vscale x 4 x i32> %x, %y1314 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1315 ret <vscale x 4 x i32> %b1316}1317 1318define <vscale x 8 x i16> @ashr_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1319; CHECK-LABEL: ashr_nxv8i16_y:1320; CHECK: // %bb.0: // %entry1321; CHECK-NEXT: ptrue p0.h1322; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #01323; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h1324; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h1325; CHECK-NEXT: ret1326entry:1327 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1328 %a = ashr <vscale x 8 x i16> %x, %y1329 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1330 ret <vscale x 8 x i16> %b1331}1332 1333define <vscale x 16 x i8> @ashr_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1334; CHECK-LABEL: ashr_nxv16i8_y:1335; CHECK: // %bb.0: // %entry1336; CHECK-NEXT: ptrue p0.b1337; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #01338; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b1339; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b1340; CHECK-NEXT: ret1341entry:1342 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1343 %a = ashr <vscale x 16 x i8> %x, %y1344 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1345 ret <vscale x 16 x i8> %b1346}1347 1348define <vscale x 2 x i64> @lshr_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {1349; CHECK-LABEL: lshr_nxv2i64_y:1350; CHECK: // %bb.0: // %entry1351; CHECK-NEXT: ptrue p0.d1352; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #01353; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d1354; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d1355; CHECK-NEXT: ret1356entry:1357 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1358 %a = lshr <vscale x 2 x i64> %x, %y1359 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1360 ret <vscale x 2 x i64> %b1361}1362 1363define <vscale x 4 x i32> @lshr_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {1364; CHECK-LABEL: lshr_nxv4i32_y:1365; CHECK: // %bb.0: // %entry1366; CHECK-NEXT: ptrue p0.s1367; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #01368; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s1369; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s1370; CHECK-NEXT: ret1371entry:1372 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1373 %a = lshr <vscale x 4 x i32> %x, %y1374 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1375 ret <vscale x 4 x i32> %b1376}1377 1378define <vscale x 8 x i16> @lshr_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {1379; CHECK-LABEL: lshr_nxv8i16_y:1380; CHECK: // %bb.0: // %entry1381; CHECK-NEXT: ptrue p0.h1382; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #01383; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h1384; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h1385; CHECK-NEXT: ret1386entry:1387 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1388 %a = lshr <vscale x 8 x i16> %x, %y1389 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1390 ret <vscale x 8 x i16> %b1391}1392 1393define <vscale x 16 x i8> @lshr_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {1394; CHECK-LABEL: lshr_nxv16i8_y:1395; CHECK: // %bb.0: // %entry1396; CHECK-NEXT: ptrue p0.b1397; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #01398; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b1399; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b1400; CHECK-NEXT: ret1401entry:1402 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1403 %a = lshr <vscale x 16 x i8> %x, %y1404 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1405 ret <vscale x 16 x i8> %b1406}1407 1408define <vscale x 2 x i64> @mla_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {1409; CHECK-LABEL: mla_nxv2i64_y:1410; CHECK: // %bb.0: // %entry1411; CHECK-NEXT: ptrue p0.d1412; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, #01413; CHECK-NEXT: mad z1.d, p0/m, z2.d, z0.d1414; CHECK-NEXT: mov z0.d, z1.d1415; CHECK-NEXT: ret1416entry:1417 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1418 %m = mul <vscale x 2 x i64> %y, %z1419 %a = add <vscale x 2 x i64> %m, %x1420 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1421 ret <vscale x 2 x i64> %b1422}1423 1424define <vscale x 4 x i32> @mla_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {1425; CHECK-LABEL: mla_nxv4i32_y:1426; CHECK: // %bb.0: // %entry1427; CHECK-NEXT: ptrue p0.s1428; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, #01429; CHECK-NEXT: mad z1.s, p0/m, z2.s, z0.s1430; CHECK-NEXT: mov z0.d, z1.d1431; CHECK-NEXT: ret1432entry:1433 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1434 %m = mul <vscale x 4 x i32> %y, %z1435 %a = add <vscale x 4 x i32> %m, %x1436 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1437 ret <vscale x 4 x i32> %b1438}1439 1440define <vscale x 8 x i16> @mla_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {1441; CHECK-LABEL: mla_nxv8i16_y:1442; CHECK: // %bb.0: // %entry1443; CHECK-NEXT: ptrue p0.h1444; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, #01445; CHECK-NEXT: mad z1.h, p0/m, z2.h, z0.h1446; CHECK-NEXT: mov z0.d, z1.d1447; CHECK-NEXT: ret1448entry:1449 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1450 %m = mul <vscale x 8 x i16> %y, %z1451 %a = add <vscale x 8 x i16> %m, %x1452 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1453 ret <vscale x 8 x i16> %b1454}1455 1456define <vscale x 16 x i8> @mla_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {1457; CHECK-LABEL: mla_nxv16i8_y:1458; CHECK: // %bb.0: // %entry1459; CHECK-NEXT: ptrue p0.b1460; CHECK-NEXT: cmpgt p0.b, p0/z, z3.b, #01461; CHECK-NEXT: mad z1.b, p0/m, z2.b, z0.b1462; CHECK-NEXT: mov z0.d, z1.d1463; CHECK-NEXT: ret1464entry:1465 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1466 %m = mul <vscale x 16 x i8> %y, %z1467 %a = add <vscale x 16 x i8> %m, %x1468 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1469 ret <vscale x 16 x i8> %b1470}1471 1472define <vscale x 2 x i64> @mls_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {1473; CHECK-LABEL: mls_nxv2i64_y:1474; CHECK: // %bb.0: // %entry1475; CHECK-NEXT: ptrue p0.d1476; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, #01477; CHECK-NEXT: msb z1.d, p0/m, z0.d, z2.d1478; CHECK-NEXT: mov z0.d, z1.d1479; CHECK-NEXT: ret1480entry:1481 %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer1482 %m = mul <vscale x 2 x i64> %x, %y1483 %a = sub <vscale x 2 x i64> %z, %m1484 %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y1485 ret <vscale x 2 x i64> %b1486}1487 1488define <vscale x 4 x i32> @mls_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {1489; CHECK-LABEL: mls_nxv4i32_y:1490; CHECK: // %bb.0: // %entry1491; CHECK-NEXT: ptrue p0.s1492; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, #01493; CHECK-NEXT: msb z1.s, p0/m, z0.s, z2.s1494; CHECK-NEXT: mov z0.d, z1.d1495; CHECK-NEXT: ret1496entry:1497 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1498 %m = mul <vscale x 4 x i32> %x, %y1499 %a = sub <vscale x 4 x i32> %z, %m1500 %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y1501 ret <vscale x 4 x i32> %b1502}1503 1504define <vscale x 8 x i16> @mls_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {1505; CHECK-LABEL: mls_nxv8i16_y:1506; CHECK: // %bb.0: // %entry1507; CHECK-NEXT: ptrue p0.h1508; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, #01509; CHECK-NEXT: msb z1.h, p0/m, z0.h, z2.h1510; CHECK-NEXT: mov z0.d, z1.d1511; CHECK-NEXT: ret1512entry:1513 %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer1514 %m = mul <vscale x 8 x i16> %x, %y1515 %a = sub <vscale x 8 x i16> %z, %m1516 %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y1517 ret <vscale x 8 x i16> %b1518}1519 1520define <vscale x 16 x i8> @mls_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {1521; CHECK-LABEL: mls_nxv16i8_y:1522; CHECK: // %bb.0: // %entry1523; CHECK-NEXT: ptrue p0.b1524; CHECK-NEXT: cmpgt p0.b, p0/z, z3.b, #01525; CHECK-NEXT: msb z1.b, p0/m, z0.b, z2.b1526; CHECK-NEXT: mov z0.d, z1.d1527; CHECK-NEXT: ret1528entry:1529 %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer1530 %m = mul <vscale x 16 x i8> %x, %y1531 %a = sub <vscale x 16 x i8> %z, %m1532 %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y1533 ret <vscale x 16 x i8> %b1534}1535 1536define <vscale x 4 x float> @fadd_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1537; CHECK-LABEL: fadd_nxv4f32_y:1538; CHECK: // %bb.0: // %entry1539; CHECK-NEXT: ptrue p0.s1540; CHECK-NEXT: fadd z0.s, z1.s, z0.s1541; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.01542; CHECK-NEXT: mov z0.s, p0/m, z1.s1543; CHECK-NEXT: ret1544entry:1545 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1546 %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %x, <vscale x 4 x float> splat (float -0.000000e+00)1547 %b = fadd <vscale x 4 x float> %a, %y1548 ret <vscale x 4 x float> %b1549}1550 1551define <vscale x 8 x half> @fadd_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1552; CHECK-LABEL: fadd_nxv8f16_y:1553; CHECK: // %bb.0: // %entry1554; CHECK-NEXT: ptrue p0.h1555; CHECK-NEXT: fadd z0.h, z1.h, z0.h1556; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.01557; CHECK-NEXT: mov z0.h, p0/m, z1.h1558; CHECK-NEXT: ret1559entry:1560 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1561 %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %x, <vscale x 8 x half> splat (half 0xH8000)1562 %b = fadd <vscale x 8 x half> %a, %y1563 ret <vscale x 8 x half> %b1564}1565 1566define <vscale x 2 x double> @fadd_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1567; CHECK-LABEL: fadd_nxv2f64_y:1568; CHECK: // %bb.0: // %entry1569; CHECK-NEXT: ptrue p0.d1570; CHECK-NEXT: fadd z0.d, z1.d, z0.d1571; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.01572; CHECK-NEXT: mov z0.d, p0/m, z1.d1573; CHECK-NEXT: ret1574entry:1575 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1576 %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %x, <vscale x 2 x double> splat (double -0.000000e+00)1577 %b = fadd <vscale x 2 x double> %a, %y1578 ret <vscale x 2 x double> %b1579}1580 1581define <vscale x 4 x float> @fsub_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1582; CHECK-LABEL: fsub_nxv4f32_y:1583; CHECK: // %bb.0: // %entry1584; CHECK-NEXT: ptrue p0.s1585; CHECK-NEXT: fsub z0.s, z0.s, z1.s1586; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.01587; CHECK-NEXT: mov z0.s, p0/m, z1.s1588; CHECK-NEXT: ret1589entry:1590 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1591 %a = fsub <vscale x 4 x float> %x, %y1592 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y1593 ret <vscale x 4 x float> %b1594}1595 1596define <vscale x 8 x half> @fsub_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1597; CHECK-LABEL: fsub_nxv8f16_y:1598; CHECK: // %bb.0: // %entry1599; CHECK-NEXT: ptrue p0.h1600; CHECK-NEXT: fsub z0.h, z0.h, z1.h1601; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.01602; CHECK-NEXT: mov z0.h, p0/m, z1.h1603; CHECK-NEXT: ret1604entry:1605 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1606 %a = fsub <vscale x 8 x half> %x, %y1607 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y1608 ret <vscale x 8 x half> %b1609}1610 1611define <vscale x 2 x double> @fsub_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1612; CHECK-LABEL: fsub_nxv2f64_y:1613; CHECK: // %bb.0: // %entry1614; CHECK-NEXT: ptrue p0.d1615; CHECK-NEXT: fsub z0.d, z0.d, z1.d1616; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.01617; CHECK-NEXT: mov z0.d, p0/m, z1.d1618; CHECK-NEXT: ret1619entry:1620 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1621 %a = fsub <vscale x 2 x double> %x, %y1622 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y1623 ret <vscale x 2 x double> %b1624}1625 1626define <vscale x 4 x float> @fmul_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1627; CHECK-LABEL: fmul_nxv4f32_y:1628; CHECK: // %bb.0: // %entry1629; CHECK-NEXT: ptrue p0.s1630; CHECK-NEXT: fmul z0.s, z1.s, z0.s1631; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.01632; CHECK-NEXT: mov z0.s, p0/m, z1.s1633; CHECK-NEXT: ret1634entry:1635 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1636 %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %x, <vscale x 4 x float> splat (float 1.000000e+00)1637 %b = fmul <vscale x 4 x float> %a, %y1638 ret <vscale x 4 x float> %b1639}1640 1641define <vscale x 8 x half> @fmul_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1642; CHECK-LABEL: fmul_nxv8f16_y:1643; CHECK: // %bb.0: // %entry1644; CHECK-NEXT: ptrue p0.h1645; CHECK-NEXT: fmul z0.h, z1.h, z0.h1646; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.01647; CHECK-NEXT: mov z0.h, p0/m, z1.h1648; CHECK-NEXT: ret1649entry:1650 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1651 %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %x, <vscale x 8 x half> splat (half 0xH3C00)1652 %b = fmul <vscale x 8 x half> %a, %y1653 ret <vscale x 8 x half> %b1654}1655 1656define <vscale x 2 x double> @fmul_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1657; CHECK-LABEL: fmul_nxv2f64_y:1658; CHECK: // %bb.0: // %entry1659; CHECK-NEXT: ptrue p0.d1660; CHECK-NEXT: fmul z0.d, z1.d, z0.d1661; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.01662; CHECK-NEXT: mov z0.d, p0/m, z1.d1663; CHECK-NEXT: ret1664entry:1665 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1666 %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %x, <vscale x 2 x double> splat (double 1.000000e+00)1667 %b = fmul <vscale x 2 x double> %a, %y1668 ret <vscale x 2 x double> %b1669}1670 1671define <vscale x 4 x float> @fdiv_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {1672; CHECK-LABEL: fdiv_nxv4f32_y:1673; CHECK: // %bb.0: // %entry1674; CHECK-NEXT: ptrue p0.s1675; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s1676; CHECK-NEXT: fcmle p0.s, p0/z, z2.s, #0.01677; CHECK-NEXT: mov z0.s, p0/m, z1.s1678; CHECK-NEXT: ret1679entry:1680 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1681 %a = fdiv <vscale x 4 x float> %x, %y1682 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y1683 ret <vscale x 4 x float> %b1684}1685 1686define <vscale x 8 x half> @fdiv_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {1687; CHECK-LABEL: fdiv_nxv8f16_y:1688; CHECK: // %bb.0: // %entry1689; CHECK-NEXT: ptrue p0.h1690; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h1691; CHECK-NEXT: fcmle p0.h, p0/z, z2.h, #0.01692; CHECK-NEXT: mov z0.h, p0/m, z1.h1693; CHECK-NEXT: ret1694entry:1695 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1696 %a = fdiv <vscale x 8 x half> %x, %y1697 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y1698 ret <vscale x 8 x half> %b1699}1700 1701define <vscale x 2 x double> @fdiv_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {1702; CHECK-LABEL: fdiv_nxv2f64_y:1703; CHECK: // %bb.0: // %entry1704; CHECK-NEXT: ptrue p0.d1705; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d1706; CHECK-NEXT: fcmle p0.d, p0/z, z2.d, #0.01707; CHECK-NEXT: mov z0.d, p0/m, z1.d1708; CHECK-NEXT: ret1709entry:1710 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1711 %a = fdiv <vscale x 2 x double> %x, %y1712 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y1713 ret <vscale x 2 x double> %b1714}1715 1716define <vscale x 4 x float> @fmai_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {1717; CHECK-LABEL: fmai_nxv4f32_y:1718; CHECK: // %bb.0: // %entry1719; CHECK-NEXT: ptrue p0.s1720; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.01721; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s1722; CHECK-NEXT: mov z0.s, p1/m, z1.s1723; CHECK-NEXT: ret1724entry:1725 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1726 %a = call <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %x)1727 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y1728 ret <vscale x 4 x float> %b1729}1730 1731define <vscale x 8 x half> @fmai_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {1732; CHECK-LABEL: fmai_nxv8f16_y:1733; CHECK: // %bb.0: // %entry1734; CHECK-NEXT: ptrue p0.h1735; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.01736; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h1737; CHECK-NEXT: mov z0.h, p1/m, z1.h1738; CHECK-NEXT: ret1739entry:1740 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1741 %a = call <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %x)1742 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y1743 ret <vscale x 8 x half> %b1744}1745 1746define <vscale x 2 x double> @fmai_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {1747; CHECK-LABEL: fmai_nxv2f64_y:1748; CHECK: // %bb.0: // %entry1749; CHECK-NEXT: ptrue p0.d1750; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.01751; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d1752; CHECK-NEXT: mov z0.d, p1/m, z1.d1753; CHECK-NEXT: ret1754entry:1755 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1756 %a = call <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %x)1757 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y1758 ret <vscale x 2 x double> %b1759}1760 1761define <vscale x 4 x float> @fma_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {1762; CHECK-LABEL: fma_nxv4f32_y:1763; CHECK: // %bb.0: // %entry1764; CHECK-NEXT: ptrue p0.s1765; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.01766; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s1767; CHECK-NEXT: mov z0.s, p1/m, z1.s1768; CHECK-NEXT: ret1769entry:1770 %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer1771 %m = fmul fast <vscale x 4 x float> %y, %z1772 %a = fadd fast <vscale x 4 x float> %m, %x1773 %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y1774 ret <vscale x 4 x float> %b1775}1776 1777define <vscale x 8 x half> @fma_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {1778; CHECK-LABEL: fma_nxv8f16_y:1779; CHECK: // %bb.0: // %entry1780; CHECK-NEXT: ptrue p0.h1781; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.01782; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h1783; CHECK-NEXT: mov z0.h, p1/m, z1.h1784; CHECK-NEXT: ret1785entry:1786 %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer1787 %m = fmul fast <vscale x 8 x half> %y, %z1788 %a = fadd fast <vscale x 8 x half> %m, %x1789 %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y1790 ret <vscale x 8 x half> %b1791}1792 1793define <vscale x 2 x double> @fma_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {1794; CHECK-LABEL: fma_nxv2f64_y:1795; CHECK: // %bb.0: // %entry1796; CHECK-NEXT: ptrue p0.d1797; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.01798; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d1799; CHECK-NEXT: mov z0.d, p1/m, z1.d1800; CHECK-NEXT: ret1801entry:1802 %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer1803 %m = fmul fast <vscale x 2 x double> %y, %z1804 %a = fadd fast <vscale x 2 x double> %m, %x1805 %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y1806 ret <vscale x 2 x double> %b1807}1808 1809 1810define <vscale x 4 x i32> @mul_nxv4i32_multiuse_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n, ptr %p) {1811; CHECK-LABEL: mul_nxv4i32_multiuse_x:1812; CHECK: // %bb.0: // %entry1813; CHECK-NEXT: ptrue p0.s1814; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #01815; CHECK-NEXT: mov z2.s, #1 // =0x11816; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s1817; CHECK-NEXT: mul z0.s, z1.s, z0.s1818; CHECK-NEXT: str z1, [x0]1819; CHECK-NEXT: ret1820entry:1821 %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer1822 %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> splat (i32 1)1823 store <vscale x 4 x i32> %a, ptr %p1824 %b = mul <vscale x 4 x i32> %a, %x1825 ret <vscale x 4 x i32> %b1826}1827 1828declare <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)1829declare <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)1830declare <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)1831