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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2 %s -o - | FileCheck %s3 4;5; MATCH6;7 8define i32 @match_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {9; CHECK-LABEL: match_nxv16i8:10; CHECK: // %bb.0:11; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b12; CHECK-NEXT: cset w0, ne13; CHECK-NEXT: ret14 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)15 %2 = tail call i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)16 %conv = zext i1 %2 to i3217 ret i32 %conv18}19 20define i32 @match_imm_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {21; CHECK-LABEL: match_imm_nxv16i8:22; CHECK: // %bb.0:23; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b24; CHECK-NEXT: cset w0, ne25; CHECK-NEXT: ret26 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)27 %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)28 %3 = tail call i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %2, <vscale x 16 x i1> %1)29 %conv = zext i1 %3 to i3230 ret i32 %conv31}32 33;34; NMATCH35;36 37define i32 @nmatch_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {38; CHECK-LABEL: nmatch_nxv16i8:39; CHECK: // %bb.0:40; CHECK-NEXT: nmatch p0.b, p0/z, z0.b, z1.b41; CHECK-NEXT: cset w0, ne42; CHECK-NEXT: ret43 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.nmatch.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)44 %2 = tail call i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)45 %conv = zext i1 %2 to i3246 ret i32 %conv47}48 49define i32 @nmatch_imm_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {50; CHECK-LABEL: nmatch_imm_nxv16i8:51; CHECK: // %bb.0:52; CHECK-NEXT: nmatch p0.b, p0/z, z0.b, z1.b53; CHECK-NEXT: cset w0, ne54; CHECK-NEXT: ret55 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.nmatch.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)56 %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)57 %3 = tail call i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1> %2, <vscale x 16 x i1> %1)58 %conv = zext i1 %3 to i3259 ret i32 %conv60}61 62declare <vscale x 16 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)63declare <vscale x 16 x i1> @llvm.aarch64.sve.nmatch.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)64declare i1 @llvm.aarch64.sve.ptest.any(<vscale x 16 x i1>, <vscale x 16 x i1>)65declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)66