75 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve %s -o - | FileCheck %s3 4define i32 @pfirst_16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {5; CHECK-LABEL: pfirst_16:6; CHECK: // %bb.0:7; CHECK-NEXT: pfirst p1.b, p0, p1.b8; CHECK-NEXT: cset w0, ne9; CHECK-NEXT: ret10 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)11 %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)12 %conv = zext i1 %2 to i3213 ret i32 %conv14}15 16define i32 @pnext_2(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a) {17; CHECK-LABEL: pnext_2:18; CHECK: // %bb.0:19; CHECK-NEXT: pnext p1.d, p0, p1.d20; CHECK-NEXT: cset w0, ne21; CHECK-NEXT: ret22 %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a)23 %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %1)24 %conv = zext i1 %2 to i3225 ret i32 %conv26}27 28define i32 @pnext_4(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a) {29; CHECK-LABEL: pnext_4:30; CHECK: // %bb.0:31; CHECK-NEXT: pnext p1.s, p0, p1.s32; CHECK-NEXT: cset w0, ne33; CHECK-NEXT: ret34 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a)35 %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %1)36 %conv = zext i1 %2 to i3237 ret i32 %conv38}39 40define i32 @pnext_8(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a) {41; CHECK-LABEL: pnext_8:42; CHECK: // %bb.0:43; CHECK-NEXT: pnext p1.h, p0, p1.h44; CHECK-NEXT: cset w0, ne45; CHECK-NEXT: ret46 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a)47 %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %1)48 %conv = zext i1 %2 to i3249 ret i32 %conv50}51 52define i32 @pnext_16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {53; CHECK-LABEL: pnext_16:54; CHECK: // %bb.0:55; CHECK-NEXT: pnext p1.b, p0, p1.b56; CHECK-NEXT: cset w0, ne57; CHECK-NEXT: ret58 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)59 %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)60 %conv = zext i1 %2 to i3261 ret i32 %conv62}63 64declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)65 66declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)67declare <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)68declare <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)69declare <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)70 71declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)72declare i1 @llvm.aarch64.sve.ptest.any.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)73declare i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)74declare i1 @llvm.aarch64.sve.ptest.any.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)75