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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3target triple = "aarch64-unknown-linux-gnu"4 5define <vscale x 8 x i1> @masked_load_sext_i8i16(ptr %ap, <vscale x 16 x i8> %b) #0 {6; CHECK-LABEL: masked_load_sext_i8i16:7; CHECK: // %bb.0:8; CHECK-NEXT: ptrue p0.b, vl329; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #010; CHECK-NEXT: punpklo p0.h, p0.b11; CHECK-NEXT: ret12 %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)13 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)14 %extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)15 %ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>16 %p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)17 %cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)18 ret <vscale x 8 x i1> %cmp119}20 21; This negative test ensures the two ptrues have the same vl22define <vscale x 8 x i1> @masked_load_sext_i8i16_ptrue_vl(ptr %ap, <vscale x 16 x i8> %b) #0 {23; CHECK-LABEL: masked_load_sext_i8i16_ptrue_vl:24; CHECK: // %bb.0:25; CHECK-NEXT: ptrue p0.b, vl6426; CHECK-NEXT: ptrue p1.h, vl3227; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #028; CHECK-NEXT: punpklo p0.h, p0.b29; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b30; CHECK-NEXT: ret31 %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)32 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)33 %extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)34 %ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>35 %p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)36 %cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)37 ret <vscale x 8 x i1> %cmp138}39 40; This negative test enforces that both predicates are ptrues41define <vscale x 8 x i1> @masked_load_sext_i8i16_parg(ptr %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 {42; CHECK-LABEL: masked_load_sext_i8i16_parg:43; CHECK: // %bb.0:44; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #045; CHECK-NEXT: ptrue p1.h, vl3246; CHECK-NEXT: punpklo p0.h, p0.b47; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b48; CHECK-NEXT: ret49 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)50 %extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)51 %ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>52 %p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)53 %cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)54 ret <vscale x 8 x i1> %cmp155}56 57define <vscale x 4 x i1> @masked_load_sext_i8i32(ptr %ap, <vscale x 16 x i8> %b) #0 {58; CHECK-LABEL: masked_load_sext_i8i32:59; CHECK: // %bb.0:60; CHECK-NEXT: ptrue p0.b, vl3261; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #062; CHECK-NEXT: punpklo p0.h, p0.b63; CHECK-NEXT: punpklo p0.h, p0.b64; CHECK-NEXT: ret65 %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)66 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)67 %extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)68 %ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>69 %p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)70 %cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)71 ret <vscale x 4 x i1> %cmp172}73 74; This negative test ensures the two ptrues have the same vl75define <vscale x 4 x i1> @masked_load_sext_i8i32_ptrue_vl(ptr %ap, <vscale x 16 x i8> %b) #0 {76; CHECK-LABEL: masked_load_sext_i8i32_ptrue_vl:77; CHECK: // %bb.0:78; CHECK-NEXT: ptrue p0.b, vl6479; CHECK-NEXT: ptrue p1.s, vl3280; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #081; CHECK-NEXT: punpklo p0.h, p0.b82; CHECK-NEXT: punpklo p0.h, p0.b83; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b84; CHECK-NEXT: ret85 %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)86 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)87 %extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)88 %ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>89 %p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)90 %cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)91 ret <vscale x 4 x i1> %cmp192}93 94; This negative test enforces that both predicates are ptrues95define <vscale x 4 x i1> @masked_load_sext_i8i32_parg(ptr %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 {96; CHECK-LABEL: masked_load_sext_i8i32_parg:97; CHECK: // %bb.0:98; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #099; CHECK-NEXT: ptrue p1.s, vl32100; CHECK-NEXT: punpklo p0.h, p0.b101; CHECK-NEXT: punpklo p0.h, p0.b102; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b103; CHECK-NEXT: ret104 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)105 %extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)106 %ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>107 %p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)108 %cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)109 ret <vscale x 4 x i1> %cmp1110}111 112define <vscale x 2 x i1> @masked_load_sext_i8i64(ptr %ap, <vscale x 16 x i8> %b) #0 {113; CHECK-LABEL: masked_load_sext_i8i64:114; CHECK: // %bb.0:115; CHECK-NEXT: ptrue p0.b, vl32116; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0117; CHECK-NEXT: punpklo p0.h, p0.b118; CHECK-NEXT: punpklo p0.h, p0.b119; CHECK-NEXT: punpklo p0.h, p0.b120; CHECK-NEXT: ret121 %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)122 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)123 %extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)124 %ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>125 %p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10)126 %cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)127 ret <vscale x 2 x i1> %cmp1128}129 130; This negative test ensures the two ptrues have the same vl131define <vscale x 2 x i1> @masked_load_sext_i8i64_ptrue_vl(ptr %ap, <vscale x 16 x i8> %b) #0 {132; CHECK-LABEL: masked_load_sext_i8i64_ptrue_vl:133; CHECK: // %bb.0:134; CHECK-NEXT: ptrue p0.b, vl64135; CHECK-NEXT: ptrue p1.d, vl32136; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0137; CHECK-NEXT: punpklo p0.h, p0.b138; CHECK-NEXT: punpklo p0.h, p0.b139; CHECK-NEXT: punpklo p0.h, p0.b140; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b141; CHECK-NEXT: ret142 %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)143 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)144 %extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)145 %ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>146 %p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10)147 %cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)148 ret <vscale x 2 x i1> %cmp1149}150 151; This negative test enforces that both predicates are ptrues152define <vscale x 2 x i1> @masked_load_sext_i8i64_parg(ptr %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 {153; CHECK-LABEL: masked_load_sext_i8i64_parg:154; CHECK: // %bb.0:155; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0156; CHECK-NEXT: ptrue p1.d, vl32157; CHECK-NEXT: punpklo p0.h, p0.b158; CHECK-NEXT: punpklo p0.h, p0.b159; CHECK-NEXT: punpklo p0.h, p0.b160; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b161; CHECK-NEXT: ret162 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)163 %extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)164 %ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>165 %p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10)166 %cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)167 ret <vscale x 2 x i1> %cmp1168}169 170; This negative test enforces that the ptrues have a specified vl171define <vscale x 8 x i1> @masked_load_sext_i8i16_ptrue_all(ptr %ap, <vscale x 16 x i8> %b) #0 {172; CHECK-LABEL: masked_load_sext_i8i16_ptrue_all:173; CHECK: // %bb.0:174; CHECK-NEXT: ptrue p0.b, vl64175; CHECK-NEXT: ptrue p1.h, vl32176; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0177; CHECK-NEXT: punpklo p0.h, p0.b178; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b179; CHECK-NEXT: ret180 %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)181 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)182 %extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)183 %ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>184 %p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)185 %cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)186 ret <vscale x 8 x i1> %cmp1187}188 189; This negative test enforces that the ptrues have a specified vl190define <vscale x 4 x i1> @masked_load_sext_i8i32_ptrue_all(ptr %ap, <vscale x 16 x i8> %b) #0 {191; CHECK-LABEL: masked_load_sext_i8i32_ptrue_all:192; CHECK: // %bb.0:193; CHECK-NEXT: ptrue p0.b, vl64194; CHECK-NEXT: ptrue p1.s, vl32195; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0196; CHECK-NEXT: punpklo p0.h, p0.b197; CHECK-NEXT: punpklo p0.h, p0.b198; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b199; CHECK-NEXT: ret200 %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)201 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)202 %extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)203 %ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>204 %p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)205 %cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)206 ret <vscale x 4 x i1> %cmp1207}208 209; This negative test enforces that the ptrues have a specified vl210define <vscale x 2 x i1> @masked_load_sext_i8i64_ptrue_all(ptr %ap, <vscale x 16 x i8> %b) #0 {211; CHECK-LABEL: masked_load_sext_i8i64_ptrue_all:212; CHECK: // %bb.0:213; CHECK-NEXT: ptrue p0.b214; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0215; CHECK-NEXT: punpklo p0.h, p0.b216; CHECK-NEXT: punpklo p0.h, p0.b217; CHECK-NEXT: punpklo p0.h, p0.b218; CHECK-NEXT: ret219 %p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)220 %cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)221 %extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)222 %ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>223 %p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)224 %cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)225 ret <vscale x 2 x i1> %cmp1226}227 228declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)229 230declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)231declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)232declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)233declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)234 235declare <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1>, i64)236declare <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1>, i64)237declare <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1>, i64)238 239declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)240declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)241declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)242 243attributes #0 = { "target-features"="+sve" }244