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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple aarch64-unknown-linux-gnu -mattr=+sve2 < %s | FileCheck %s3 4; SABA from ADD(ABS(SUB NSW))5 6define <vscale x 2 x i64> @saba_abs_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) #0 {7; CHECK-LABEL: saba_abs_d:8; CHECK: // %bb.0:9; CHECK-NEXT: saba z0.d, z1.d, z2.d10; CHECK-NEXT: ret11 %sub = sub nsw <vscale x 2 x i64> %b, %c12 %abs = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %sub, i1 true)13 %add = add <vscale x 2 x i64> %a, %abs14 ret <vscale x 2 x i64> %add15}16 17define <vscale x 4 x i32> @saba_abs_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {18; CHECK-LABEL: saba_abs_s:19; CHECK: // %bb.0:20; CHECK-NEXT: saba z0.s, z1.s, z2.s21; CHECK-NEXT: ret22 %sub = sub nsw <vscale x 4 x i32> %b, %c23 %abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)24 %add = add <vscale x 4 x i32> %a, %abs25 ret <vscale x 4 x i32> %add26}27 28define <vscale x 8 x i16> @saba_abs_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) #0 {29; CHECK-LABEL: saba_abs_h:30; CHECK: // %bb.0:31; CHECK-NEXT: saba z0.h, z1.h, z2.h32; CHECK-NEXT: ret33 %sub = sub nsw <vscale x 8 x i16> %b, %c34 %abs = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %sub, i1 true)35 %add = add <vscale x 8 x i16> %a, %abs36 ret <vscale x 8 x i16> %add37}38 39define <vscale x 16 x i8> @saba_abs_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {40; CHECK-LABEL: saba_abs_b:41; CHECK: // %bb.0:42; CHECK-NEXT: saba z0.b, z1.b, z2.b43; CHECK-NEXT: ret44 %sub = sub nsw <vscale x 16 x i8> %b, %c45 %abs = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %sub, i1 true)46 %add = add <vscale x 16 x i8> %a, %abs47 ret <vscale x 16 x i8> %add48}49 50; SABA from ADD(SABD)51 52define <vscale x 2 x i64> @saba_sabd_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) #0 {53; CHECK-LABEL: saba_sabd_d:54; CHECK: // %bb.0:55; CHECK-NEXT: saba z0.d, z1.d, z2.d56; CHECK-NEXT: ret57 %true = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)58 %sabd = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.u.nxv2i64(<vscale x 2 x i1> %true, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)59 %add = add <vscale x 2 x i64> %sabd, %a60 ret <vscale x 2 x i64> %add61}62 63define <vscale x 4 x i32> @saba_sabd_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {64; CHECK-LABEL: saba_sabd_s:65; CHECK: // %bb.0:66; CHECK-NEXT: saba z0.s, z1.s, z2.s67; CHECK-NEXT: ret68 %true = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)69 %sabd = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.u.nxv4i32(<vscale x 4 x i1> %true, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)70 %add = add <vscale x 4 x i32> %sabd, %a71 ret <vscale x 4 x i32> %add72}73 74define <vscale x 8 x i16> @saba_sabd_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) #0 {75; CHECK-LABEL: saba_sabd_h:76; CHECK: // %bb.0:77; CHECK-NEXT: saba z0.h, z1.h, z2.h78; CHECK-NEXT: ret79 %true = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)80 %sabd = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.u.nxv8i16(<vscale x 8 x i1> %true, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)81 %add = add <vscale x 8 x i16> %sabd, %a82 ret <vscale x 8 x i16> %add83}84 85define <vscale x 16 x i8> @saba_sabd_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {86; CHECK-LABEL: saba_sabd_b:87; CHECK: // %bb.0:88; CHECK-NEXT: saba z0.b, z1.b, z2.b89; CHECK-NEXT: ret90 %true = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)91 %sabd = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.u.nxv16i8(<vscale x 16 x i1> %true, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)92 %add = add <vscale x 16 x i8> %sabd, %a93 ret <vscale x 16 x i8> %add94}95 96declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)97declare <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32>, i1)98declare <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16>, i1)99declare <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8>, i1)100 101declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)102declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)103declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)104declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)105 106declare <vscale x 2 x i64> @llvm.aarch64.sve.sabd.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)107declare <vscale x 4 x i32> @llvm.aarch64.sve.sabd.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)108declare <vscale x 8 x i16> @llvm.aarch64.sve.sabd.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)109declare <vscale x 16 x i8> @llvm.aarch64.sve.sabd.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)110