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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64 -mattr=+sve -verify-machineinstrs %s -o - | FileCheck %s3; RUN: llc -mtriple=aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s4 5; SQADD6define <vscale x 16 x i8> @sqadd_i8_low(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {7; CHECK-LABEL: sqadd_i8_low:8; CHECK: // %bb.0:9; CHECK-NEXT: sqadd z0.b, z0.b, z1.b10; CHECK-NEXT: ret11 %res = call <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)12 ret <vscale x 16 x i8> %res13}14 15define <vscale x 8 x i16> @sqadd_i16_low(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {16; CHECK-LABEL: sqadd_i16_low:17; CHECK: // %bb.0:18; CHECK-NEXT: sqadd z0.h, z0.h, z1.h19; CHECK-NEXT: ret20 %res = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)21 ret <vscale x 8 x i16> %res22}23 24define <vscale x 4 x i32> @sqadd_i32_low(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {25; CHECK-LABEL: sqadd_i32_low:26; CHECK: // %bb.0:27; CHECK-NEXT: sqadd z0.s, z0.s, z1.s28; CHECK-NEXT: ret29 %res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)30 ret <vscale x 4 x i32> %res31}32 33define <vscale x 2 x i64> @sqadd_i64_low(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {34; CHECK-LABEL: sqadd_i64_low:35; CHECK: // %bb.0:36; CHECK-NEXT: sqadd z0.d, z0.d, z1.d37; CHECK-NEXT: ret38 %res = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)39 ret <vscale x 2 x i64> %res40}41 42; UQADD43define <vscale x 16 x i8> @uqadd_i8_low(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {44; CHECK-LABEL: uqadd_i8_low:45; CHECK: // %bb.0:46; CHECK-NEXT: uqadd z0.b, z0.b, z1.b47; CHECK-NEXT: ret48 %res = call <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)49 ret <vscale x 16 x i8> %res50}51 52define <vscale x 8 x i16> @uqadd_i16_low(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {53; CHECK-LABEL: uqadd_i16_low:54; CHECK: // %bb.0:55; CHECK-NEXT: uqadd z0.h, z0.h, z1.h56; CHECK-NEXT: ret57 %res = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)58 ret <vscale x 8 x i16> %res59}60 61define <vscale x 4 x i32> @uqadd_i32_low(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {62; CHECK-LABEL: uqadd_i32_low:63; CHECK: // %bb.0:64; CHECK-NEXT: uqadd z0.s, z0.s, z1.s65; CHECK-NEXT: ret66 %res = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)67 ret <vscale x 4 x i32> %res68}69 70define <vscale x 2 x i64> @uqadd_i64_low(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {71; CHECK-LABEL: uqadd_i64_low:72; CHECK: // %bb.0:73; CHECK-NEXT: uqadd z0.d, z0.d, z1.d74; CHECK-NEXT: ret75 %res = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)76 ret <vscale x 2 x i64> %res77}78 79; SQSUB80define <vscale x 16 x i8> @sqsub_i8_low(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {81; CHECK-LABEL: sqsub_i8_low:82; CHECK: // %bb.0:83; CHECK-NEXT: sqsub z0.b, z0.b, z1.b84; CHECK-NEXT: ret85 %res = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)86 ret <vscale x 16 x i8> %res87}88 89define <vscale x 8 x i16> @sqsub_i16_low(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {90; CHECK-LABEL: sqsub_i16_low:91; CHECK: // %bb.0:92; CHECK-NEXT: sqsub z0.h, z0.h, z1.h93; CHECK-NEXT: ret94 %res = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)95 ret <vscale x 8 x i16> %res96}97 98define <vscale x 4 x i32> @sqsub_i32_low(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {99; CHECK-LABEL: sqsub_i32_low:100; CHECK: // %bb.0:101; CHECK-NEXT: sqsub z0.s, z0.s, z1.s102; CHECK-NEXT: ret103 %res = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)104 ret <vscale x 4 x i32> %res105}106 107define <vscale x 2 x i64> @sqsub_i64_low(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {108; CHECK-LABEL: sqsub_i64_low:109; CHECK: // %bb.0:110; CHECK-NEXT: sqsub z0.d, z0.d, z1.d111; CHECK-NEXT: ret112 %res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)113 ret <vscale x 2 x i64> %res114}115 116; UQSUB117define <vscale x 16 x i8> @uqsub_i8_low(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {118; CHECK-LABEL: uqsub_i8_low:119; CHECK: // %bb.0:120; CHECK-NEXT: uqsub z0.b, z0.b, z1.b121; CHECK-NEXT: ret122 %res = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)123 ret <vscale x 16 x i8> %res124}125 126define <vscale x 8 x i16> @uqsub_i16_low(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {127; CHECK-LABEL: uqsub_i16_low:128; CHECK: // %bb.0:129; CHECK-NEXT: uqsub z0.h, z0.h, z1.h130; CHECK-NEXT: ret131 %res = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)132 ret <vscale x 8 x i16> %res133}134 135define <vscale x 4 x i32> @uqsub_i32_low(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {136; CHECK-LABEL: uqsub_i32_low:137; CHECK: // %bb.0:138; CHECK-NEXT: uqsub z0.s, z0.s, z1.s139; CHECK-NEXT: ret140 %res = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)141 ret <vscale x 4 x i32> %res142}143 144define <vscale x 2 x i64> @uqsub_i64_low(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {145; CHECK-LABEL: uqsub_i64_low:146; CHECK: // %bb.0:147; CHECK-NEXT: uqsub z0.d, z0.d, z1.d148; CHECK-NEXT: ret149 %res = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)150 ret <vscale x 2 x i64> %res151}152 153declare <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)154declare <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)155declare <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)156declare <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)157declare <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)158declare <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)159declare <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)160declare <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)161declare <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)162declare <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)163declare <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)164declare <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)165declare <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)166declare <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)167declare <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)168declare <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)169