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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64 -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s3 4define <vscale x 8 x i8> @s_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {5; CHECK-LABEL: s_nxv8i8:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: ptrue p0.h8; CHECK-NEXT: sxtb z0.h, p0/m, z0.h9; CHECK-NEXT: sxtb z1.h, p0/m, z1.h10; CHECK-NEXT: cmpgt p1.h, p0/z, z0.h, z1.h11; CHECK-NEXT: cmpgt p0.h, p0/z, z1.h, z0.h12; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x113; CHECK-NEXT: mov z0.h, p0/m, #-1 // =0xffffffffffffffff14; CHECK-NEXT: ret15entry:16 %c = call <vscale x 8 x i8> @llvm.scmp(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b)17 ret <vscale x 8 x i8> %c18}19 20define <vscale x 16 x i8> @s_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {21; CHECK-LABEL: s_nxv16i8:22; CHECK: // %bb.0: // %entry23; CHECK-NEXT: ptrue p0.b24; CHECK-NEXT: cmpgt p1.b, p0/z, z0.b, z1.b25; CHECK-NEXT: cmpgt p0.b, p0/z, z1.b, z0.b26; CHECK-NEXT: mov z0.b, p1/z, #1 // =0x127; CHECK-NEXT: mov z0.b, p0/m, #-1 // =0xffffffffffffffff28; CHECK-NEXT: ret29entry:30 %c = call <vscale x 16 x i8> @llvm.scmp(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)31 ret <vscale x 16 x i8> %c32}33 34define <vscale x 4 x i16> @s_nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {35; CHECK-LABEL: s_nxv4i16:36; CHECK: // %bb.0: // %entry37; CHECK-NEXT: ptrue p0.s38; CHECK-NEXT: sxth z0.s, p0/m, z0.s39; CHECK-NEXT: sxth z1.s, p0/m, z1.s40; CHECK-NEXT: cmpgt p1.s, p0/z, z0.s, z1.s41; CHECK-NEXT: cmpgt p0.s, p0/z, z1.s, z0.s42; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x143; CHECK-NEXT: mov z0.s, p0/m, #-1 // =0xffffffffffffffff44; CHECK-NEXT: ret45entry:46 %c = call <vscale x 4 x i16> @llvm.scmp(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b)47 ret <vscale x 4 x i16> %c48}49 50define <vscale x 8 x i16> @s_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {51; CHECK-LABEL: s_nxv8i16:52; CHECK: // %bb.0: // %entry53; CHECK-NEXT: ptrue p0.h54; CHECK-NEXT: cmpgt p1.h, p0/z, z0.h, z1.h55; CHECK-NEXT: cmpgt p0.h, p0/z, z1.h, z0.h56; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x157; CHECK-NEXT: mov z0.h, p0/m, #-1 // =0xffffffffffffffff58; CHECK-NEXT: ret59entry:60 %c = call <vscale x 8 x i16> @llvm.scmp(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)61 ret <vscale x 8 x i16> %c62}63 64define <vscale x 16 x i16> @s_nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {65; CHECK-LABEL: s_nxv16i16:66; CHECK: // %bb.0: // %entry67; CHECK-NEXT: ptrue p0.h68; CHECK-NEXT: cmpgt p1.h, p0/z, z0.h, z2.h69; CHECK-NEXT: cmpgt p2.h, p0/z, z1.h, z3.h70; CHECK-NEXT: cmpgt p3.h, p0/z, z2.h, z0.h71; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, z1.h72; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x173; CHECK-NEXT: mov z1.h, p2/z, #1 // =0x174; CHECK-NEXT: mov z0.h, p3/m, #-1 // =0xffffffffffffffff75; CHECK-NEXT: mov z1.h, p0/m, #-1 // =0xffffffffffffffff76; CHECK-NEXT: ret77entry:78 %c = call <vscale x 16 x i16> @llvm.scmp(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b)79 ret <vscale x 16 x i16> %c80}81 82define <vscale x 2 x i32> @s_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {83; CHECK-LABEL: s_nxv2i32:84; CHECK: // %bb.0: // %entry85; CHECK-NEXT: ptrue p0.d86; CHECK-NEXT: sxtw z0.d, p0/m, z0.d87; CHECK-NEXT: sxtw z1.d, p0/m, z1.d88; CHECK-NEXT: cmpgt p1.d, p0/z, z0.d, z1.d89; CHECK-NEXT: cmpgt p0.d, p0/z, z1.d, z0.d90; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x191; CHECK-NEXT: mov z0.d, p0/m, #-1 // =0xffffffffffffffff92; CHECK-NEXT: ret93entry:94 %c = call <vscale x 2 x i32> @llvm.scmp(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)95 ret <vscale x 2 x i32> %c96}97 98define <vscale x 4 x i32> @s_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {99; CHECK-LABEL: s_nxv4i32:100; CHECK: // %bb.0: // %entry101; CHECK-NEXT: ptrue p0.s102; CHECK-NEXT: cmpgt p1.s, p0/z, z0.s, z1.s103; CHECK-NEXT: cmpgt p0.s, p0/z, z1.s, z0.s104; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x1105; CHECK-NEXT: mov z0.s, p0/m, #-1 // =0xffffffffffffffff106; CHECK-NEXT: ret107entry:108 %c = call <vscale x 4 x i32> @llvm.scmp(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)109 ret <vscale x 4 x i32> %c110}111 112define <vscale x 8 x i32> @s_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {113; CHECK-LABEL: s_nxv8i32:114; CHECK: // %bb.0: // %entry115; CHECK-NEXT: ptrue p0.s116; CHECK-NEXT: cmpgt p1.s, p0/z, z0.s, z2.s117; CHECK-NEXT: cmpgt p2.s, p0/z, z1.s, z3.s118; CHECK-NEXT: cmpgt p3.s, p0/z, z2.s, z0.s119; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, z1.s120; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x1121; CHECK-NEXT: mov z1.s, p2/z, #1 // =0x1122; CHECK-NEXT: mov z0.s, p3/m, #-1 // =0xffffffffffffffff123; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff124; CHECK-NEXT: ret125entry:126 %c = call <vscale x 8 x i32> @llvm.scmp(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b)127 ret <vscale x 8 x i32> %c128}129 130define <vscale x 2 x i64> @s_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {131; CHECK-LABEL: s_nxv2i64:132; CHECK: // %bb.0: // %entry133; CHECK-NEXT: ptrue p0.d134; CHECK-NEXT: cmpgt p1.d, p0/z, z0.d, z1.d135; CHECK-NEXT: cmpgt p0.d, p0/z, z1.d, z0.d136; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x1137; CHECK-NEXT: mov z0.d, p0/m, #-1 // =0xffffffffffffffff138; CHECK-NEXT: ret139entry:140 %c = call <vscale x 2 x i64> @llvm.scmp(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)141 ret <vscale x 2 x i64> %c142}143 144define <vscale x 4 x i64> @s_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {145; CHECK-LABEL: s_nxv4i64:146; CHECK: // %bb.0: // %entry147; CHECK-NEXT: ptrue p0.d148; CHECK-NEXT: cmpgt p1.d, p0/z, z0.d, z2.d149; CHECK-NEXT: cmpgt p2.d, p0/z, z1.d, z3.d150; CHECK-NEXT: cmpgt p3.d, p0/z, z2.d, z0.d151; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, z1.d152; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x1153; CHECK-NEXT: mov z1.d, p2/z, #1 // =0x1154; CHECK-NEXT: mov z0.d, p3/m, #-1 // =0xffffffffffffffff155; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff156; CHECK-NEXT: ret157entry:158 %c = call <vscale x 4 x i64> @llvm.scmp(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b)159 ret <vscale x 4 x i64> %c160}161