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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s3 4define <vscale x 1 x i8> @select_nxv1i8(i1 %cond, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {5; CHECK-LABEL: select_nxv1i8:6; CHECK: // %bb.0:7; CHECK-NEXT: // kill: def $w0 killed $w0 def $x08; CHECK-NEXT: sbfx x8, x0, #0, #19; CHECK-NEXT: whilelo p0.b, xzr, x810; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b11; CHECK-NEXT: ret12 %res = select i1 %cond, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b13 ret <vscale x 1 x i8> %res14}15 16define <vscale x 16 x i8> @select_nxv16i8(i1 %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {17; CHECK-LABEL: select_nxv16i8:18; CHECK: // %bb.0:19; CHECK-NEXT: // kill: def $w0 killed $w0 def $x020; CHECK-NEXT: sbfx x8, x0, #0, #121; CHECK-NEXT: whilelo p0.b, xzr, x822; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b23; CHECK-NEXT: ret24 %res = select i1 %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b25 ret <vscale x 16 x i8> %res26}27 28define <vscale x 1 x i16> @select_nxv1i16(i1 %cond, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b) {29; CHECK-LABEL: select_nxv1i16:30; CHECK: // %bb.0:31; CHECK-NEXT: // kill: def $w0 killed $w0 def $x032; CHECK-NEXT: sbfx x8, x0, #0, #133; CHECK-NEXT: whilelo p0.h, xzr, x834; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h35; CHECK-NEXT: ret36 %res = select i1 %cond, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b37 ret <vscale x 1 x i16> %res38}39 40define <vscale x 8 x i16> @select_nxv8i16(i1 %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {41; CHECK-LABEL: select_nxv8i16:42; CHECK: // %bb.0:43; CHECK-NEXT: // kill: def $w0 killed $w0 def $x044; CHECK-NEXT: sbfx x8, x0, #0, #145; CHECK-NEXT: whilelo p0.h, xzr, x846; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h47; CHECK-NEXT: ret48 %res = select i1 %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b49 ret <vscale x 8 x i16> %res50}51 52define <vscale x 1 x i32> @select_nxv1i32(i1 %cond, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {53; CHECK-LABEL: select_nxv1i32:54; CHECK: // %bb.0:55; CHECK-NEXT: // kill: def $w0 killed $w0 def $x056; CHECK-NEXT: sbfx x8, x0, #0, #157; CHECK-NEXT: whilelo p0.s, xzr, x858; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s59; CHECK-NEXT: ret60 %res = select i1 %cond, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b61 ret <vscale x 1 x i32> %res62}63 64define <vscale x 4 x i32> @select_nxv4i32(i1 %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {65; CHECK-LABEL: select_nxv4i32:66; CHECK: // %bb.0:67; CHECK-NEXT: // kill: def $w0 killed $w0 def $x068; CHECK-NEXT: sbfx x8, x0, #0, #169; CHECK-NEXT: whilelo p0.s, xzr, x870; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s71; CHECK-NEXT: ret72 %res = select i1 %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b73 ret <vscale x 4 x i32> %res74}75 76define <vscale x 1 x i64> @select_nxv1i64(i1 %cond, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {77; CHECK-LABEL: select_nxv1i64:78; CHECK: // %bb.0:79; CHECK-NEXT: // kill: def $w0 killed $w0 def $x080; CHECK-NEXT: sbfx x8, x0, #0, #181; CHECK-NEXT: whilelo p0.d, xzr, x882; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d83; CHECK-NEXT: ret84 %res = select i1 %cond, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b85 ret <vscale x 1 x i64> %res86}87 88define <vscale x 2 x i64> @select_nxv2i64(i1 %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {89; CHECK-LABEL: select_nxv2i64:90; CHECK: // %bb.0:91; CHECK-NEXT: // kill: def $w0 killed $w0 def $x092; CHECK-NEXT: sbfx x8, x0, #0, #193; CHECK-NEXT: whilelo p0.d, xzr, x894; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d95; CHECK-NEXT: ret96 %res = select i1 %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b97 ret <vscale x 2 x i64> %res98}99 100define <vscale x 8 x half> @select_nxv8f16(i1 %cond, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {101; CHECK-LABEL: select_nxv8f16:102; CHECK: // %bb.0:103; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0104; CHECK-NEXT: sbfx x8, x0, #0, #1105; CHECK-NEXT: whilelo p0.h, xzr, x8106; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h107; CHECK-NEXT: ret108 %res = select i1 %cond, <vscale x 8 x half> %a, <vscale x 8 x half> %b109 ret <vscale x 8 x half> %res110}111 112define <vscale x 4 x half> @select_nxv4f16(i1 %cond, <vscale x 4 x half> %a, <vscale x 4 x half> %b) {113; CHECK-LABEL: select_nxv4f16:114; CHECK: // %bb.0:115; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0116; CHECK-NEXT: sbfx x8, x0, #0, #1117; CHECK-NEXT: whilelo p0.s, xzr, x8118; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s119; CHECK-NEXT: ret120 %res = select i1 %cond, <vscale x 4 x half> %a, <vscale x 4 x half> %b121 ret <vscale x 4 x half> %res122}123 124define <vscale x 2 x half> @select_nxv2f16(i1 %cond, <vscale x 2 x half> %a, <vscale x 2 x half> %b) {125; CHECK-LABEL: select_nxv2f16:126; CHECK: // %bb.0:127; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0128; CHECK-NEXT: sbfx x8, x0, #0, #1129; CHECK-NEXT: whilelo p0.d, xzr, x8130; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d131; CHECK-NEXT: ret132 %res = select i1 %cond, <vscale x 2 x half> %a, <vscale x 2 x half> %b133 ret <vscale x 2 x half> %res134}135 136define <vscale x 4 x float> @select_nxv4f32(i1 %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {137; CHECK-LABEL: select_nxv4f32:138; CHECK: // %bb.0:139; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0140; CHECK-NEXT: sbfx x8, x0, #0, #1141; CHECK-NEXT: whilelo p0.s, xzr, x8142; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s143; CHECK-NEXT: ret144 %res = select i1 %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b145 ret <vscale x 4 x float> %res146}147 148define <vscale x 2 x float> @select_nxv2f32(i1 %cond, <vscale x 2 x float> %a, <vscale x 2 x float> %b) {149; CHECK-LABEL: select_nxv2f32:150; CHECK: // %bb.0:151; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0152; CHECK-NEXT: sbfx x8, x0, #0, #1153; CHECK-NEXT: whilelo p0.d, xzr, x8154; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d155; CHECK-NEXT: ret156 %res = select i1 %cond, <vscale x 2 x float> %a, <vscale x 2 x float> %b157 ret <vscale x 2 x float> %res158}159 160define <vscale x 2 x double> @select_nxv2f64(i1 %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {161; CHECK-LABEL: select_nxv2f64:162; CHECK: // %bb.0:163; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0164; CHECK-NEXT: sbfx x8, x0, #0, #1165; CHECK-NEXT: whilelo p0.d, xzr, x8166; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d167; CHECK-NEXT: ret168 %res = select i1 %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b169 ret <vscale x 2 x double> %res170}171 172define <vscale x 8 x bfloat> @select_nxv8bf16(i1 %cond, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {173; CHECK-LABEL: select_nxv8bf16:174; CHECK: // %bb.0:175; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0176; CHECK-NEXT: sbfx x8, x0, #0, #1177; CHECK-NEXT: whilelo p0.h, xzr, x8178; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h179; CHECK-NEXT: ret180 %res = select i1 %cond, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b181 ret <vscale x 8 x bfloat> %res182}183 184define <vscale x 4 x bfloat> @select_nxv4bf16(i1 %cond, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {185; CHECK-LABEL: select_nxv4bf16:186; CHECK: // %bb.0:187; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0188; CHECK-NEXT: sbfx x8, x0, #0, #1189; CHECK-NEXT: whilelo p0.s, xzr, x8190; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s191; CHECK-NEXT: ret192 %res = select i1 %cond, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b193 ret <vscale x 4 x bfloat> %res194}195 196define <vscale x 2 x bfloat> @select_nxv2bf16(i1 %cond, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {197; CHECK-LABEL: select_nxv2bf16:198; CHECK: // %bb.0:199; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0200; CHECK-NEXT: sbfx x8, x0, #0, #1201; CHECK-NEXT: whilelo p0.d, xzr, x8202; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d203; CHECK-NEXT: ret204 %res = select i1 %cond, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b205 ret <vscale x 2 x bfloat> %res206}207 208define <vscale x 16 x i1> @select_nxv16i1(i1 %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {209; CHECK-LABEL: select_nxv16i1:210; CHECK: // %bb.0:211; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0212; CHECK-NEXT: sbfx x8, x0, #0, #1213; CHECK-NEXT: whilelo p2.b, xzr, x8214; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b215; CHECK-NEXT: ret216 %res = select i1 %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b217 ret <vscale x 16 x i1> %res218}219 220define <vscale x 8 x i1> @select_nxv8i1(i1 %cond, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {221; CHECK-LABEL: select_nxv8i1:222; CHECK: // %bb.0:223; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0224; CHECK-NEXT: sbfx x8, x0, #0, #1225; CHECK-NEXT: whilelo p2.h, xzr, x8226; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b227; CHECK-NEXT: ret228 %res = select i1 %cond, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b229 ret <vscale x 8 x i1> %res230}231 232define <vscale x 4 x i1> @select_nxv4i1(i1 %cond, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {233; CHECK-LABEL: select_nxv4i1:234; CHECK: // %bb.0:235; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0236; CHECK-NEXT: sbfx x8, x0, #0, #1237; CHECK-NEXT: whilelo p2.s, xzr, x8238; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b239; CHECK-NEXT: ret240 %res = select i1 %cond, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b241 ret <vscale x 4 x i1> %res242}243 244define <vscale x 2 x i1> @select_nxv2i1(i1 %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {245; CHECK-LABEL: select_nxv2i1:246; CHECK: // %bb.0:247; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0248; CHECK-NEXT: sbfx x8, x0, #0, #1249; CHECK-NEXT: whilelo p2.d, xzr, x8250; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b251; CHECK-NEXT: ret252 %res = select i1 %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b253 ret <vscale x 2 x i1> %res254}255 256define <vscale x 1 x i1> @select_nxv1i1(i1 %cond, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {257; CHECK-LABEL: select_nxv1i1:258; CHECK: // %bb.0:259; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0260; CHECK-NEXT: sbfx x8, x0, #0, #1261; CHECK-NEXT: whilelo p2.d, xzr, x8262; CHECK-NEXT: punpklo p2.h, p2.b263; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b264; CHECK-NEXT: ret265 %res = select i1 %cond, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b266 ret <vscale x 1 x i1> %res267}268 269; Integer vector select270 271define <vscale x 16 x i8> @sel_nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %dst, <vscale x 16 x i8> %a) {272; CHECK-LABEL: sel_nxv16i8:273; CHECK: // %bb.0:274; CHECK-NEXT: mov z0.b, p0/m, z1.b275; CHECK-NEXT: ret276 %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %dst277 ret <vscale x 16 x i8> %sel278}279 280define <vscale x 8 x i16> @sel_nxv8i16(<vscale x 8 x i1> %p, <vscale x 8 x i16> %dst, <vscale x 8 x i16> %a) {281; CHECK-LABEL: sel_nxv8i16:282; CHECK: // %bb.0:283; CHECK-NEXT: mov z0.h, p0/m, z1.h284; CHECK-NEXT: ret285 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %a, <vscale x 8 x i16> %dst286 ret <vscale x 8 x i16> %sel287}288 289define <vscale x 4 x i32> @sel_nxv4i32(<vscale x 4 x i1> %p, <vscale x 4 x i32> %dst, <vscale x 4 x i32> %a) {290; CHECK-LABEL: sel_nxv4i32:291; CHECK: // %bb.0:292; CHECK-NEXT: mov z0.s, p0/m, z1.s293; CHECK-NEXT: ret294 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %a, <vscale x 4 x i32> %dst295 ret <vscale x 4 x i32> %sel296}297 298define <vscale x 1 x i64> @sel_nxv1i64(<vscale x 1 x i1> %p, <vscale x 1 x i64> %dst, <vscale x 1 x i64> %a) {299; CHECK-LABEL: sel_nxv1i64:300; CHECK: // %bb.0:301; CHECK-NEXT: uzp1 p0.d, p0.d, p0.d302; CHECK-NEXT: mov z0.d, p0/m, z1.d303; CHECK-NEXT: ret304 %sel = select <vscale x 1 x i1> %p, <vscale x 1 x i64> %a, <vscale x 1 x i64> %dst305 ret <vscale x 1 x i64> %sel306}307 308define <vscale x 2 x i64> @sel_nxv2i64(<vscale x 2 x i1> %p, <vscale x 2 x i64> %dst, <vscale x 2 x i64> %a) {309; CHECK-LABEL: sel_nxv2i64:310; CHECK: // %bb.0:311; CHECK-NEXT: mov z0.d, p0/m, z1.d312; CHECK-NEXT: ret313 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %a, <vscale x 2 x i64> %dst314 ret <vscale x 2 x i64> %sel315}316 317; Floating point vector select318 319define <vscale x 8 x half> @sel_nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %dst, <vscale x 8 x half> %a) {320; CHECK-LABEL: sel_nxv8f16:321; CHECK: // %bb.0:322; CHECK-NEXT: mov z0.h, p0/m, z1.h323; CHECK-NEXT: ret324 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %dst325 ret <vscale x 8 x half> %sel326}327 328define <vscale x 4 x float> @sel_nxv4f32(<vscale x 4 x i1> %p, <vscale x 4 x float> %dst, <vscale x 4 x float> %a) {329; CHECK-LABEL: sel_nxv4f32:330; CHECK: // %bb.0:331; CHECK-NEXT: mov z0.s, p0/m, z1.s332; CHECK-NEXT: ret333 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %dst334 ret <vscale x 4 x float> %sel335}336 337define <vscale x 2 x float> @sel_nxv2f32(<vscale x 2 x i1> %p, <vscale x 2 x float> %dst, <vscale x 2 x float> %a) {338; CHECK-LABEL: sel_nxv2f32:339; CHECK: // %bb.0:340; CHECK-NEXT: mov z0.d, p0/m, z1.d341; CHECK-NEXT: ret342 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> %a, <vscale x 2 x float> %dst343 ret <vscale x 2 x float> %sel344}345 346define <vscale x 2 x double> @sel_nxv8f64(<vscale x 2 x i1> %p, <vscale x 2 x double> %dst, <vscale x 2 x double> %a) {347; CHECK-LABEL: sel_nxv8f64:348; CHECK: // %bb.0:349; CHECK-NEXT: mov z0.d, p0/m, z1.d350; CHECK-NEXT: ret351 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %dst352 ret <vscale x 2 x double> %sel353}354 355; Check icmp+select356 357define <vscale x 2 x half> @icmp_select_nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i64 %x0) {358; CHECK-LABEL: icmp_select_nxv2f16:359; CHECK: // %bb.0:360; CHECK-NEXT: cmp x0, #0361; CHECK-NEXT: cset w8, eq362; CHECK-NEXT: sbfx x8, x8, #0, #1363; CHECK-NEXT: whilelo p0.d, xzr, x8364; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d365; CHECK-NEXT: ret366 %mask = icmp eq i64 %x0, 0367 %sel = select i1 %mask, <vscale x 2 x half> %a, <vscale x 2 x half> %b368 ret <vscale x 2 x half> %sel369}370 371define <vscale x 2 x float> @icmp_select_nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i64 %x0) {372; CHECK-LABEL: icmp_select_nxv2f32:373; CHECK: // %bb.0:374; CHECK-NEXT: cmp x0, #0375; CHECK-NEXT: cset w8, eq376; CHECK-NEXT: sbfx x8, x8, #0, #1377; CHECK-NEXT: whilelo p0.d, xzr, x8378; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d379; CHECK-NEXT: ret380 %mask = icmp eq i64 %x0, 0381 %sel = select i1 %mask, <vscale x 2 x float> %a, <vscale x 2 x float> %b382 ret <vscale x 2 x float> %sel383}384 385define <vscale x 2 x double> @icmp_select_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i64 %x0) {386; CHECK-LABEL: icmp_select_nxv2f64:387; CHECK: // %bb.0:388; CHECK-NEXT: cmp x0, #0389; CHECK-NEXT: cset w8, eq390; CHECK-NEXT: sbfx x8, x8, #0, #1391; CHECK-NEXT: whilelo p0.d, xzr, x8392; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d393; CHECK-NEXT: ret394 %mask = icmp eq i64 %x0, 0395 %sel = select i1 %mask, <vscale x 2 x double> %a, <vscale x 2 x double> %b396 ret <vscale x 2 x double> %sel397}398 399define <vscale x 2 x bfloat> @icmp_select_nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i64 %x0) {400; CHECK-LABEL: icmp_select_nxv2bf16:401; CHECK: // %bb.0:402; CHECK-NEXT: cmp x0, #0403; CHECK-NEXT: cset w8, eq404; CHECK-NEXT: sbfx x8, x8, #0, #1405; CHECK-NEXT: whilelo p0.d, xzr, x8406; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d407; CHECK-NEXT: ret408 %mask = icmp eq i64 %x0, 0409 %sel = select i1 %mask, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b410 ret <vscale x 2 x bfloat> %sel411}412 413define <vscale x 4 x half> @icmp_select_nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i64 %x0) {414; CHECK-LABEL: icmp_select_nxv4f16:415; CHECK: // %bb.0:416; CHECK-NEXT: cmp x0, #0417; CHECK-NEXT: cset w8, eq418; CHECK-NEXT: sbfx x8, x8, #0, #1419; CHECK-NEXT: whilelo p0.s, xzr, x8420; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s421; CHECK-NEXT: ret422 %mask = icmp eq i64 %x0, 0423 %sel = select i1 %mask, <vscale x 4 x half> %a, <vscale x 4 x half> %b424 ret <vscale x 4 x half> %sel425}426 427define <vscale x 4 x float> @icmp_select_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i64 %x0) {428; CHECK-LABEL: icmp_select_nxv4f32:429; CHECK: // %bb.0:430; CHECK-NEXT: cmp x0, #0431; CHECK-NEXT: cset w8, eq432; CHECK-NEXT: sbfx x8, x8, #0, #1433; CHECK-NEXT: whilelo p0.s, xzr, x8434; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s435; CHECK-NEXT: ret436 %mask = icmp eq i64 %x0, 0437 %sel = select i1 %mask, <vscale x 4 x float> %a, <vscale x 4 x float> %b438 ret <vscale x 4 x float> %sel439}440 441define <vscale x 4 x bfloat> @icmp_select_nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i64 %x0) {442; CHECK-LABEL: icmp_select_nxv4bf16:443; CHECK: // %bb.0:444; CHECK-NEXT: cmp x0, #0445; CHECK-NEXT: cset w8, eq446; CHECK-NEXT: sbfx x8, x8, #0, #1447; CHECK-NEXT: whilelo p0.s, xzr, x8448; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s449; CHECK-NEXT: ret450 %mask = icmp eq i64 %x0, 0451 %sel = select i1 %mask, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b452 ret <vscale x 4 x bfloat> %sel453}454 455define <vscale x 8 x half> @icmp_select_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i64 %x0) {456; CHECK-LABEL: icmp_select_nxv8f16:457; CHECK: // %bb.0:458; CHECK-NEXT: cmp x0, #0459; CHECK-NEXT: cset w8, eq460; CHECK-NEXT: sbfx x8, x8, #0, #1461; CHECK-NEXT: whilelo p0.h, xzr, x8462; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h463; CHECK-NEXT: ret464 %mask = icmp eq i64 %x0, 0465 %sel = select i1 %mask, <vscale x 8 x half> %a, <vscale x 8 x half> %b466 ret <vscale x 8 x half> %sel467}468 469define <vscale x 8 x bfloat> @icmp_select_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, i64 %x0) {470; CHECK-LABEL: icmp_select_nxv8bf16:471; CHECK: // %bb.0:472; CHECK-NEXT: cmp x0, #0473; CHECK-NEXT: cset w8, eq474; CHECK-NEXT: sbfx x8, x8, #0, #1475; CHECK-NEXT: whilelo p0.h, xzr, x8476; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h477; CHECK-NEXT: ret478 %mask = icmp eq i64 %x0, 0479 %sel = select i1 %mask, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b480 ret <vscale x 8 x bfloat> %sel481}482 483define <vscale x 1 x i64> @icmp_select_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i64 %x0) {484; CHECK-LABEL: icmp_select_nxv1i64:485; CHECK: // %bb.0:486; CHECK-NEXT: cmp x0, #0487; CHECK-NEXT: cset w8, eq488; CHECK-NEXT: sbfx x8, x8, #0, #1489; CHECK-NEXT: whilelo p0.d, xzr, x8490; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d491; CHECK-NEXT: ret492 %mask = icmp eq i64 %x0, 0493 %sel = select i1 %mask, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b494 ret <vscale x 1 x i64> %sel495}496 497define <vscale x 2 x i64> @icmp_select_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i64 %x0) {498; CHECK-LABEL: icmp_select_nxv2i64:499; CHECK: // %bb.0:500; CHECK-NEXT: cmp x0, #0501; CHECK-NEXT: cset w8, eq502; CHECK-NEXT: sbfx x8, x8, #0, #1503; CHECK-NEXT: whilelo p0.d, xzr, x8504; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d505; CHECK-NEXT: ret506 %mask = icmp eq i64 %x0, 0507 %sel = select i1 %mask, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b508 ret <vscale x 2 x i64> %sel509}510 511define <vscale x 1 x i32> @icmp_select_nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i64 %x0) {512; CHECK-LABEL: icmp_select_nxv1i32:513; CHECK: // %bb.0:514; CHECK-NEXT: cmp x0, #0515; CHECK-NEXT: cset w8, eq516; CHECK-NEXT: sbfx x8, x8, #0, #1517; CHECK-NEXT: whilelo p0.s, xzr, x8518; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s519; CHECK-NEXT: ret520 %mask = icmp eq i64 %x0, 0521 %sel = select i1 %mask, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b522 ret <vscale x 1 x i32> %sel523}524 525define <vscale x 4 x i32> @icmp_select_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i64 %x0) {526; CHECK-LABEL: icmp_select_nxv4i32:527; CHECK: // %bb.0:528; CHECK-NEXT: cmp x0, #0529; CHECK-NEXT: cset w8, eq530; CHECK-NEXT: sbfx x8, x8, #0, #1531; CHECK-NEXT: whilelo p0.s, xzr, x8532; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s533; CHECK-NEXT: ret534 %mask = icmp eq i64 %x0, 0535 %sel = select i1 %mask, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b536 ret <vscale x 4 x i32> %sel537}538 539define <vscale x 1 x i16> @icmp_select_nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i64 %x0) {540; CHECK-LABEL: icmp_select_nxv1i16:541; CHECK: // %bb.0:542; CHECK-NEXT: cmp x0, #0543; CHECK-NEXT: cset w8, eq544; CHECK-NEXT: sbfx x8, x8, #0, #1545; CHECK-NEXT: whilelo p0.h, xzr, x8546; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h547; CHECK-NEXT: ret548 %mask = icmp eq i64 %x0, 0549 %sel = select i1 %mask, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b550 ret <vscale x 1 x i16> %sel551}552 553define <vscale x 8 x i16> @icmp_select_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i64 %x0) {554; CHECK-LABEL: icmp_select_nxv8i16:555; CHECK: // %bb.0:556; CHECK-NEXT: cmp x0, #0557; CHECK-NEXT: cset w8, eq558; CHECK-NEXT: sbfx x8, x8, #0, #1559; CHECK-NEXT: whilelo p0.h, xzr, x8560; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h561; CHECK-NEXT: ret562 %mask = icmp eq i64 %x0, 0563 %sel = select i1 %mask, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b564 ret <vscale x 8 x i16> %sel565}566 567define <vscale x 1 x i8> @icmp_select_nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i64 %x0) {568; CHECK-LABEL: icmp_select_nxv1i8:569; CHECK: // %bb.0:570; CHECK-NEXT: cmp x0, #0571; CHECK-NEXT: cset w8, eq572; CHECK-NEXT: sbfx x8, x8, #0, #1573; CHECK-NEXT: whilelo p0.b, xzr, x8574; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b575; CHECK-NEXT: ret576 %mask = icmp eq i64 %x0, 0577 %sel = select i1 %mask, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b578 ret <vscale x 1 x i8> %sel579}580 581define <vscale x 16 x i8> @icmp_select_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 %x0) {582; CHECK-LABEL: icmp_select_nxv16i8:583; CHECK: // %bb.0:584; CHECK-NEXT: cmp x0, #0585; CHECK-NEXT: cset w8, eq586; CHECK-NEXT: sbfx x8, x8, #0, #1587; CHECK-NEXT: whilelo p0.b, xzr, x8588; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b589; CHECK-NEXT: ret590 %mask = icmp eq i64 %x0, 0591 %sel = select i1 %mask, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b592 ret <vscale x 16 x i8> %sel593}594 595define <vscale x 1 x i1> @icmp_select_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i64 %x0) {596; CHECK-LABEL: icmp_select_nxv1i1:597; CHECK: // %bb.0:598; CHECK-NEXT: cmp x0, #0599; CHECK-NEXT: cset w8, eq600; CHECK-NEXT: sbfx x8, x8, #0, #1601; CHECK-NEXT: whilelo p2.d, xzr, x8602; CHECK-NEXT: punpklo p2.h, p2.b603; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b604; CHECK-NEXT: ret605 %mask = icmp eq i64 %x0, 0606 %sel = select i1 %mask, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b607 ret <vscale x 1 x i1> %sel608}609 610define <vscale x 2 x i1> @icmp_select_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, i64 %x0) {611; CHECK-LABEL: icmp_select_nxv2i1:612; CHECK: // %bb.0:613; CHECK-NEXT: cmp x0, #0614; CHECK-NEXT: cset w8, eq615; CHECK-NEXT: sbfx x8, x8, #0, #1616; CHECK-NEXT: whilelo p2.d, xzr, x8617; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b618; CHECK-NEXT: ret619 %mask = icmp eq i64 %x0, 0620 %sel = select i1 %mask, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b621 ret <vscale x 2 x i1> %sel622}623define <vscale x 4 x i1> @icmp_select_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, i64 %x0) {624; CHECK-LABEL: icmp_select_nxv4i1:625; CHECK: // %bb.0:626; CHECK-NEXT: cmp x0, #0627; CHECK-NEXT: cset w8, eq628; CHECK-NEXT: sbfx x8, x8, #0, #1629; CHECK-NEXT: whilelo p2.s, xzr, x8630; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b631; CHECK-NEXT: ret632 %mask = icmp eq i64 %x0, 0633 %sel = select i1 %mask, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b634 ret <vscale x 4 x i1> %sel635}636define <vscale x 8 x i1> @icmp_select_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, i64 %x0) {637; CHECK-LABEL: icmp_select_nxv8i1:638; CHECK: // %bb.0:639; CHECK-NEXT: cmp x0, #0640; CHECK-NEXT: cset w8, eq641; CHECK-NEXT: sbfx x8, x8, #0, #1642; CHECK-NEXT: whilelo p2.h, xzr, x8643; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b644; CHECK-NEXT: ret645 %mask = icmp eq i64 %x0, 0646 %sel = select i1 %mask, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b647 ret <vscale x 8 x i1> %sel648}649define <vscale x 16 x i1> @icmp_select_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, i64 %x0) {650; CHECK-LABEL: icmp_select_nxv16i1:651; CHECK: // %bb.0:652; CHECK-NEXT: cmp x0, #0653; CHECK-NEXT: cset w8, eq654; CHECK-NEXT: sbfx x8, x8, #0, #1655; CHECK-NEXT: whilelo p2.b, xzr, x8656; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b657; CHECK-NEXT: ret658 %mask = icmp eq i64 %x0, 0659 %sel = select i1 %mask, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b660 ret <vscale x 16 x i1> %sel661}662 663define <vscale x 4 x float> @select_f32_invert_fmul(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {664; CHECK-LABEL: select_f32_invert_fmul:665; CHECK: // %bb.0:666; CHECK-NEXT: ptrue p0.s667; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0668; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s669; CHECK-NEXT: ret670 %p = fcmp oeq <vscale x 4 x float> %a, zeroinitializer671 %fmul = fmul <vscale x 4 x float> %a, %b672 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %fmul673 ret <vscale x 4 x float> %sel674}675 676define <vscale x 4 x float> @select_f32_invert_fadd(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {677; CHECK-LABEL: select_f32_invert_fadd:678; CHECK: // %bb.0:679; CHECK-NEXT: ptrue p0.s680; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0681; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s682; CHECK-NEXT: ret683 %p = fcmp oeq <vscale x 4 x float> %a, zeroinitializer684 %fadd = fadd <vscale x 4 x float> %a, %b685 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %fadd686 ret <vscale x 4 x float> %sel687}688 689define <vscale x 4 x float> @select_f32_invert_fsub(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x i32> %c) {690; CHECK-LABEL: select_f32_invert_fsub:691; CHECK: // %bb.0:692; CHECK-NEXT: ptrue p0.s693; CHECK-NEXT: cmpne p0.s, p0/z, z2.s, #0694; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s695; CHECK-NEXT: ret696 %p = icmp eq <vscale x 4 x i32> %c, zeroinitializer697 %fsub = fsub <vscale x 4 x float> %a, %b698 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %fsub699 ret <vscale x 4 x float> %sel700}701 702define <vscale x 4 x float> @select_f32_no_invert_op_lhs(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {703; CHECK-LABEL: select_f32_no_invert_op_lhs:704; CHECK: // %bb.0:705; CHECK-NEXT: ptrue p0.s706; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0707; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s708; CHECK-NEXT: ret709 %p = fcmp oeq <vscale x 4 x float> %a, zeroinitializer710 %fmul = fmul <vscale x 4 x float> %a, %b711 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %fmul, <vscale x 4 x float> %a712 ret <vscale x 4 x float> %sel713}714 715define <vscale x 4 x float> @select_f32_no_invert_2_op(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, <vscale x 4 x float> %d) {716; CHECK-LABEL: select_f32_no_invert_2_op:717; CHECK: // %bb.0:718; CHECK-NEXT: ptrue p0.s719; CHECK-NEXT: fmul z1.s, z0.s, z1.s720; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0721; CHECK-NEXT: fmul z0.s, z2.s, z3.s722; CHECK-NEXT: mov z0.s, p0/m, z1.s723; CHECK-NEXT: ret724 %p = fcmp oeq <vscale x 4 x float> %a, zeroinitializer725 %fmul1 = fmul <vscale x 4 x float> %a, %b726 %fmul2 = fmul <vscale x 4 x float> %c, %d727 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %fmul1, <vscale x 4 x float> %fmul2728 ret <vscale x 4 x float> %sel729}730 731define <vscale x 4 x float> @select_f32_no_invert_equal_ops(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {732; CHECK-LABEL: select_f32_no_invert_equal_ops:733; CHECK: // %bb.0:734; CHECK-NEXT: fmul z0.s, z0.s, z1.s735; CHECK-NEXT: ret736 %m = fmul <vscale x 4 x float> %a, %b737 %p = fcmp oeq <vscale x 4 x float> %m, zeroinitializer738 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %m, <vscale x 4 x float> %m739 ret <vscale x 4 x float> %sel740}741 742define <vscale x 4 x float> @select_f32_no_invert_fmul_two_setcc_uses(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, i32 %len) #0 {743; CHECK-LABEL: select_f32_no_invert_fmul_two_setcc_uses:744; CHECK: // %bb.0:745; CHECK-NEXT: ptrue p0.s746; CHECK-NEXT: fadd z1.s, z0.s, z1.s747; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0748; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s749; CHECK-NEXT: mov z0.s, p0/m, z2.s750; CHECK-NEXT: ret751 %p = fcmp oeq <vscale x 4 x float> %a, zeroinitializer752 %fadd = fadd <vscale x 4 x float> %a, %b753 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %fadd754 %sel2 = select <vscale x 4 x i1> %p, <vscale x 4 x float> %c, <vscale x 4 x float> %sel755 ret <vscale x 4 x float> %sel2756}757 758define <4 x float> @select_f32_no_invert_not_scalable(<4 x float> %a, <4 x float> %b) #0 {759; CHECK-LABEL: select_f32_no_invert_not_scalable:760; CHECK: // %bb.0:761; CHECK-NEXT: fcmeq v2.4s, v0.4s, #0.0762; CHECK-NEXT: fmul v1.4s, v0.4s, v1.4s763; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b764; CHECK-NEXT: ret765 %p = fcmp oeq <4 x float> %a, zeroinitializer766 %fmul = fmul <4 x float> %a, %b767 %sel = select <4 x i1> %p, <4 x float> %a, <4 x float> %fmul768 ret <4 x float> %sel769}770