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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s3 4define <vscale x 16 x i8> @sext_i1_i8(<vscale x 16 x i1> %a) {5; CHECK-LABEL: sext_i1_i8:6; CHECK: // %bb.0:7; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff8; CHECK-NEXT: ret9 %r = sext <vscale x 16 x i1> %a to <vscale x 16 x i8>10 ret <vscale x 16 x i8> %r11}12 13define <vscale x 8 x i16> @sext_i1_i16(<vscale x 8 x i1> %a) {14; CHECK-LABEL: sext_i1_i16:15; CHECK: // %bb.0:16; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff17; CHECK-NEXT: ret18 %r = sext <vscale x 8 x i1> %a to <vscale x 8 x i16>19 ret <vscale x 8 x i16> %r20}21 22define <vscale x 4 x i32> @sext_i1_i32(<vscale x 4 x i1> %a) {23; CHECK-LABEL: sext_i1_i32:24; CHECK: // %bb.0:25; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff26; CHECK-NEXT: ret27 %r = sext <vscale x 4 x i1> %a to <vscale x 4 x i32>28 ret <vscale x 4 x i32> %r29}30 31define <vscale x 2 x i64> @sext_i1_i64(<vscale x 2 x i1> %a) {32; CHECK-LABEL: sext_i1_i64:33; CHECK: // %bb.0:34; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff35; CHECK-NEXT: ret36 %r = sext <vscale x 2 x i1> %a to <vscale x 2 x i64>37 ret <vscale x 2 x i64> %r38}39 40define <vscale x 16 x i8> @zext_i1_i8(<vscale x 16 x i1> %a) {41; CHECK-LABEL: zext_i1_i8:42; CHECK: // %bb.0:43; CHECK-NEXT: mov z0.b, p0/z, #1 // =0x144; CHECK-NEXT: ret45 %r = zext <vscale x 16 x i1> %a to <vscale x 16 x i8>46 ret <vscale x 16 x i8> %r47}48 49define <vscale x 8 x i16> @zext_i1_i16(<vscale x 8 x i1> %a) {50; CHECK-LABEL: zext_i1_i16:51; CHECK: // %bb.0:52; CHECK-NEXT: mov z0.h, p0/z, #1 // =0x153; CHECK-NEXT: ret54 %r = zext <vscale x 8 x i1> %a to <vscale x 8 x i16>55 ret <vscale x 8 x i16> %r56}57 58define <vscale x 4 x i32> @zext_i1_i32(<vscale x 4 x i1> %a) {59; CHECK-LABEL: zext_i1_i32:60; CHECK: // %bb.0:61; CHECK-NEXT: mov z0.s, p0/z, #1 // =0x162; CHECK-NEXT: ret63 %r = zext <vscale x 4 x i1> %a to <vscale x 4 x i32>64 ret <vscale x 4 x i32> %r65}66 67define <vscale x 2 x i64> @zext_i1_i64(<vscale x 2 x i1> %a) {68; CHECK-LABEL: zext_i1_i64:69; CHECK: // %bb.0:70; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x171; CHECK-NEXT: ret72 %r = zext <vscale x 2 x i1> %a to <vscale x 2 x i64>73 ret <vscale x 2 x i64> %r74}75 76define <vscale x 8 x i16> @sext_i8_i16(<vscale x 8 x i8> %a) {77; CHECK-LABEL: sext_i8_i16:78; CHECK: // %bb.0:79; CHECK-NEXT: ptrue p0.h80; CHECK-NEXT: sxtb z0.h, p0/m, z0.h81; CHECK-NEXT: ret82 %r = sext <vscale x 8 x i8> %a to <vscale x 8 x i16>83 ret <vscale x 8 x i16> %r84}85 86define <vscale x 4 x i32> @sext_i8_i32(<vscale x 4 x i8> %a) {87; CHECK-LABEL: sext_i8_i32:88; CHECK: // %bb.0:89; CHECK-NEXT: ptrue p0.s90; CHECK-NEXT: sxtb z0.s, p0/m, z0.s91; CHECK-NEXT: ret92 %r = sext <vscale x 4 x i8> %a to <vscale x 4 x i32>93 ret <vscale x 4 x i32> %r94}95 96define <vscale x 2 x i64> @sext_i8_i64(<vscale x 2 x i8> %a) {97; CHECK-LABEL: sext_i8_i64:98; CHECK: // %bb.0:99; CHECK-NEXT: ptrue p0.d100; CHECK-NEXT: sxtb z0.d, p0/m, z0.d101; CHECK-NEXT: ret102 %r = sext <vscale x 2 x i8> %a to <vscale x 2 x i64>103 ret <vscale x 2 x i64> %r104}105 106define <vscale x 8 x i16> @zext_i8_i16(<vscale x 8 x i8> %a) {107; CHECK-LABEL: zext_i8_i16:108; CHECK: // %bb.0:109; CHECK-NEXT: and z0.h, z0.h, #0xff110; CHECK-NEXT: ret111 %r = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>112 ret <vscale x 8 x i16> %r113}114 115define <vscale x 4 x i32> @zext_i8_i32(<vscale x 4 x i8> %a) {116; CHECK-LABEL: zext_i8_i32:117; CHECK: // %bb.0:118; CHECK-NEXT: and z0.s, z0.s, #0xff119; CHECK-NEXT: ret120 %r = zext <vscale x 4 x i8> %a to <vscale x 4 x i32>121 ret <vscale x 4 x i32> %r122}123 124define <vscale x 2 x i64> @zext_i8_i64(<vscale x 2 x i8> %a) {125; CHECK-LABEL: zext_i8_i64:126; CHECK: // %bb.0:127; CHECK-NEXT: and z0.d, z0.d, #0xff128; CHECK-NEXT: ret129 %r = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>130 ret <vscale x 2 x i64> %r131}132 133define <vscale x 4 x i32> @sext_i16_i32(<vscale x 4 x i16> %a) {134; CHECK-LABEL: sext_i16_i32:135; CHECK: // %bb.0:136; CHECK-NEXT: ptrue p0.s137; CHECK-NEXT: sxth z0.s, p0/m, z0.s138; CHECK-NEXT: ret139 %r = sext <vscale x 4 x i16> %a to <vscale x 4 x i32>140 ret <vscale x 4 x i32> %r141}142 143define <vscale x 2 x i64> @sext_i16_i64(<vscale x 2 x i16> %a) {144; CHECK-LABEL: sext_i16_i64:145; CHECK: // %bb.0:146; CHECK-NEXT: ptrue p0.d147; CHECK-NEXT: sxth z0.d, p0/m, z0.d148; CHECK-NEXT: ret149 %r = sext <vscale x 2 x i16> %a to <vscale x 2 x i64>150 ret <vscale x 2 x i64> %r151}152 153define <vscale x 4 x i32> @zext_i16_i32(<vscale x 4 x i16> %a) {154; CHECK-LABEL: zext_i16_i32:155; CHECK: // %bb.0:156; CHECK-NEXT: and z0.s, z0.s, #0xffff157; CHECK-NEXT: ret158 %r = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>159 ret <vscale x 4 x i32> %r160}161 162define <vscale x 2 x i64> @zext_i16_i64(<vscale x 2 x i16> %a) {163; CHECK-LABEL: zext_i16_i64:164; CHECK: // %bb.0:165; CHECK-NEXT: and z0.d, z0.d, #0xffff166; CHECK-NEXT: ret167 %r = zext <vscale x 2 x i16> %a to <vscale x 2 x i64>168 ret <vscale x 2 x i64> %r169}170 171define <vscale x 2 x i64> @sext_i32_i64(<vscale x 2 x i32> %a) {172; CHECK-LABEL: sext_i32_i64:173; CHECK: // %bb.0:174; CHECK-NEXT: ptrue p0.d175; CHECK-NEXT: sxtw z0.d, p0/m, z0.d176; CHECK-NEXT: ret177 %r = sext <vscale x 2 x i32> %a to <vscale x 2 x i64>178 ret <vscale x 2 x i64> %r179}180 181define <vscale x 2 x i64> @zext_i32_i64(<vscale x 2 x i32> %a) {182; CHECK-LABEL: zext_i32_i64:183; CHECK: // %bb.0:184; CHECK-NEXT: and z0.d, z0.d, #0xffffffff185; CHECK-NEXT: ret186 %r = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>187 ret <vscale x 2 x i64> %r188}189 190; Extending to illegal types191 192define <vscale x 16 x i16> @sext_b_to_h(<vscale x 16 x i8> %a) {193; CHECK-LABEL: sext_b_to_h:194; CHECK: // %bb.0:195; CHECK-NEXT: sunpklo z2.h, z0.b196; CHECK-NEXT: sunpkhi z1.h, z0.b197; CHECK-NEXT: mov z0.d, z2.d198; CHECK-NEXT: ret199 %ext = sext <vscale x 16 x i8> %a to <vscale x 16 x i16>200 ret <vscale x 16 x i16> %ext201}202 203define <vscale x 8 x i32> @sext_h_to_s(<vscale x 8 x i16> %a) {204; CHECK-LABEL: sext_h_to_s:205; CHECK: // %bb.0:206; CHECK-NEXT: sunpklo z2.s, z0.h207; CHECK-NEXT: sunpkhi z1.s, z0.h208; CHECK-NEXT: mov z0.d, z2.d209; CHECK-NEXT: ret210 %ext = sext <vscale x 8 x i16> %a to <vscale x 8 x i32>211 ret <vscale x 8 x i32> %ext212}213 214define <vscale x 4 x i64> @sext_s_to_d(<vscale x 4 x i32> %a) {215; CHECK-LABEL: sext_s_to_d:216; CHECK: // %bb.0:217; CHECK-NEXT: sunpklo z2.d, z0.s218; CHECK-NEXT: sunpkhi z1.d, z0.s219; CHECK-NEXT: mov z0.d, z2.d220; CHECK-NEXT: ret221 %ext = sext <vscale x 4 x i32> %a to <vscale x 4 x i64>222 ret <vscale x 4 x i64> %ext223}224 225define <vscale x 16 x i32> @sext_b_to_s(<vscale x 16 x i8> %a) {226; CHECK-LABEL: sext_b_to_s:227; CHECK: // %bb.0:228; CHECK-NEXT: sunpklo z1.h, z0.b229; CHECK-NEXT: sunpkhi z3.h, z0.b230; CHECK-NEXT: sunpklo z0.s, z1.h231; CHECK-NEXT: sunpkhi z1.s, z1.h232; CHECK-NEXT: sunpklo z2.s, z3.h233; CHECK-NEXT: sunpkhi z3.s, z3.h234; CHECK-NEXT: ret235 %ext = sext <vscale x 16 x i8> %a to <vscale x 16 x i32>236 ret <vscale x 16 x i32> %ext237}238 239define <vscale x 16 x i64> @sext_b_to_d(<vscale x 16 x i8> %a) {240; CHECK-LABEL: sext_b_to_d:241; CHECK: // %bb.0:242; CHECK-NEXT: sunpklo z1.h, z0.b243; CHECK-NEXT: sunpkhi z0.h, z0.b244; CHECK-NEXT: sunpklo z2.s, z1.h245; CHECK-NEXT: sunpkhi z3.s, z1.h246; CHECK-NEXT: sunpklo z5.s, z0.h247; CHECK-NEXT: sunpkhi z7.s, z0.h248; CHECK-NEXT: sunpklo z0.d, z2.s249; CHECK-NEXT: sunpkhi z1.d, z2.s250; CHECK-NEXT: sunpklo z2.d, z3.s251; CHECK-NEXT: sunpkhi z3.d, z3.s252; CHECK-NEXT: sunpklo z4.d, z5.s253; CHECK-NEXT: sunpkhi z5.d, z5.s254; CHECK-NEXT: sunpklo z6.d, z7.s255; CHECK-NEXT: sunpkhi z7.d, z7.s256; CHECK-NEXT: ret257 %ext = sext <vscale x 16 x i8> %a to <vscale x 16 x i64>258 ret <vscale x 16 x i64> %ext259}260 261define <vscale x 16 x i16> @zext_b_to_h(<vscale x 16 x i8> %a) {262; CHECK-LABEL: zext_b_to_h:263; CHECK: // %bb.0:264; CHECK-NEXT: uunpklo z2.h, z0.b265; CHECK-NEXT: uunpkhi z1.h, z0.b266; CHECK-NEXT: mov z0.d, z2.d267; CHECK-NEXT: ret268 %ext = zext <vscale x 16 x i8> %a to <vscale x 16 x i16>269 ret <vscale x 16 x i16> %ext270}271 272define <vscale x 8 x i32> @zext_h_to_s(<vscale x 8 x i16> %a) {273; CHECK-LABEL: zext_h_to_s:274; CHECK: // %bb.0:275; CHECK-NEXT: uunpklo z2.s, z0.h276; CHECK-NEXT: uunpkhi z1.s, z0.h277; CHECK-NEXT: mov z0.d, z2.d278; CHECK-NEXT: ret279 %ext = zext <vscale x 8 x i16> %a to <vscale x 8 x i32>280 ret <vscale x 8 x i32> %ext281}282 283define <vscale x 4 x i64> @zext_s_to_d(<vscale x 4 x i32> %a) {284; CHECK-LABEL: zext_s_to_d:285; CHECK: // %bb.0:286; CHECK-NEXT: uunpklo z2.d, z0.s287; CHECK-NEXT: uunpkhi z1.d, z0.s288; CHECK-NEXT: mov z0.d, z2.d289; CHECK-NEXT: ret290 %ext = zext <vscale x 4 x i32> %a to <vscale x 4 x i64>291 ret <vscale x 4 x i64> %ext292}293 294define <vscale x 16 x i32> @zext_b_to_s(<vscale x 16 x i8> %a) {295; CHECK-LABEL: zext_b_to_s:296; CHECK: // %bb.0:297; CHECK-NEXT: uunpklo z1.h, z0.b298; CHECK-NEXT: uunpkhi z3.h, z0.b299; CHECK-NEXT: uunpklo z0.s, z1.h300; CHECK-NEXT: uunpkhi z1.s, z1.h301; CHECK-NEXT: uunpklo z2.s, z3.h302; CHECK-NEXT: uunpkhi z3.s, z3.h303; CHECK-NEXT: ret304 %ext = zext <vscale x 16 x i8> %a to <vscale x 16 x i32>305 ret <vscale x 16 x i32> %ext306}307 308define <vscale x 16 x i64> @zext_b_to_d(<vscale x 16 x i8> %a) {309; CHECK-LABEL: zext_b_to_d:310; CHECK: // %bb.0:311; CHECK-NEXT: uunpklo z1.h, z0.b312; CHECK-NEXT: uunpkhi z0.h, z0.b313; CHECK-NEXT: uunpklo z2.s, z1.h314; CHECK-NEXT: uunpkhi z3.s, z1.h315; CHECK-NEXT: uunpklo z5.s, z0.h316; CHECK-NEXT: uunpkhi z7.s, z0.h317; CHECK-NEXT: uunpklo z0.d, z2.s318; CHECK-NEXT: uunpkhi z1.d, z2.s319; CHECK-NEXT: uunpklo z2.d, z3.s320; CHECK-NEXT: uunpkhi z3.d, z3.s321; CHECK-NEXT: uunpklo z4.d, z5.s322; CHECK-NEXT: uunpkhi z5.d, z5.s323; CHECK-NEXT: uunpklo z6.d, z7.s324; CHECK-NEXT: uunpkhi z7.d, z7.s325; CHECK-NEXT: ret326 %ext = zext <vscale x 16 x i8> %a to <vscale x 16 x i64>327 ret <vscale x 16 x i64> %ext328}329 330; Extending unpacked data to wide, illegal types331 332define <vscale x 4 x i64> @zext_4i8_4i64(<vscale x 4 x i8> %aval) {333; CHECK-LABEL: zext_4i8_4i64:334; CHECK: // %bb.0:335; CHECK-NEXT: and z0.s, z0.s, #0xff336; CHECK-NEXT: uunpklo z2.d, z0.s337; CHECK-NEXT: uunpkhi z1.d, z0.s338; CHECK-NEXT: mov z0.d, z2.d339; CHECK-NEXT: ret340 %aext = zext <vscale x 4 x i8> %aval to <vscale x 4 x i64>341 ret <vscale x 4 x i64> %aext342}343 344define <vscale x 4 x i64> @zext_4i16_4i64(<vscale x 4 x i16> %aval) {345; CHECK-LABEL: zext_4i16_4i64:346; CHECK: // %bb.0:347; CHECK-NEXT: and z0.s, z0.s, #0xffff348; CHECK-NEXT: uunpklo z2.d, z0.s349; CHECK-NEXT: uunpkhi z1.d, z0.s350; CHECK-NEXT: mov z0.d, z2.d351; CHECK-NEXT: ret352 %aext = zext <vscale x 4 x i16> %aval to <vscale x 4 x i64>353 ret <vscale x 4 x i64> %aext354}355 356define <vscale x 8 x i32> @zext_8i8_8i32(<vscale x 8 x i8> %aval) {357; CHECK-LABEL: zext_8i8_8i32:358; CHECK: // %bb.0:359; CHECK-NEXT: and z0.h, z0.h, #0xff360; CHECK-NEXT: uunpklo z2.s, z0.h361; CHECK-NEXT: uunpkhi z1.s, z0.h362; CHECK-NEXT: mov z0.d, z2.d363; CHECK-NEXT: ret364 %aext = zext <vscale x 8 x i8> %aval to <vscale x 8 x i32>365 ret <vscale x 8 x i32> %aext366}367 368define <vscale x 8 x i64> @zext_8i8_8i64(<vscale x 8 x i8> %aval) {369; CHECK-LABEL: zext_8i8_8i64:370; CHECK: // %bb.0:371; CHECK-NEXT: and z0.h, z0.h, #0xff372; CHECK-NEXT: uunpklo z1.s, z0.h373; CHECK-NEXT: uunpkhi z3.s, z0.h374; CHECK-NEXT: uunpklo z0.d, z1.s375; CHECK-NEXT: uunpkhi z1.d, z1.s376; CHECK-NEXT: uunpklo z2.d, z3.s377; CHECK-NEXT: uunpkhi z3.d, z3.s378; CHECK-NEXT: ret379 %aext = zext <vscale x 8 x i8> %aval to <vscale x 8 x i64>380 ret <vscale x 8 x i64> %aext381}382 383define <vscale x 4 x i64> @sext_4i8_4i64(<vscale x 4 x i8> %aval) {384; CHECK-LABEL: sext_4i8_4i64:385; CHECK: // %bb.0:386; CHECK-NEXT: ptrue p0.s387; CHECK-NEXT: movprfx z1, z0388; CHECK-NEXT: sxtb z1.s, p0/m, z0.s389; CHECK-NEXT: sunpklo z0.d, z1.s390; CHECK-NEXT: sunpkhi z1.d, z1.s391; CHECK-NEXT: ret392 %aext = sext <vscale x 4 x i8> %aval to <vscale x 4 x i64>393 ret <vscale x 4 x i64> %aext394}395 396define <vscale x 4 x i64> @sext_4i16_4i64(<vscale x 4 x i16> %aval) {397; CHECK-LABEL: sext_4i16_4i64:398; CHECK: // %bb.0:399; CHECK-NEXT: ptrue p0.s400; CHECK-NEXT: movprfx z1, z0401; CHECK-NEXT: sxth z1.s, p0/m, z0.s402; CHECK-NEXT: sunpklo z0.d, z1.s403; CHECK-NEXT: sunpkhi z1.d, z1.s404; CHECK-NEXT: ret405 %aext = sext <vscale x 4 x i16> %aval to <vscale x 4 x i64>406 ret <vscale x 4 x i64> %aext407}408 409define <vscale x 8 x i32> @sext_8i8_8i32(<vscale x 8 x i8> %aval) {410; CHECK-LABEL: sext_8i8_8i32:411; CHECK: // %bb.0:412; CHECK-NEXT: ptrue p0.h413; CHECK-NEXT: movprfx z1, z0414; CHECK-NEXT: sxtb z1.h, p0/m, z0.h415; CHECK-NEXT: sunpklo z0.s, z1.h416; CHECK-NEXT: sunpkhi z1.s, z1.h417; CHECK-NEXT: ret418 %aext = sext <vscale x 8 x i8> %aval to <vscale x 8 x i32>419 ret <vscale x 8 x i32> %aext420}421 422define <vscale x 8 x i64> @sext_8i8_8i64(<vscale x 8 x i8> %aval) {423; CHECK-LABEL: sext_8i8_8i64:424; CHECK: // %bb.0:425; CHECK-NEXT: ptrue p0.h426; CHECK-NEXT: sxtb z0.h, p0/m, z0.h427; CHECK-NEXT: sunpklo z1.s, z0.h428; CHECK-NEXT: sunpkhi z3.s, z0.h429; CHECK-NEXT: sunpklo z0.d, z1.s430; CHECK-NEXT: sunpkhi z1.d, z1.s431; CHECK-NEXT: sunpklo z2.d, z3.s432; CHECK-NEXT: sunpkhi z3.d, z3.s433; CHECK-NEXT: ret434 %aext = sext <vscale x 8 x i8> %aval to <vscale x 8 x i64>435 ret <vscale x 8 x i64> %aext436}437 438 439; Extending non power-of-two types440 441define <vscale x 2 x i64> @sext_i18_i64(<vscale x 2 x i18> %a) {442; CHECK-LABEL: sext_i18_i64:443; CHECK: // %bb.0:444; CHECK-NEXT: lsl z0.d, z0.d, #46445; CHECK-NEXT: asr z0.d, z0.d, #46446; CHECK-NEXT: ret447 %r = sext <vscale x 2 x i18> %a to <vscale x 2 x i64>448 ret <vscale x 2 x i64> %r449}450 451define <vscale x 2 x i64> @zext_i18_i64(<vscale x 2 x i18> %a) {452; CHECK-LABEL: zext_i18_i64:453; CHECK: // %bb.0:454; CHECK-NEXT: and z0.d, z0.d, #0x3ffff455; CHECK-NEXT: ret456 %r = zext <vscale x 2 x i18> %a to <vscale x 2 x i64>457 ret <vscale x 2 x i64> %r458}459