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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s3 4declare { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)5 6define <vscale x 2 x i8> @smulo_nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y) {7; CHECK-LABEL: smulo_nxv2i8:8; CHECK: // %bb.0:9; CHECK-NEXT: ptrue p0.d10; CHECK-NEXT: sxtb z1.d, p0/m, z1.d11; CHECK-NEXT: sxtb z0.d, p0/m, z0.d12; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d13; CHECK-NEXT: movprfx z1, z014; CHECK-NEXT: sxtb z1.d, p0/m, z0.d15; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, z0.d16; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x017; CHECK-NEXT: ret18 %a = call { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y)19 %b = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 020 %c = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 121 %d = select <vscale x 2 x i1> %c, <vscale x 2 x i8> zeroinitializer, <vscale x 2 x i8> %b22 ret <vscale x 2 x i8> %d23}24 25declare { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)26 27define <vscale x 4 x i8> @smulo_nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y) {28; CHECK-LABEL: smulo_nxv4i8:29; CHECK: // %bb.0:30; CHECK-NEXT: ptrue p0.s31; CHECK-NEXT: sxtb z1.s, p0/m, z1.s32; CHECK-NEXT: sxtb z0.s, p0/m, z0.s33; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s34; CHECK-NEXT: movprfx z1, z035; CHECK-NEXT: sxtb z1.s, p0/m, z0.s36; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, z0.s37; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x038; CHECK-NEXT: ret39 %a = call { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y)40 %b = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 041 %c = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 142 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i8> zeroinitializer, <vscale x 4 x i8> %b43 ret <vscale x 4 x i8> %d44}45 46declare { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)47 48define <vscale x 8 x i8> @smulo_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {49; CHECK-LABEL: smulo_nxv8i8:50; CHECK: // %bb.0:51; CHECK-NEXT: ptrue p0.h52; CHECK-NEXT: sxtb z1.h, p0/m, z1.h53; CHECK-NEXT: sxtb z0.h, p0/m, z0.h54; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h55; CHECK-NEXT: movprfx z1, z056; CHECK-NEXT: sxtb z1.h, p0/m, z0.h57; CHECK-NEXT: cmpne p0.h, p0/z, z1.h, z0.h58; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x059; CHECK-NEXT: ret60 %a = call { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y)61 %b = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 062 %c = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 163 %d = select <vscale x 8 x i1> %c, <vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> %b64 ret <vscale x 8 x i8> %d65}66 67declare { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)68 69define <vscale x 16 x i8> @smulo_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {70; CHECK-LABEL: smulo_nxv16i8:71; CHECK: // %bb.0:72; CHECK-NEXT: ptrue p0.b73; CHECK-NEXT: movprfx z2, z074; CHECK-NEXT: mul z2.b, p0/m, z2.b, z1.b75; CHECK-NEXT: smulh z0.b, p0/m, z0.b, z1.b76; CHECK-NEXT: asr z1.b, z2.b, #777; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, z1.b78; CHECK-NEXT: mov z2.b, p0/m, #0 // =0x079; CHECK-NEXT: mov z0.d, z2.d80; CHECK-NEXT: ret81 %a = call { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)82 %b = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 083 %c = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 184 %d = select <vscale x 16 x i1> %c, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %b85 ret <vscale x 16 x i8> %d86}87 88declare { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>)89 90define <vscale x 32 x i8> @smulo_nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y) {91; CHECK-LABEL: smulo_nxv32i8:92; CHECK: // %bb.0:93; CHECK-NEXT: ptrue p0.b94; CHECK-NEXT: movprfx z4, z195; CHECK-NEXT: mul z4.b, p0/m, z4.b, z3.b96; CHECK-NEXT: movprfx z5, z097; CHECK-NEXT: mul z5.b, p0/m, z5.b, z2.b98; CHECK-NEXT: smulh z1.b, p0/m, z1.b, z3.b99; CHECK-NEXT: smulh z0.b, p0/m, z0.b, z2.b100; CHECK-NEXT: asr z2.b, z4.b, #7101; CHECK-NEXT: asr z3.b, z5.b, #7102; CHECK-NEXT: cmpne p1.b, p0/z, z1.b, z2.b103; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, z3.b104; CHECK-NEXT: mov z5.b, p0/m, #0 // =0x0105; CHECK-NEXT: mov z4.b, p1/m, #0 // =0x0106; CHECK-NEXT: mov z0.d, z5.d107; CHECK-NEXT: mov z1.d, z4.d108; CHECK-NEXT: ret109 %a = call { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y)110 %b = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 0111 %c = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 1112 %d = select <vscale x 32 x i1> %c, <vscale x 32 x i8> zeroinitializer, <vscale x 32 x i8> %b113 ret <vscale x 32 x i8> %d114}115 116declare { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.smul.with.overflow.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>)117 118define <vscale x 64 x i8> @smulo_nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y) {119; CHECK-LABEL: smulo_nxv64i8:120; CHECK: // %bb.0:121; CHECK-NEXT: ptrue p0.b122; CHECK-NEXT: movprfx z24, z3123; CHECK-NEXT: mul z24.b, p0/m, z24.b, z7.b124; CHECK-NEXT: movprfx z25, z0125; CHECK-NEXT: mul z25.b, p0/m, z25.b, z4.b126; CHECK-NEXT: movprfx z26, z2127; CHECK-NEXT: mul z26.b, p0/m, z26.b, z6.b128; CHECK-NEXT: movprfx z27, z1129; CHECK-NEXT: mul z27.b, p0/m, z27.b, z5.b130; CHECK-NEXT: smulh z3.b, p0/m, z3.b, z7.b131; CHECK-NEXT: smulh z0.b, p0/m, z0.b, z4.b132; CHECK-NEXT: smulh z2.b, p0/m, z2.b, z6.b133; CHECK-NEXT: smulh z1.b, p0/m, z1.b, z5.b134; CHECK-NEXT: asr z4.b, z25.b, #7135; CHECK-NEXT: asr z5.b, z24.b, #7136; CHECK-NEXT: asr z6.b, z26.b, #7137; CHECK-NEXT: asr z7.b, z27.b, #7138; CHECK-NEXT: cmpne p1.b, p0/z, z0.b, z4.b139; CHECK-NEXT: cmpne p2.b, p0/z, z3.b, z5.b140; CHECK-NEXT: cmpne p3.b, p0/z, z2.b, z6.b141; CHECK-NEXT: cmpne p0.b, p0/z, z1.b, z7.b142; CHECK-NEXT: mov z25.b, p1/m, #0 // =0x0143; CHECK-NEXT: mov z26.b, p3/m, #0 // =0x0144; CHECK-NEXT: mov z24.b, p2/m, #0 // =0x0145; CHECK-NEXT: mov z27.b, p0/m, #0 // =0x0146; CHECK-NEXT: mov z0.d, z25.d147; CHECK-NEXT: mov z2.d, z26.d148; CHECK-NEXT: mov z3.d, z24.d149; CHECK-NEXT: mov z1.d, z27.d150; CHECK-NEXT: ret151 %a = call { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.smul.with.overflow.nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y)152 %b = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 0153 %c = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 1154 %d = select <vscale x 64 x i1> %c, <vscale x 64 x i8> zeroinitializer, <vscale x 64 x i8> %b155 ret <vscale x 64 x i8> %d156}157 158declare { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)159 160define <vscale x 2 x i16> @smulo_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y) {161; CHECK-LABEL: smulo_nxv2i16:162; CHECK: // %bb.0:163; CHECK-NEXT: ptrue p0.d164; CHECK-NEXT: sxth z1.d, p0/m, z1.d165; CHECK-NEXT: sxth z0.d, p0/m, z0.d166; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d167; CHECK-NEXT: movprfx z1, z0168; CHECK-NEXT: sxth z1.d, p0/m, z0.d169; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, z0.d170; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0171; CHECK-NEXT: ret172 %a = call { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y)173 %b = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 0174 %c = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 1175 %d = select <vscale x 2 x i1> %c, <vscale x 2 x i16> zeroinitializer, <vscale x 2 x i16> %b176 ret <vscale x 2 x i16> %d177}178 179declare { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)180 181define <vscale x 4 x i16> @smulo_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y) {182; CHECK-LABEL: smulo_nxv4i16:183; CHECK: // %bb.0:184; CHECK-NEXT: ptrue p0.s185; CHECK-NEXT: sxth z1.s, p0/m, z1.s186; CHECK-NEXT: sxth z0.s, p0/m, z0.s187; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s188; CHECK-NEXT: movprfx z1, z0189; CHECK-NEXT: sxth z1.s, p0/m, z0.s190; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, z0.s191; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0192; CHECK-NEXT: ret193 %a = call { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y)194 %b = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 0195 %c = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 1196 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i16> zeroinitializer, <vscale x 4 x i16> %b197 ret <vscale x 4 x i16> %d198}199 200declare { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)201 202define <vscale x 8 x i16> @smulo_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {203; CHECK-LABEL: smulo_nxv8i16:204; CHECK: // %bb.0:205; CHECK-NEXT: ptrue p0.h206; CHECK-NEXT: movprfx z2, z0207; CHECK-NEXT: mul z2.h, p0/m, z2.h, z1.h208; CHECK-NEXT: smulh z0.h, p0/m, z0.h, z1.h209; CHECK-NEXT: asr z1.h, z2.h, #15210; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z1.h211; CHECK-NEXT: mov z2.h, p0/m, #0 // =0x0212; CHECK-NEXT: mov z0.d, z2.d213; CHECK-NEXT: ret214 %a = call { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)215 %b = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 0216 %c = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 1217 %d = select <vscale x 8 x i1> %c, <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i16> %b218 ret <vscale x 8 x i16> %d219}220 221declare { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)222 223define <vscale x 16 x i16> @smulo_nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y) {224; CHECK-LABEL: smulo_nxv16i16:225; CHECK: // %bb.0:226; CHECK-NEXT: ptrue p0.h227; CHECK-NEXT: movprfx z4, z1228; CHECK-NEXT: mul z4.h, p0/m, z4.h, z3.h229; CHECK-NEXT: movprfx z5, z0230; CHECK-NEXT: mul z5.h, p0/m, z5.h, z2.h231; CHECK-NEXT: smulh z1.h, p0/m, z1.h, z3.h232; CHECK-NEXT: smulh z0.h, p0/m, z0.h, z2.h233; CHECK-NEXT: asr z2.h, z4.h, #15234; CHECK-NEXT: asr z3.h, z5.h, #15235; CHECK-NEXT: cmpne p1.h, p0/z, z1.h, z2.h236; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z3.h237; CHECK-NEXT: mov z5.h, p0/m, #0 // =0x0238; CHECK-NEXT: mov z4.h, p1/m, #0 // =0x0239; CHECK-NEXT: mov z0.d, z5.d240; CHECK-NEXT: mov z1.d, z4.d241; CHECK-NEXT: ret242 %a = call { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y)243 %b = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 0244 %c = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 1245 %d = select <vscale x 16 x i1> %c, <vscale x 16 x i16> zeroinitializer, <vscale x 16 x i16> %b246 ret <vscale x 16 x i16> %d247}248 249declare { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>)250 251define <vscale x 32 x i16> @smulo_nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y) {252; CHECK-LABEL: smulo_nxv32i16:253; CHECK: // %bb.0:254; CHECK-NEXT: ptrue p0.h255; CHECK-NEXT: movprfx z24, z3256; CHECK-NEXT: mul z24.h, p0/m, z24.h, z7.h257; CHECK-NEXT: movprfx z25, z0258; CHECK-NEXT: mul z25.h, p0/m, z25.h, z4.h259; CHECK-NEXT: movprfx z26, z2260; CHECK-NEXT: mul z26.h, p0/m, z26.h, z6.h261; CHECK-NEXT: movprfx z27, z1262; CHECK-NEXT: mul z27.h, p0/m, z27.h, z5.h263; CHECK-NEXT: smulh z3.h, p0/m, z3.h, z7.h264; CHECK-NEXT: smulh z0.h, p0/m, z0.h, z4.h265; CHECK-NEXT: smulh z2.h, p0/m, z2.h, z6.h266; CHECK-NEXT: smulh z1.h, p0/m, z1.h, z5.h267; CHECK-NEXT: asr z4.h, z25.h, #15268; CHECK-NEXT: asr z5.h, z24.h, #15269; CHECK-NEXT: asr z6.h, z26.h, #15270; CHECK-NEXT: asr z7.h, z27.h, #15271; CHECK-NEXT: cmpne p1.h, p0/z, z0.h, z4.h272; CHECK-NEXT: cmpne p2.h, p0/z, z3.h, z5.h273; CHECK-NEXT: cmpne p3.h, p0/z, z2.h, z6.h274; CHECK-NEXT: cmpne p0.h, p0/z, z1.h, z7.h275; CHECK-NEXT: mov z25.h, p1/m, #0 // =0x0276; CHECK-NEXT: mov z26.h, p3/m, #0 // =0x0277; CHECK-NEXT: mov z24.h, p2/m, #0 // =0x0278; CHECK-NEXT: mov z27.h, p0/m, #0 // =0x0279; CHECK-NEXT: mov z0.d, z25.d280; CHECK-NEXT: mov z2.d, z26.d281; CHECK-NEXT: mov z3.d, z24.d282; CHECK-NEXT: mov z1.d, z27.d283; CHECK-NEXT: ret284 %a = call { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y)285 %b = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 0286 %c = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 1287 %d = select <vscale x 32 x i1> %c, <vscale x 32 x i16> zeroinitializer, <vscale x 32 x i16> %b288 ret <vscale x 32 x i16> %d289}290 291declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)292 293define <vscale x 2 x i32> @smulo_nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {294; CHECK-LABEL: smulo_nxv2i32:295; CHECK: // %bb.0:296; CHECK-NEXT: ptrue p0.d297; CHECK-NEXT: sxtw z1.d, p0/m, z1.d298; CHECK-NEXT: sxtw z0.d, p0/m, z0.d299; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d300; CHECK-NEXT: movprfx z1, z0301; CHECK-NEXT: sxtw z1.d, p0/m, z0.d302; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, z0.d303; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0304; CHECK-NEXT: ret305 %a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)306 %b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0307 %c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1308 %d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b309 ret <vscale x 2 x i32> %d310}311 312declare { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)313 314define <vscale x 4 x i32> @smulo_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {315; CHECK-LABEL: smulo_nxv4i32:316; CHECK: // %bb.0:317; CHECK-NEXT: ptrue p0.s318; CHECK-NEXT: movprfx z2, z0319; CHECK-NEXT: mul z2.s, p0/m, z2.s, z1.s320; CHECK-NEXT: smulh z0.s, p0/m, z0.s, z1.s321; CHECK-NEXT: asr z1.s, z2.s, #31322; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z1.s323; CHECK-NEXT: mov z2.s, p0/m, #0 // =0x0324; CHECK-NEXT: mov z0.d, z2.d325; CHECK-NEXT: ret326 %a = call { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)327 %b = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 0328 %c = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 1329 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> %b330 ret <vscale x 4 x i32> %d331}332 333declare { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)334 335define <vscale x 8 x i32> @smulo_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {336; CHECK-LABEL: smulo_nxv8i32:337; CHECK: // %bb.0:338; CHECK-NEXT: ptrue p0.s339; CHECK-NEXT: movprfx z4, z1340; CHECK-NEXT: mul z4.s, p0/m, z4.s, z3.s341; CHECK-NEXT: movprfx z5, z0342; CHECK-NEXT: mul z5.s, p0/m, z5.s, z2.s343; CHECK-NEXT: smulh z1.s, p0/m, z1.s, z3.s344; CHECK-NEXT: smulh z0.s, p0/m, z0.s, z2.s345; CHECK-NEXT: asr z2.s, z4.s, #31346; CHECK-NEXT: asr z3.s, z5.s, #31347; CHECK-NEXT: cmpne p1.s, p0/z, z1.s, z2.s348; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z3.s349; CHECK-NEXT: mov z5.s, p0/m, #0 // =0x0350; CHECK-NEXT: mov z4.s, p1/m, #0 // =0x0351; CHECK-NEXT: mov z0.d, z5.d352; CHECK-NEXT: mov z1.d, z4.d353; CHECK-NEXT: ret354 %a = call { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y)355 %b = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 0356 %c = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 1357 %d = select <vscale x 8 x i1> %c, <vscale x 8 x i32> zeroinitializer, <vscale x 8 x i32> %b358 ret <vscale x 8 x i32> %d359}360 361declare { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)362 363define <vscale x 16 x i32> @smulo_nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y) {364; CHECK-LABEL: smulo_nxv16i32:365; CHECK: // %bb.0:366; CHECK-NEXT: ptrue p0.s367; CHECK-NEXT: movprfx z24, z3368; CHECK-NEXT: mul z24.s, p0/m, z24.s, z7.s369; CHECK-NEXT: movprfx z25, z0370; CHECK-NEXT: mul z25.s, p0/m, z25.s, z4.s371; CHECK-NEXT: movprfx z26, z2372; CHECK-NEXT: mul z26.s, p0/m, z26.s, z6.s373; CHECK-NEXT: movprfx z27, z1374; CHECK-NEXT: mul z27.s, p0/m, z27.s, z5.s375; CHECK-NEXT: smulh z3.s, p0/m, z3.s, z7.s376; CHECK-NEXT: smulh z0.s, p0/m, z0.s, z4.s377; CHECK-NEXT: smulh z2.s, p0/m, z2.s, z6.s378; CHECK-NEXT: smulh z1.s, p0/m, z1.s, z5.s379; CHECK-NEXT: asr z4.s, z25.s, #31380; CHECK-NEXT: asr z5.s, z24.s, #31381; CHECK-NEXT: asr z6.s, z26.s, #31382; CHECK-NEXT: asr z7.s, z27.s, #31383; CHECK-NEXT: cmpne p1.s, p0/z, z0.s, z4.s384; CHECK-NEXT: cmpne p2.s, p0/z, z3.s, z5.s385; CHECK-NEXT: cmpne p3.s, p0/z, z2.s, z6.s386; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, z7.s387; CHECK-NEXT: mov z25.s, p1/m, #0 // =0x0388; CHECK-NEXT: mov z26.s, p3/m, #0 // =0x0389; CHECK-NEXT: mov z24.s, p2/m, #0 // =0x0390; CHECK-NEXT: mov z27.s, p0/m, #0 // =0x0391; CHECK-NEXT: mov z0.d, z25.d392; CHECK-NEXT: mov z2.d, z26.d393; CHECK-NEXT: mov z3.d, z24.d394; CHECK-NEXT: mov z1.d, z27.d395; CHECK-NEXT: ret396 %a = call { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y)397 %b = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 0398 %c = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 1399 %d = select <vscale x 16 x i1> %c, <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i32> %b400 ret <vscale x 16 x i32> %d401}402 403declare { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)404 405define <vscale x 2 x i64> @smulo_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {406; CHECK-LABEL: smulo_nxv2i64:407; CHECK: // %bb.0:408; CHECK-NEXT: ptrue p0.d409; CHECK-NEXT: movprfx z2, z0410; CHECK-NEXT: mul z2.d, p0/m, z2.d, z1.d411; CHECK-NEXT: smulh z0.d, p0/m, z0.d, z1.d412; CHECK-NEXT: asr z1.d, z2.d, #63413; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, z1.d414; CHECK-NEXT: mov z2.d, p0/m, #0 // =0x0415; CHECK-NEXT: mov z0.d, z2.d416; CHECK-NEXT: ret417 %a = call { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)418 %b = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 0419 %c = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 1420 %d = select <vscale x 2 x i1> %c, <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i64> %b421 ret <vscale x 2 x i64> %d422}423 424declare { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)425 426define <vscale x 4 x i64> @smulo_nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y) {427; CHECK-LABEL: smulo_nxv4i64:428; CHECK: // %bb.0:429; CHECK-NEXT: ptrue p0.d430; CHECK-NEXT: movprfx z4, z1431; CHECK-NEXT: mul z4.d, p0/m, z4.d, z3.d432; CHECK-NEXT: movprfx z5, z0433; CHECK-NEXT: mul z5.d, p0/m, z5.d, z2.d434; CHECK-NEXT: smulh z1.d, p0/m, z1.d, z3.d435; CHECK-NEXT: smulh z0.d, p0/m, z0.d, z2.d436; CHECK-NEXT: asr z2.d, z4.d, #63437; CHECK-NEXT: asr z3.d, z5.d, #63438; CHECK-NEXT: cmpne p1.d, p0/z, z1.d, z2.d439; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, z3.d440; CHECK-NEXT: mov z5.d, p0/m, #0 // =0x0441; CHECK-NEXT: mov z4.d, p1/m, #0 // =0x0442; CHECK-NEXT: mov z0.d, z5.d443; CHECK-NEXT: mov z1.d, z4.d444; CHECK-NEXT: ret445 %a = call { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y)446 %b = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 0447 %c = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 1448 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> zeroinitializer, <vscale x 4 x i64> %b449 ret <vscale x 4 x i64> %d450}451 452declare { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)453 454define <vscale x 8 x i64> @smulo_nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {455; CHECK-LABEL: smulo_nxv8i64:456; CHECK: // %bb.0:457; CHECK-NEXT: ptrue p0.d458; CHECK-NEXT: movprfx z24, z3459; CHECK-NEXT: mul z24.d, p0/m, z24.d, z7.d460; CHECK-NEXT: movprfx z25, z0461; CHECK-NEXT: mul z25.d, p0/m, z25.d, z4.d462; CHECK-NEXT: movprfx z26, z2463; CHECK-NEXT: mul z26.d, p0/m, z26.d, z6.d464; CHECK-NEXT: movprfx z27, z1465; CHECK-NEXT: mul z27.d, p0/m, z27.d, z5.d466; CHECK-NEXT: smulh z3.d, p0/m, z3.d, z7.d467; CHECK-NEXT: smulh z0.d, p0/m, z0.d, z4.d468; CHECK-NEXT: smulh z2.d, p0/m, z2.d, z6.d469; CHECK-NEXT: smulh z1.d, p0/m, z1.d, z5.d470; CHECK-NEXT: asr z4.d, z25.d, #63471; CHECK-NEXT: asr z5.d, z24.d, #63472; CHECK-NEXT: asr z6.d, z26.d, #63473; CHECK-NEXT: asr z7.d, z27.d, #63474; CHECK-NEXT: cmpne p1.d, p0/z, z0.d, z4.d475; CHECK-NEXT: cmpne p2.d, p0/z, z3.d, z5.d476; CHECK-NEXT: cmpne p3.d, p0/z, z2.d, z6.d477; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, z7.d478; CHECK-NEXT: mov z25.d, p1/m, #0 // =0x0479; CHECK-NEXT: mov z26.d, p3/m, #0 // =0x0480; CHECK-NEXT: mov z24.d, p2/m, #0 // =0x0481; CHECK-NEXT: mov z27.d, p0/m, #0 // =0x0482; CHECK-NEXT: mov z0.d, z25.d483; CHECK-NEXT: mov z2.d, z26.d484; CHECK-NEXT: mov z3.d, z24.d485; CHECK-NEXT: mov z1.d, z27.d486; CHECK-NEXT: ret487 %a = call { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y)488 %b = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 0489 %c = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 1490 %d = select <vscale x 8 x i1> %c, <vscale x 8 x i64> zeroinitializer, <vscale x 8 x i64> %b491 ret <vscale x 8 x i64> %d492}493