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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; Ensure that a no-op 'and' get removed with vector splat of 1 or ptrue with proper constant7 8define <vscale x 16 x i1> @fold_away_ptrue_and_ptrue() #0 {9; CHECK-LABEL: fold_away_ptrue_and_ptrue:10; CHECK: // %bb.0:11; CHECK-NEXT: ptrue p0.s12; CHECK-NEXT: ret13 %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)14 %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)15 %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)16 %and = and <vscale x 16 x i1> %3, %217 ret <vscale x 16 x i1> %and18}19 20define <vscale x 16 x i1> @fold_away_ptrue_and_splat_predicate() #0 {21; CHECK-LABEL: fold_away_ptrue_and_splat_predicate:22; CHECK: // %bb.0:23; CHECK-NEXT: ptrue p0.s24; CHECK-NEXT: ret25 %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> splat(i1 true))26 %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)27 %and = and <vscale x 16 x i1> %1, %228 ret <vscale x 16 x i1> %and29}30 31; Ensure that one AND operation remain for inactive lanes zeroing with 2 x i1 type (llvm.aarch64.sve.convert.to.svbool.nxv2i1).32define <vscale x 16 x i1> @fold_away_ptrue_and_convert_to() #0 {33; CHECK-LABEL: fold_away_ptrue_and_convert_to:34; CHECK: // %bb.0:35; CHECK-NEXT: ptrue p0.s36; CHECK-NEXT: ptrue p1.d37; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b38; CHECK-NEXT: ret39 %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)40 %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)41 %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)42 %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %3)43 %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)44 %and = and <vscale x 16 x i1> %5, %245 ret <vscale x 16 x i1> %and46}47 48define <vscale x 16 x i1> @fold_away_two_similar() #0 {49; CHECK-LABEL: fold_away_two_similar:50; CHECK: // %bb.0:51; CHECK-NEXT: ptrue p0.b52; CHECK-NEXT: ret53 %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)54 %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)55 %and = and <vscale x 16 x i1> %1, %256 ret <vscale x 16 x i1> %and57}58 59declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg)60 61declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)62 63declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)64 65declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)66 67declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>)68 69 70attributes #0 = { "target-features"="+sve" }71