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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4; UNPREDICATED5 6define <vscale x 4 x i16> @load_promote_4i16(ptr %a) {7; CHECK-LABEL: load_promote_4i16:8; CHECK: // %bb.0:9; CHECK-NEXT: ptrue p0.s10; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]11; CHECK-NEXT: ret12 %load = load <vscale x 4 x i16>, ptr %a13 ret <vscale x 4 x i16> %load14}15 16define <vscale x 16 x i16> @load_split_i16(ptr %a) {17; CHECK-LABEL: load_split_i16:18; CHECK: // %bb.0:19; CHECK-NEXT: ldr z0, [x0]20; CHECK-NEXT: ldr z1, [x0, #1, mul vl]21; CHECK-NEXT: ret22 %load = load <vscale x 16 x i16>, ptr %a23 ret <vscale x 16 x i16> %load24}25 26define <vscale x 24 x i16> @load_split_24i16(ptr %a) {27; CHECK-LABEL: load_split_24i16:28; CHECK: // %bb.0:29; CHECK-NEXT: ldr z0, [x0]30; CHECK-NEXT: ldr z1, [x0, #1, mul vl]31; CHECK-NEXT: ldr z2, [x0, #2, mul vl]32; CHECK-NEXT: ret33 %load = load <vscale x 24 x i16>, ptr %a34 ret <vscale x 24 x i16> %load35}36 37define <vscale x 32 x i16> @load_split_32i16(ptr %a) {38; CHECK-LABEL: load_split_32i16:39; CHECK: // %bb.0:40; CHECK-NEXT: ldr z0, [x0]41; CHECK-NEXT: ldr z1, [x0, #1, mul vl]42; CHECK-NEXT: ldr z2, [x0, #2, mul vl]43; CHECK-NEXT: ldr z3, [x0, #3, mul vl]44; CHECK-NEXT: ret45 %load = load <vscale x 32 x i16>, ptr %a46 ret <vscale x 32 x i16> %load47}48 49define <vscale x 16 x i64> @load_split_16i64(ptr %a) {50; CHECK-LABEL: load_split_16i64:51; CHECK: // %bb.0:52; CHECK-NEXT: ldr z0, [x0]53; CHECK-NEXT: ldr z1, [x0, #1, mul vl]54; CHECK-NEXT: ldr z2, [x0, #2, mul vl]55; CHECK-NEXT: ldr z3, [x0, #3, mul vl]56; CHECK-NEXT: ldr z4, [x0, #4, mul vl]57; CHECK-NEXT: ldr z5, [x0, #5, mul vl]58; CHECK-NEXT: ldr z6, [x0, #6, mul vl]59; CHECK-NEXT: ldr z7, [x0, #7, mul vl]60; CHECK-NEXT: ret61 %load = load <vscale x 16 x i64>, ptr %a62 ret <vscale x 16 x i64> %load63}64 65; MASKED66 67define <vscale x 2 x i32> @masked_load_promote_2i32(ptr %a, <vscale x 2 x i1> %pg) {68; CHECK-LABEL: masked_load_promote_2i32:69; CHECK: // %bb.0:70; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]71; CHECK-NEXT: ret72 %load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(ptr %a, i32 1, <vscale x 2 x i1> %pg, <vscale x 2 x i32> poison)73 ret <vscale x 2 x i32> %load74}75 76define <vscale x 32 x i8> @masked_load_split_32i8(ptr %a, <vscale x 32 x i1> %pg) {77; CHECK-LABEL: masked_load_split_32i8:78; CHECK: // %bb.0:79; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]80; CHECK-NEXT: ld1b { z1.b }, p1/z, [x0, #1, mul vl]81; CHECK-NEXT: ret82 %load = call <vscale x 32 x i8> @llvm.masked.load.nxv32i8(ptr %a, i32 1, <vscale x 32 x i1> %pg, <vscale x 32 x i8> poison)83 ret <vscale x 32 x i8> %load84}85 86define <vscale x 32 x i16> @masked_load_split_32i16(ptr %a, <vscale x 32 x i1> %pg) {87; CHECK-LABEL: masked_load_split_32i16:88; CHECK: // %bb.0:89; CHECK-NEXT: punpklo p2.h, p0.b90; CHECK-NEXT: punpkhi p0.h, p0.b91; CHECK-NEXT: punpklo p3.h, p1.b92; CHECK-NEXT: ld1h { z0.h }, p2/z, [x0]93; CHECK-NEXT: punpkhi p1.h, p1.b94; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0, #1, mul vl]95; CHECK-NEXT: ld1h { z2.h }, p3/z, [x0, #2, mul vl]96; CHECK-NEXT: ld1h { z3.h }, p1/z, [x0, #3, mul vl]97; CHECK-NEXT: ret98 %load = call <vscale x 32 x i16> @llvm.masked.load.nxv32i16(ptr %a, i32 1, <vscale x 32 x i1> %pg, <vscale x 32 x i16> poison)99 ret <vscale x 32 x i16> %load100}101 102define <vscale x 8 x i32> @masked_load_split_8i32(ptr %a, <vscale x 8 x i1> %pg) {103; CHECK-LABEL: masked_load_split_8i32:104; CHECK: // %bb.0:105; CHECK-NEXT: punpklo p1.h, p0.b106; CHECK-NEXT: punpkhi p0.h, p0.b107; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0]108; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0, #1, mul vl]109; CHECK-NEXT: ret110 %load = call <vscale x 8 x i32> @llvm.masked.load.nxv8i32(ptr %a, i32 1, <vscale x 8 x i1> %pg, <vscale x 8 x i32> poison)111 ret <vscale x 8 x i32> %load112}113 114define <vscale x 8 x i64> @masked_load_split_8i64(ptr %a, <vscale x 8 x i1> %pg) {115; CHECK-LABEL: masked_load_split_8i64:116; CHECK: // %bb.0:117; CHECK-NEXT: punpklo p1.h, p0.b118; CHECK-NEXT: punpkhi p0.h, p0.b119; CHECK-NEXT: punpklo p2.h, p1.b120; CHECK-NEXT: punpkhi p1.h, p1.b121; CHECK-NEXT: punpklo p3.h, p0.b122; CHECK-NEXT: ld1d { z0.d }, p2/z, [x0]123; CHECK-NEXT: punpkhi p0.h, p0.b124; CHECK-NEXT: ld1d { z1.d }, p1/z, [x0, #1, mul vl]125; CHECK-NEXT: ld1d { z2.d }, p3/z, [x0, #2, mul vl]126; CHECK-NEXT: ld1d { z3.d }, p0/z, [x0, #3, mul vl]127; CHECK-NEXT: ret128 %load = call <vscale x 8 x i64> @llvm.masked.load.nxv8i64(ptr %a, i32 1, <vscale x 8 x i1> %pg, <vscale x 8 x i64> poison)129 ret <vscale x 8 x i64> %load130}131 132declare <vscale x 32 x i8> @llvm.masked.load.nxv32i8(ptr, i32, <vscale x 32 x i1>, <vscale x 32 x i8>)133 134declare <vscale x 32 x i16> @llvm.masked.load.nxv32i16(ptr, i32, <vscale x 32 x i1>, <vscale x 32 x i16>)135 136declare <vscale x 2 x i32> @llvm.masked.load.nxv2i32(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i32>)137declare <vscale x 8 x i32> @llvm.masked.load.nxv8i32(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x i32>)138 139declare <vscale x 8 x i64> @llvm.masked.load.nxv8i64(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x i64>)140