129 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4; UNPREDICATED5 6define void @store_promote_4i8(<vscale x 4 x i8> %data, ptr %a) {7; CHECK-LABEL: store_promote_4i8:8; CHECK: // %bb.0:9; CHECK-NEXT: ptrue p0.s10; CHECK-NEXT: st1b { z0.s }, p0, [x0]11; CHECK-NEXT: ret12 store <vscale x 4 x i8> %data, ptr %a13 ret void14}15 16define void @store_split_i16(<vscale x 16 x i16> %data, ptr %a) {17; CHECK-LABEL: store_split_i16:18; CHECK: // %bb.0:19; CHECK-NEXT: str z1, [x0, #1, mul vl]20; CHECK-NEXT: str z0, [x0]21; CHECK-NEXT: ret22 store <vscale x 16 x i16> %data, ptr %a23 ret void24}25 26define void @store_split_16i32(<vscale x 16 x i32> %data, ptr %a) {27; CHECK-LABEL: store_split_16i32:28; CHECK: // %bb.0:29; CHECK-NEXT: str z3, [x0, #3, mul vl]30; CHECK-NEXT: str z2, [x0, #2, mul vl]31; CHECK-NEXT: str z1, [x0, #1, mul vl]32; CHECK-NEXT: str z0, [x0]33; CHECK-NEXT: ret34 store <vscale x 16 x i32> %data, ptr %a35 ret void36}37 38define void @store_split_16i64(<vscale x 16 x i64> %data, ptr %a) {39; CHECK-LABEL: store_split_16i64:40; CHECK: // %bb.0:41; CHECK-NEXT: str z7, [x0, #7, mul vl]42; CHECK-NEXT: str z6, [x0, #6, mul vl]43; CHECK-NEXT: str z5, [x0, #5, mul vl]44; CHECK-NEXT: str z4, [x0, #4, mul vl]45; CHECK-NEXT: str z3, [x0, #3, mul vl]46; CHECK-NEXT: str z2, [x0, #2, mul vl]47; CHECK-NEXT: str z1, [x0, #1, mul vl]48; CHECK-NEXT: str z0, [x0]49; CHECK-NEXT: ret50 store <vscale x 16 x i64> %data, ptr %a51 ret void52}53 54; MASKED55 56define void @masked_store_promote_2i8(<vscale x 2 x i8> %data, ptr %a, <vscale x 2 x i1> %pg) {57; CHECK-LABEL: masked_store_promote_2i8:58; CHECK: // %bb.0:59; CHECK-NEXT: st1b { z0.d }, p0, [x0]60; CHECK-NEXT: ret61 call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %data, ptr %a, i32 1, <vscale x 2 x i1> %pg)62 ret void63}64 65define void @masked_store_split_32i8(<vscale x 32 x i8> %data, ptr %a, <vscale x 32 x i1> %pg) {66; CHECK-LABEL: masked_store_split_32i8:67; CHECK: // %bb.0:68; CHECK-NEXT: st1b { z1.b }, p1, [x0, #1, mul vl]69; CHECK-NEXT: st1b { z0.b }, p0, [x0]70; CHECK-NEXT: ret71 call void @llvm.masked.store.nxv32i8(<vscale x 32 x i8> %data, ptr %a, i32 1, <vscale x 32 x i1> %pg)72 ret void73}74 75define void @masked_store_split_32i16(<vscale x 32 x i16> %data, ptr %a, <vscale x 32 x i1> %pg) {76; CHECK-LABEL: masked_store_split_32i16:77; CHECK: // %bb.0:78; CHECK-NEXT: punpkhi p2.h, p1.b79; CHECK-NEXT: punpklo p1.h, p1.b80; CHECK-NEXT: punpkhi p3.h, p0.b81; CHECK-NEXT: st1h { z3.h }, p2, [x0, #3, mul vl]82; CHECK-NEXT: punpklo p0.h, p0.b83; CHECK-NEXT: st1h { z2.h }, p1, [x0, #2, mul vl]84; CHECK-NEXT: st1h { z1.h }, p3, [x0, #1, mul vl]85; CHECK-NEXT: st1h { z0.h }, p0, [x0]86; CHECK-NEXT: ret87 call void @llvm.masked.store.nxv32i16(<vscale x 32 x i16> %data, ptr %a, i32 1, <vscale x 32 x i1> %pg)88 ret void89}90 91define void @masked_store_split_8i32(<vscale x 8 x i32> %data, ptr %a, <vscale x 8 x i1> %pg) {92; CHECK-LABEL: masked_store_split_8i32:93; CHECK: // %bb.0:94; CHECK-NEXT: punpkhi p1.h, p0.b95; CHECK-NEXT: punpklo p0.h, p0.b96; CHECK-NEXT: st1w { z1.s }, p1, [x0, #1, mul vl]97; CHECK-NEXT: st1w { z0.s }, p0, [x0]98; CHECK-NEXT: ret99 call void @llvm.masked.store.nxv8i32(<vscale x 8 x i32> %data, ptr %a, i32 1, <vscale x 8 x i1> %pg)100 ret void101}102 103define void @masked_store_split_8i64(<vscale x 8 x i64> %data, ptr %a, <vscale x 8 x i1> %pg) {104; CHECK-LABEL: masked_store_split_8i64:105; CHECK: // %bb.0:106; CHECK-NEXT: punpkhi p1.h, p0.b107; CHECK-NEXT: punpklo p0.h, p0.b108; CHECK-NEXT: punpkhi p2.h, p1.b109; CHECK-NEXT: punpklo p1.h, p1.b110; CHECK-NEXT: st1d { z3.d }, p2, [x0, #3, mul vl]111; CHECK-NEXT: punpkhi p2.h, p0.b112; CHECK-NEXT: punpklo p0.h, p0.b113; CHECK-NEXT: st1d { z2.d }, p1, [x0, #2, mul vl]114; CHECK-NEXT: st1d { z1.d }, p2, [x0, #1, mul vl]115; CHECK-NEXT: st1d { z0.d }, p0, [x0]116; CHECK-NEXT: ret117 call void @llvm.masked.store.nxv8i64(<vscale x 8 x i64> %data, ptr %a, i32 1, <vscale x 8 x i1> %pg)118 ret void119}120 121declare void @llvm.masked.store.nxv2i8(<vscale x 2 x i8>, ptr, i32, <vscale x 2 x i1>)122declare void @llvm.masked.store.nxv32i8(<vscale x 32 x i8>, ptr, i32, <vscale x 32 x i1>)123 124declare void @llvm.masked.store.nxv32i16(<vscale x 32 x i16>, ptr, i32, <vscale x 32 x i1>)125 126declare void @llvm.masked.store.nxv8i32(<vscale x 8 x i32>, ptr, i32, <vscale x 8 x i1>)127 128declare void @llvm.masked.store.nxv8i64(<vscale x 8 x i64>, ptr, i32, <vscale x 8 x i1>)129