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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s3 4define <vscale x 16 x i8> @trunc_i16toi8(<vscale x 16 x i16> %in) {5; CHECK-LABEL: trunc_i16toi8:6; CHECK: // %bb.0:7; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b8; CHECK-NEXT: ret9 %out = trunc <vscale x 16 x i16> %in to <vscale x 16 x i8>10 ret <vscale x 16 x i8> %out11}12 13define <vscale x 16 x i8> @trunc_i32toi8(<vscale x 16 x i32> %in) {14; CHECK-LABEL: trunc_i32toi8:15; CHECK: // %bb.0:16; CHECK-NEXT: uzp1 z2.h, z2.h, z3.h17; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h18; CHECK-NEXT: uzp1 z0.b, z0.b, z2.b19; CHECK-NEXT: ret20 %out = trunc <vscale x 16 x i32> %in to <vscale x 16 x i8>21 ret <vscale x 16 x i8> %out22}23 24define <vscale x 8 x i16> @trunc_i32toi16(<vscale x 8 x i32> %in) {25; CHECK-LABEL: trunc_i32toi16:26; CHECK: // %bb.0:27; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h28; CHECK-NEXT: ret29 %out = trunc <vscale x 8 x i32> %in to <vscale x 8 x i16>30 ret <vscale x 8 x i16> %out31}32 33define <vscale x 4 x i32> @trunc_i64toi32(<vscale x 4 x i64> %in) {34; CHECK-LABEL: trunc_i64toi32:35; CHECK: // %bb.0:36; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s37; CHECK-NEXT: ret38 %out = trunc <vscale x 4 x i64> %in to <vscale x 4 x i32>39 ret <vscale x 4 x i32> %out40}41 42define <vscale x 8 x i16> @trunc_i64toi16(<vscale x 8 x i64> %in) {43; CHECK-LABEL: trunc_i64toi16:44; CHECK: // %bb.0:45; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s46; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s47; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h48; CHECK-NEXT: ret49 %out = trunc <vscale x 8 x i64> %in to <vscale x 8 x i16>50 ret <vscale x 8 x i16> %out51}52 53define <vscale x 16 x i8> @trunc_i64toi8(<vscale x 16 x i64> %in) {54; CHECK-LABEL: trunc_i64toi8:55; CHECK: // %bb.0:56; CHECK-NEXT: uzp1 z6.s, z6.s, z7.s57; CHECK-NEXT: uzp1 z4.s, z4.s, z5.s58; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s59; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s60; CHECK-NEXT: uzp1 z1.h, z4.h, z6.h61; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h62; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b63; CHECK-NEXT: ret64 %out = trunc <vscale x 16 x i64> %in to <vscale x 16 x i8>65 ret <vscale x 16 x i8> %out66}67