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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s3; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s4; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE5 6target triple = "aarch64"7 8;9; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we10; don't currently expect the code below to lower to BSL/BIT/BIF. Once11; this is implemented, this test will be fleshed out.12;13 14define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %right_ptr) {15; CHECK-LABEL: fixed_bitselect_v8i32:16; CHECK: // %bb.0:17; CHECK-NEXT: ldp q1, q0, [x0]18; CHECK-NEXT: ldp q5, q4, [x1]19; CHECK-NEXT: ldp q6, q7, [x2]20; CHECK-NEXT: mov z2.d, z0.d21; CHECK-NEXT: mov z3.d, z1.d22; CHECK-NEXT: sub z1.s, z1.s, #1 // =0x123; CHECK-NEXT: sub z0.s, z0.s, #1 // =0x124; CHECK-NEXT: subr z2.s, z2.s, #0 // =0x025; CHECK-NEXT: subr z3.s, z3.s, #0 // =0x026; CHECK-NEXT: and z2.d, z2.d, z4.d27; CHECK-NEXT: and z3.d, z3.d, z5.d28; CHECK-NEXT: and z4.d, z0.d, z7.d29; CHECK-NEXT: and z0.d, z1.d, z6.d30; CHECK-NEXT: orr z1.d, z4.d, z2.d31; CHECK-NEXT: orr z0.d, z0.d, z3.d32; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z133; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z034; CHECK-NEXT: ret35;36; NONEON-NOSVE-LABEL: fixed_bitselect_v8i32:37; NONEON-NOSVE: // %bb.0:38; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]39; NONEON-NOSVE-NEXT: ldp q2, q3, [x1]40; NONEON-NOSVE-NEXT: ldp q4, q5, [x2]41; NONEON-NOSVE-NEXT: stp q0, q2, [sp, #-128]!42; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 12843; NONEON-NOSVE-NEXT: stp q1, q3, [sp, #48]44; NONEON-NOSVE-NEXT: ldp w13, w11, [sp, #48]45; NONEON-NOSVE-NEXT: ldp w14, w4, [sp, #64]46; NONEON-NOSVE-NEXT: ldp w17, w16, [sp]47; NONEON-NOSVE-NEXT: ldp w9, w8, [sp, #56]48; NONEON-NOSVE-NEXT: neg w15, w1149; NONEON-NOSVE-NEXT: neg w3, w1350; NONEON-NOSVE-NEXT: str q4, [sp, #32]51; NONEON-NOSVE-NEXT: and w14, w3, w1452; NONEON-NOSVE-NEXT: and w15, w15, w453; NONEON-NOSVE-NEXT: neg w1, w1754; NONEON-NOSVE-NEXT: ldp w5, w3, [sp, #72]55; NONEON-NOSVE-NEXT: ldp w6, w4, [sp, #16]56; NONEON-NOSVE-NEXT: ldp w12, w10, [sp, #8]57; NONEON-NOSVE-NEXT: neg w2, w958; NONEON-NOSVE-NEXT: neg w7, w859; NONEON-NOSVE-NEXT: sub w17, w17, #160; NONEON-NOSVE-NEXT: and w2, w2, w561; NONEON-NOSVE-NEXT: and w1, w1, w662; NONEON-NOSVE-NEXT: and w3, w7, w363; NONEON-NOSVE-NEXT: ldp w5, w6, [sp, #24]64; NONEON-NOSVE-NEXT: neg w0, w1265; NONEON-NOSVE-NEXT: neg w7, w1666; NONEON-NOSVE-NEXT: neg w18, w1067; NONEON-NOSVE-NEXT: and w4, w7, w468; NONEON-NOSVE-NEXT: sub w10, w10, #169; NONEON-NOSVE-NEXT: sub w12, w12, #170; NONEON-NOSVE-NEXT: and w0, w0, w571; NONEON-NOSVE-NEXT: and w18, w18, w672; NONEON-NOSVE-NEXT: str q5, [sp, #80]73; NONEON-NOSVE-NEXT: ldp w7, w5, [sp, #32]74; NONEON-NOSVE-NEXT: sub w16, w16, #175; NONEON-NOSVE-NEXT: sub w8, w8, #176; NONEON-NOSVE-NEXT: sub w9, w9, #177; NONEON-NOSVE-NEXT: and w17, w17, w778; NONEON-NOSVE-NEXT: and w16, w16, w579; NONEON-NOSVE-NEXT: ldp w6, w7, [sp, #40]80; NONEON-NOSVE-NEXT: and w12, w12, w681; NONEON-NOSVE-NEXT: and w10, w10, w782; NONEON-NOSVE-NEXT: orr w10, w10, w1883; NONEON-NOSVE-NEXT: orr w12, w12, w084; NONEON-NOSVE-NEXT: ldp w18, w0, [sp, #88]85; NONEON-NOSVE-NEXT: ldp w5, w6, [sp, #80]86; NONEON-NOSVE-NEXT: stp w12, w10, [sp, #104]87; NONEON-NOSVE-NEXT: sub w10, w11, #188; NONEON-NOSVE-NEXT: sub w11, w13, #189; NONEON-NOSVE-NEXT: and w8, w8, w090; NONEON-NOSVE-NEXT: and w9, w9, w1891; NONEON-NOSVE-NEXT: orr w12, w16, w492; NONEON-NOSVE-NEXT: orr w8, w8, w393; NONEON-NOSVE-NEXT: orr w9, w9, w294; NONEON-NOSVE-NEXT: and w10, w10, w695; NONEON-NOSVE-NEXT: stp w9, w8, [sp, #120]96; NONEON-NOSVE-NEXT: and w8, w11, w597; NONEON-NOSVE-NEXT: orr w13, w17, w198; NONEON-NOSVE-NEXT: orr w9, w10, w1599; NONEON-NOSVE-NEXT: orr w8, w8, w14100; NONEON-NOSVE-NEXT: stp w13, w12, [sp, #96]101; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #112]102; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]103; NONEON-NOSVE-NEXT: add sp, sp, #128104; NONEON-NOSVE-NEXT: ret105 %pre_cond = load <8 x i32>, ptr %pre_cond_ptr106 %left = load <8 x i32>, ptr %left_ptr107 %right = load <8 x i32>, ptr %right_ptr108 109 %neg_cond = sub <8 x i32> zeroinitializer, %pre_cond110 %min_cond = add <8 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>111 %left_bits_0 = and <8 x i32> %neg_cond, %left112 %right_bits_0 = and <8 x i32> %min_cond, %right113 %bsl0000 = or <8 x i32> %right_bits_0, %left_bits_0114 ret <8 x i32> %bsl0000115}116 117