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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s3; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s4; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE5 6target triple = "aarch64-unknown-linux-gnu"7 8; Ensure we don't crash when trying to combine fp<->int conversions9define void @fp_convert_combine_crash(ptr %a, ptr %b) {10; CHECK-LABEL: fp_convert_combine_crash:11; CHECK: // %bb.0:12; CHECK-NEXT: fmov z0.s, #8.0000000013; CHECK-NEXT: ldp q1, q2, [x0]14; CHECK-NEXT: ptrue p0.s, vl415; CHECK-NEXT: fmul z1.s, p0/m, z1.s, z0.s16; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z2.s17; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s18; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s19; CHECK-NEXT: stp q1, q0, [x1]20; CHECK-NEXT: ret21;22; NONEON-NOSVE-LABEL: fp_convert_combine_crash:23; NONEON-NOSVE: // %bb.0:24; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]25; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-64]!26; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 6427; NONEON-NOSVE-NEXT: ldp s1, s0, [sp, #24]28; NONEON-NOSVE-NEXT: fcvtzs w8, s0, #329; NONEON-NOSVE-NEXT: ldp s2, s0, [sp, #16]30; NONEON-NOSVE-NEXT: fcvtzs w9, s1, #331; NONEON-NOSVE-NEXT: fcvtzs w10, s0, #332; NONEON-NOSVE-NEXT: fcvtzs w11, s2, #333; NONEON-NOSVE-NEXT: ldp s1, s0, [sp, #8]34; NONEON-NOSVE-NEXT: ldp s2, s3, [sp]35; NONEON-NOSVE-NEXT: stp w9, w8, [sp, #56]36; NONEON-NOSVE-NEXT: fcvtzs w12, s0, #337; NONEON-NOSVE-NEXT: fcvtzs w8, s1, #338; NONEON-NOSVE-NEXT: stp w11, w10, [sp, #48]39; NONEON-NOSVE-NEXT: fcvtzs w9, s3, #340; NONEON-NOSVE-NEXT: fcvtzs w10, s2, #341; NONEON-NOSVE-NEXT: stp w8, w12, [sp, #40]42; NONEON-NOSVE-NEXT: stp w10, w9, [sp, #32]43; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]44; NONEON-NOSVE-NEXT: stp q0, q1, [x1]45; NONEON-NOSVE-NEXT: add sp, sp, #6446; NONEON-NOSVE-NEXT: ret47 %f = load <8 x float>, ptr %a48 %mul.i = fmul <8 x float> %f, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00,49 float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>50 %vcvt.i = fptosi <8 x float> %mul.i to <8 x i32>51 store <8 x i32> %vcvt.i, ptr %b52 ret void53}54