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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s3; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s4; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE5 6target triple = "aarch64-unknown-linux-gnu"7 8;9; FCVT H -> S; Without load instr10;11 12define void @fcvt_v2f16_to_v2f32(<2 x half> %a, ptr %b) {13; CHECK-LABEL: fcvt_v2f16_to_v2f32:14; CHECK: // %bb.0:15; CHECK-NEXT: // kill: def $d0 killed $d0 def $z016; CHECK-NEXT: ptrue p0.s, vl417; CHECK-NEXT: uunpklo z0.s, z0.h18; CHECK-NEXT: fcvt z0.s, p0/m, z0.h19; CHECK-NEXT: str d0, [x0]20; CHECK-NEXT: ret21;22; NONEON-NOSVE-LABEL: fcvt_v2f16_to_v2f32:23; NONEON-NOSVE: // %bb.0:24; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!25; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 1626; NONEON-NOSVE-NEXT: ldr h0, [sp, #2]27; NONEON-NOSVE-NEXT: fcvt s1, h028; NONEON-NOSVE-NEXT: ldr h0, [sp]29; NONEON-NOSVE-NEXT: fcvt s0, h030; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #8]31; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]32; NONEON-NOSVE-NEXT: str d0, [x0]33; NONEON-NOSVE-NEXT: add sp, sp, #1634; NONEON-NOSVE-NEXT: ret35 %res = fpext <2 x half> %a to <2 x float>36 store <2 x float> %res, ptr %b37 ret void38}39 40define void @fcvt_v4f16_to_v4f32(<4 x half> %a, ptr %b) {41; CHECK-LABEL: fcvt_v4f16_to_v4f32:42; CHECK: // %bb.0:43; CHECK-NEXT: // kill: def $d0 killed $d0 def $z044; CHECK-NEXT: ptrue p0.s, vl445; CHECK-NEXT: uunpklo z0.s, z0.h46; CHECK-NEXT: fcvt z0.s, p0/m, z0.h47; CHECK-NEXT: str q0, [x0]48; CHECK-NEXT: ret49;50; NONEON-NOSVE-LABEL: fcvt_v4f16_to_v4f32:51; NONEON-NOSVE: // %bb.0:52; NONEON-NOSVE-NEXT: sub sp, sp, #3253; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 3254; NONEON-NOSVE-NEXT: str d0, [sp, #8]55; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]56; NONEON-NOSVE-NEXT: fcvt s1, h057; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]58; NONEON-NOSVE-NEXT: fcvt s0, h059; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #24]60; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]61; NONEON-NOSVE-NEXT: fcvt s1, h062; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]63; NONEON-NOSVE-NEXT: fcvt s0, h064; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #16]65; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]66; NONEON-NOSVE-NEXT: str q0, [x0]67; NONEON-NOSVE-NEXT: add sp, sp, #3268; NONEON-NOSVE-NEXT: ret69 %res = fpext <4 x half> %a to <4 x float>70 store <4 x float> %res, ptr %b71 ret void72}73 74define void @fcvt_v8f16_to_v8f32(<8 x half> %a, ptr %b) {75; CHECK-LABEL: fcvt_v8f16_to_v8f32:76; CHECK: // %bb.0:77; CHECK-NEXT: // kill: def $q0 killed $q0 def $z078; CHECK-NEXT: movprfx z1, z079; CHECK-NEXT: ext z1.b, z1.b, z0.b, #880; CHECK-NEXT: ptrue p0.s, vl481; CHECK-NEXT: uunpklo z0.s, z0.h82; CHECK-NEXT: uunpklo z1.s, z1.h83; CHECK-NEXT: fcvt z0.s, p0/m, z0.h84; CHECK-NEXT: fcvt z1.s, p0/m, z1.h85; CHECK-NEXT: stp q0, q1, [x0]86; CHECK-NEXT: ret87;88; NONEON-NOSVE-LABEL: fcvt_v8f16_to_v8f32:89; NONEON-NOSVE: // %bb.0:90; NONEON-NOSVE-NEXT: str q0, [sp, #-64]!91; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 6492; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]93; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]94; NONEON-NOSVE-NEXT: ldr h0, [sp, #30]95; NONEON-NOSVE-NEXT: fcvt s1, h096; NONEON-NOSVE-NEXT: ldr h0, [sp, #28]97; NONEON-NOSVE-NEXT: fcvt s0, h098; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #56]99; NONEON-NOSVE-NEXT: ldr h0, [sp, #26]100; NONEON-NOSVE-NEXT: fcvt s1, h0101; NONEON-NOSVE-NEXT: ldr h0, [sp, #24]102; NONEON-NOSVE-NEXT: fcvt s0, h0103; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #48]104; NONEON-NOSVE-NEXT: ldr h0, [sp, #22]105; NONEON-NOSVE-NEXT: fcvt s1, h0106; NONEON-NOSVE-NEXT: ldr h0, [sp, #20]107; NONEON-NOSVE-NEXT: fcvt s0, h0108; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #40]109; NONEON-NOSVE-NEXT: ldr h0, [sp, #18]110; NONEON-NOSVE-NEXT: fcvt s1, h0111; NONEON-NOSVE-NEXT: ldr h0, [sp, #16]112; NONEON-NOSVE-NEXT: fcvt s0, h0113; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #32]114; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]115; NONEON-NOSVE-NEXT: stp q1, q0, [x0]116; NONEON-NOSVE-NEXT: add sp, sp, #64117; NONEON-NOSVE-NEXT: ret118 %res = fpext <8 x half> %a to <8 x float>119 store <8 x float> %res, ptr %b120 ret void121}122 123define void @fcvt_v16f16_to_v16f32(<16 x half> %a, ptr %b) {124; CHECK-LABEL: fcvt_v16f16_to_v16f32:125; CHECK: // %bb.0:126; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1127; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0128; CHECK-NEXT: movprfx z2, z1129; CHECK-NEXT: ext z2.b, z2.b, z1.b, #8130; CHECK-NEXT: movprfx z3, z0131; CHECK-NEXT: ext z3.b, z3.b, z0.b, #8132; CHECK-NEXT: ptrue p0.s, vl4133; CHECK-NEXT: uunpklo z1.s, z1.h134; CHECK-NEXT: uunpklo z0.s, z0.h135; CHECK-NEXT: uunpklo z2.s, z2.h136; CHECK-NEXT: uunpklo z3.s, z3.h137; CHECK-NEXT: fcvt z1.s, p0/m, z1.h138; CHECK-NEXT: fcvt z0.s, p0/m, z0.h139; CHECK-NEXT: fcvt z2.s, p0/m, z2.h140; CHECK-NEXT: fcvt z3.s, p0/m, z3.h141; CHECK-NEXT: stp q0, q3, [x0]142; CHECK-NEXT: stp q1, q2, [x0, #32]143; CHECK-NEXT: ret144;145; NONEON-NOSVE-LABEL: fcvt_v16f16_to_v16f32:146; NONEON-NOSVE: // %bb.0:147; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-128]!148; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128149; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]150; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]151; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16]152; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]153; NONEON-NOSVE-NEXT: ldr h0, [sp, #46]154; NONEON-NOSVE-NEXT: fcvt s1, h0155; NONEON-NOSVE-NEXT: ldr h0, [sp, #44]156; NONEON-NOSVE-NEXT: fcvt s0, h0157; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #88]158; NONEON-NOSVE-NEXT: ldr h0, [sp, #42]159; NONEON-NOSVE-NEXT: fcvt s1, h0160; NONEON-NOSVE-NEXT: ldr h0, [sp, #40]161; NONEON-NOSVE-NEXT: fcvt s0, h0162; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #80]163; NONEON-NOSVE-NEXT: ldr h0, [sp, #38]164; NONEON-NOSVE-NEXT: fcvt s1, h0165; NONEON-NOSVE-NEXT: ldr h0, [sp, #36]166; NONEON-NOSVE-NEXT: fcvt s0, h0167; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #72]168; NONEON-NOSVE-NEXT: ldr h0, [sp, #34]169; NONEON-NOSVE-NEXT: fcvt s1, h0170; NONEON-NOSVE-NEXT: ldr h0, [sp, #32]171; NONEON-NOSVE-NEXT: fcvt s0, h0172; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #64]173; NONEON-NOSVE-NEXT: ldr h0, [sp, #62]174; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64]175; NONEON-NOSVE-NEXT: fcvt s1, h0176; NONEON-NOSVE-NEXT: ldr h0, [sp, #60]177; NONEON-NOSVE-NEXT: fcvt s0, h0178; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #120]179; NONEON-NOSVE-NEXT: ldr h0, [sp, #58]180; NONEON-NOSVE-NEXT: fcvt s1, h0181; NONEON-NOSVE-NEXT: ldr h0, [sp, #56]182; NONEON-NOSVE-NEXT: fcvt s0, h0183; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #112]184; NONEON-NOSVE-NEXT: ldr h0, [sp, #54]185; NONEON-NOSVE-NEXT: fcvt s1, h0186; NONEON-NOSVE-NEXT: ldr h0, [sp, #52]187; NONEON-NOSVE-NEXT: fcvt s0, h0188; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #104]189; NONEON-NOSVE-NEXT: ldr h0, [sp, #50]190; NONEON-NOSVE-NEXT: fcvt s1, h0191; NONEON-NOSVE-NEXT: ldr h0, [sp, #48]192; NONEON-NOSVE-NEXT: fcvt s0, h0193; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #96]194; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]195; NONEON-NOSVE-NEXT: stp q2, q3, [x0]196; NONEON-NOSVE-NEXT: stp q1, q0, [x0, #32]197; NONEON-NOSVE-NEXT: add sp, sp, #128198; NONEON-NOSVE-NEXT: ret199 %res = fpext <16 x half> %a to <16 x float>200 store <16 x float> %res, ptr %b201 ret void202}203 204;205;206; FCVT H -> S207;208 209define void @fcvt_v2f16_v2f32(ptr %a, ptr %b) {210; CHECK-LABEL: fcvt_v2f16_v2f32:211; CHECK: // %bb.0:212; CHECK-NEXT: ptrue p0.s, vl2213; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]214; CHECK-NEXT: fcvt z0.s, p0/m, z0.h215; CHECK-NEXT: str d0, [x1]216; CHECK-NEXT: ret217;218; NONEON-NOSVE-LABEL: fcvt_v2f16_v2f32:219; NONEON-NOSVE: // %bb.0:220; NONEON-NOSVE-NEXT: sub sp, sp, #32221; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32222; NONEON-NOSVE-NEXT: ldr w8, [x0]223; NONEON-NOSVE-NEXT: str w8, [sp, #8]224; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]225; NONEON-NOSVE-NEXT: str d0, [sp, #16]226; NONEON-NOSVE-NEXT: ldr h0, [sp, #18]227; NONEON-NOSVE-NEXT: fcvt s1, h0228; NONEON-NOSVE-NEXT: ldr h0, [sp, #16]229; NONEON-NOSVE-NEXT: fcvt s0, h0230; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #24]231; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]232; NONEON-NOSVE-NEXT: str d0, [x1]233; NONEON-NOSVE-NEXT: add sp, sp, #32234; NONEON-NOSVE-NEXT: ret235 %op1 = load <2 x half>, ptr %a236 %res = fpext <2 x half> %op1 to <2 x float>237 store <2 x float> %res, ptr %b238 ret void239}240 241define void @fcvt_v4f16_v4f32(ptr %a, ptr %b) {242; CHECK-LABEL: fcvt_v4f16_v4f32:243; CHECK: // %bb.0:244; CHECK-NEXT: ptrue p0.s, vl4245; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]246; CHECK-NEXT: fcvt z0.s, p0/m, z0.h247; CHECK-NEXT: str q0, [x1]248; CHECK-NEXT: ret249;250; NONEON-NOSVE-LABEL: fcvt_v4f16_v4f32:251; NONEON-NOSVE: // %bb.0:252; NONEON-NOSVE-NEXT: sub sp, sp, #32253; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32254; NONEON-NOSVE-NEXT: ldr d0, [x0]255; NONEON-NOSVE-NEXT: str d0, [sp, #8]256; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]257; NONEON-NOSVE-NEXT: fcvt s1, h0258; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]259; NONEON-NOSVE-NEXT: fcvt s0, h0260; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #24]261; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]262; NONEON-NOSVE-NEXT: fcvt s1, h0263; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]264; NONEON-NOSVE-NEXT: fcvt s0, h0265; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #16]266; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]267; NONEON-NOSVE-NEXT: str q0, [x1]268; NONEON-NOSVE-NEXT: add sp, sp, #32269; NONEON-NOSVE-NEXT: ret270 %op1 = load <4 x half>, ptr %a271 %res = fpext <4 x half> %op1 to <4 x float>272 store <4 x float> %res, ptr %b273 ret void274}275 276define void @fcvt_v8f16_v8f32(ptr %a, ptr %b) {277; CHECK-LABEL: fcvt_v8f16_v8f32:278; CHECK: // %bb.0:279; CHECK-NEXT: ptrue p0.s, vl4280; CHECK-NEXT: mov x8, #4 // =0x4281; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, x8, lsl #1]282; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0]283; CHECK-NEXT: fcvt z0.s, p0/m, z0.h284; CHECK-NEXT: fcvt z1.s, p0/m, z1.h285; CHECK-NEXT: stp q1, q0, [x1]286; CHECK-NEXT: ret287;288; NONEON-NOSVE-LABEL: fcvt_v8f16_v8f32:289; NONEON-NOSVE: // %bb.0:290; NONEON-NOSVE-NEXT: ldr q0, [x0]291; NONEON-NOSVE-NEXT: str q0, [sp, #-64]!292; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64293; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]294; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]295; NONEON-NOSVE-NEXT: ldr h0, [sp, #30]296; NONEON-NOSVE-NEXT: fcvt s1, h0297; NONEON-NOSVE-NEXT: ldr h0, [sp, #28]298; NONEON-NOSVE-NEXT: fcvt s0, h0299; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #56]300; NONEON-NOSVE-NEXT: ldr h0, [sp, #26]301; NONEON-NOSVE-NEXT: fcvt s1, h0302; NONEON-NOSVE-NEXT: ldr h0, [sp, #24]303; NONEON-NOSVE-NEXT: fcvt s0, h0304; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #48]305; NONEON-NOSVE-NEXT: ldr h0, [sp, #22]306; NONEON-NOSVE-NEXT: fcvt s1, h0307; NONEON-NOSVE-NEXT: ldr h0, [sp, #20]308; NONEON-NOSVE-NEXT: fcvt s0, h0309; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #40]310; NONEON-NOSVE-NEXT: ldr h0, [sp, #18]311; NONEON-NOSVE-NEXT: fcvt s1, h0312; NONEON-NOSVE-NEXT: ldr h0, [sp, #16]313; NONEON-NOSVE-NEXT: fcvt s0, h0314; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #32]315; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]316; NONEON-NOSVE-NEXT: stp q1, q0, [x1]317; NONEON-NOSVE-NEXT: add sp, sp, #64318; NONEON-NOSVE-NEXT: ret319 %op1 = load <8 x half>, ptr %a320 %res = fpext <8 x half> %op1 to <8 x float>321 store <8 x float> %res, ptr %b322 ret void323}324 325define void @fcvt_v16f16_v16f32(ptr %a, ptr %b) {326; CHECK-LABEL: fcvt_v16f16_v16f32:327; CHECK: // %bb.0:328; CHECK-NEXT: ptrue p0.s, vl4329; CHECK-NEXT: mov x8, #8 // =0x8330; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, x8, lsl #1]331; CHECK-NEXT: mov x8, #12 // =0xc332; CHECK-NEXT: ld1h { z2.s }, p0/z, [x0]333; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0, x8, lsl #1]334; CHECK-NEXT: mov x8, #4 // =0x4335; CHECK-NEXT: ld1h { z3.s }, p0/z, [x0, x8, lsl #1]336; CHECK-NEXT: fcvt z0.s, p0/m, z0.h337; CHECK-NEXT: fcvt z2.s, p0/m, z2.h338; CHECK-NEXT: fcvt z1.s, p0/m, z1.h339; CHECK-NEXT: fcvt z3.s, p0/m, z3.h340; CHECK-NEXT: stp q0, q1, [x1, #32]341; CHECK-NEXT: stp q2, q3, [x1]342; CHECK-NEXT: ret343;344; NONEON-NOSVE-LABEL: fcvt_v16f16_v16f32:345; NONEON-NOSVE: // %bb.0:346; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]347; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-128]!348; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128349; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]350; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]351; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16]352; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]353; NONEON-NOSVE-NEXT: ldr h0, [sp, #46]354; NONEON-NOSVE-NEXT: fcvt s1, h0355; NONEON-NOSVE-NEXT: ldr h0, [sp, #44]356; NONEON-NOSVE-NEXT: fcvt s0, h0357; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #88]358; NONEON-NOSVE-NEXT: ldr h0, [sp, #42]359; NONEON-NOSVE-NEXT: fcvt s1, h0360; NONEON-NOSVE-NEXT: ldr h0, [sp, #40]361; NONEON-NOSVE-NEXT: fcvt s0, h0362; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #80]363; NONEON-NOSVE-NEXT: ldr h0, [sp, #38]364; NONEON-NOSVE-NEXT: fcvt s1, h0365; NONEON-NOSVE-NEXT: ldr h0, [sp, #36]366; NONEON-NOSVE-NEXT: fcvt s0, h0367; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #72]368; NONEON-NOSVE-NEXT: ldr h0, [sp, #34]369; NONEON-NOSVE-NEXT: fcvt s1, h0370; NONEON-NOSVE-NEXT: ldr h0, [sp, #32]371; NONEON-NOSVE-NEXT: fcvt s0, h0372; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #64]373; NONEON-NOSVE-NEXT: ldr h0, [sp, #62]374; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64]375; NONEON-NOSVE-NEXT: fcvt s1, h0376; NONEON-NOSVE-NEXT: ldr h0, [sp, #60]377; NONEON-NOSVE-NEXT: fcvt s0, h0378; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #120]379; NONEON-NOSVE-NEXT: ldr h0, [sp, #58]380; NONEON-NOSVE-NEXT: fcvt s1, h0381; NONEON-NOSVE-NEXT: ldr h0, [sp, #56]382; NONEON-NOSVE-NEXT: fcvt s0, h0383; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #112]384; NONEON-NOSVE-NEXT: ldr h0, [sp, #54]385; NONEON-NOSVE-NEXT: fcvt s1, h0386; NONEON-NOSVE-NEXT: ldr h0, [sp, #52]387; NONEON-NOSVE-NEXT: fcvt s0, h0388; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #104]389; NONEON-NOSVE-NEXT: ldr h0, [sp, #50]390; NONEON-NOSVE-NEXT: fcvt s1, h0391; NONEON-NOSVE-NEXT: ldr h0, [sp, #48]392; NONEON-NOSVE-NEXT: fcvt s0, h0393; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #96]394; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]395; NONEON-NOSVE-NEXT: stp q2, q3, [x1]396; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32]397; NONEON-NOSVE-NEXT: add sp, sp, #128398; NONEON-NOSVE-NEXT: ret399 %op1 = load <16 x half>, ptr %a400 %res = fpext <16 x half> %op1 to <16 x float>401 store <16 x float> %res, ptr %b402 ret void403}404 405;406; FCVT H -> D407;408 409define void @fcvt_v1f16_v1f64(ptr %a, ptr %b) {410; CHECK-LABEL: fcvt_v1f16_v1f64:411; CHECK: // %bb.0:412; CHECK-NEXT: ldr h0, [x0]413; CHECK-NEXT: fcvt d0, h0414; CHECK-NEXT: str d0, [x1]415; CHECK-NEXT: ret416;417; NONEON-NOSVE-LABEL: fcvt_v1f16_v1f64:418; NONEON-NOSVE: // %bb.0:419; NONEON-NOSVE-NEXT: sub sp, sp, #16420; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16421; NONEON-NOSVE-NEXT: ldr h0, [x0]422; NONEON-NOSVE-NEXT: fcvt d0, h0423; NONEON-NOSVE-NEXT: str d0, [sp, #8]424; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]425; NONEON-NOSVE-NEXT: str d0, [x1]426; NONEON-NOSVE-NEXT: add sp, sp, #16427; NONEON-NOSVE-NEXT: ret428 %op1 = load <1 x half>, ptr %a429 %res = fpext <1 x half> %op1 to <1 x double>430 store <1 x double> %res, ptr %b431 ret void432}433 434define void @fcvt_v2f16_v2f64(ptr %a, ptr %b) {435; CHECK-LABEL: fcvt_v2f16_v2f64:436; CHECK: // %bb.0:437; CHECK-NEXT: ptrue p0.d, vl2438; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]439; CHECK-NEXT: fcvt z0.d, p0/m, z0.h440; CHECK-NEXT: str q0, [x1]441; CHECK-NEXT: ret442;443; NONEON-NOSVE-LABEL: fcvt_v2f16_v2f64:444; NONEON-NOSVE: // %bb.0:445; NONEON-NOSVE-NEXT: ldr w8, [x0]446; NONEON-NOSVE-NEXT: str w8, [sp, #-32]!447; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32448; NONEON-NOSVE-NEXT: ldr d0, [sp]449; NONEON-NOSVE-NEXT: str d0, [sp, #8]450; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]451; NONEON-NOSVE-NEXT: fcvt s0, h0452; NONEON-NOSVE-NEXT: fcvt d1, s0453; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]454; NONEON-NOSVE-NEXT: fcvt s0, h0455; NONEON-NOSVE-NEXT: fcvt d0, s0456; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]457; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]458; NONEON-NOSVE-NEXT: str q0, [x1]459; NONEON-NOSVE-NEXT: add sp, sp, #32460; NONEON-NOSVE-NEXT: ret461 %op1 = load <2 x half>, ptr %a462 %res = fpext <2 x half> %op1 to <2 x double>463 store <2 x double> %res, ptr %b464 ret void465}466 467define void @fcvt_v4f16_v4f64(ptr %a, ptr %b) {468; CHECK-LABEL: fcvt_v4f16_v4f64:469; CHECK: // %bb.0:470; CHECK-NEXT: ptrue p0.d, vl2471; CHECK-NEXT: mov x8, #2 // =0x2472; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, x8, lsl #1]473; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0]474; CHECK-NEXT: fcvt z0.d, p0/m, z0.h475; CHECK-NEXT: fcvt z1.d, p0/m, z1.h476; CHECK-NEXT: stp q1, q0, [x1]477; CHECK-NEXT: ret478;479; NONEON-NOSVE-LABEL: fcvt_v4f16_v4f64:480; NONEON-NOSVE: // %bb.0:481; NONEON-NOSVE-NEXT: sub sp, sp, #48482; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48483; NONEON-NOSVE-NEXT: ldr d0, [x0]484; NONEON-NOSVE-NEXT: str d0, [sp, #8]485; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]486; NONEON-NOSVE-NEXT: fcvt s0, h0487; NONEON-NOSVE-NEXT: fcvt d1, s0488; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]489; NONEON-NOSVE-NEXT: fcvt s0, h0490; NONEON-NOSVE-NEXT: fcvt d0, s0491; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]492; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]493; NONEON-NOSVE-NEXT: fcvt s0, h0494; NONEON-NOSVE-NEXT: fcvt d1, s0495; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]496; NONEON-NOSVE-NEXT: fcvt s0, h0497; NONEON-NOSVE-NEXT: fcvt d0, s0498; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]499; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #16]500; NONEON-NOSVE-NEXT: stp q1, q0, [x1]501; NONEON-NOSVE-NEXT: add sp, sp, #48502; NONEON-NOSVE-NEXT: ret503 %op1 = load <4 x half>, ptr %a504 %res = fpext <4 x half> %op1 to <4 x double>505 store <4 x double> %res, ptr %b506 ret void507}508 509define void @fcvt_v8f16_v8f64(ptr %a, ptr %b) {510; CHECK-LABEL: fcvt_v8f16_v8f64:511; CHECK: // %bb.0:512; CHECK-NEXT: ptrue p0.d, vl2513; CHECK-NEXT: mov x8, #4 // =0x4514; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, x8, lsl #1]515; CHECK-NEXT: mov x8, #6 // =0x6516; CHECK-NEXT: ld1h { z2.d }, p0/z, [x0]517; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, x8, lsl #1]518; CHECK-NEXT: mov x8, #2 // =0x2519; CHECK-NEXT: ld1h { z3.d }, p0/z, [x0, x8, lsl #1]520; CHECK-NEXT: fcvt z0.d, p0/m, z0.h521; CHECK-NEXT: fcvt z2.d, p0/m, z2.h522; CHECK-NEXT: fcvt z1.d, p0/m, z1.h523; CHECK-NEXT: fcvt z3.d, p0/m, z3.h524; CHECK-NEXT: stp q0, q1, [x1, #32]525; CHECK-NEXT: stp q2, q3, [x1]526; CHECK-NEXT: ret527;528; NONEON-NOSVE-LABEL: fcvt_v8f16_v8f64:529; NONEON-NOSVE: // %bb.0:530; NONEON-NOSVE-NEXT: ldr q0, [x0]531; NONEON-NOSVE-NEXT: str q0, [sp, #-96]!532; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96533; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]534; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]535; NONEON-NOSVE-NEXT: ldr h0, [sp, #26]536; NONEON-NOSVE-NEXT: fcvt s0, h0537; NONEON-NOSVE-NEXT: fcvt d1, s0538; NONEON-NOSVE-NEXT: ldr h0, [sp, #24]539; NONEON-NOSVE-NEXT: fcvt s0, h0540; NONEON-NOSVE-NEXT: fcvt d0, s0541; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #80]542; NONEON-NOSVE-NEXT: ldr h0, [sp, #30]543; NONEON-NOSVE-NEXT: fcvt s0, h0544; NONEON-NOSVE-NEXT: fcvt d1, s0545; NONEON-NOSVE-NEXT: ldr h0, [sp, #28]546; NONEON-NOSVE-NEXT: fcvt s0, h0547; NONEON-NOSVE-NEXT: fcvt d0, s0548; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #64]549; NONEON-NOSVE-NEXT: ldr h0, [sp, #18]550; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64]551; NONEON-NOSVE-NEXT: fcvt s0, h0552; NONEON-NOSVE-NEXT: fcvt d1, s0553; NONEON-NOSVE-NEXT: ldr h0, [sp, #16]554; NONEON-NOSVE-NEXT: fcvt s0, h0555; NONEON-NOSVE-NEXT: fcvt d0, s0556; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]557; NONEON-NOSVE-NEXT: ldr h0, [sp, #22]558; NONEON-NOSVE-NEXT: fcvt s0, h0559; NONEON-NOSVE-NEXT: fcvt d1, s0560; NONEON-NOSVE-NEXT: ldr h0, [sp, #20]561; NONEON-NOSVE-NEXT: fcvt s0, h0562; NONEON-NOSVE-NEXT: fcvt d0, s0563; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]564; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]565; NONEON-NOSVE-NEXT: stp q2, q3, [x1]566; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32]567; NONEON-NOSVE-NEXT: add sp, sp, #96568; NONEON-NOSVE-NEXT: ret569 %op1 = load <8 x half>, ptr %a570 %res = fpext <8 x half> %op1 to <8 x double>571 store <8 x double> %res, ptr %b572 ret void573}574 575define void @fcvt_v16f16_v16f64(ptr %a, ptr %b) {576; CHECK-LABEL: fcvt_v16f16_v16f64:577; CHECK: // %bb.0:578; CHECK-NEXT: ptrue p0.d, vl2579; CHECK-NEXT: mov x8, #12 // =0xc580; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, x8, lsl #1]581; CHECK-NEXT: mov x8, #14 // =0xe582; CHECK-NEXT: ld1h { z6.d }, p0/z, [x0]583; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, x8, lsl #1]584; CHECK-NEXT: mov x8, #8 // =0x8585; CHECK-NEXT: ld1h { z2.d }, p0/z, [x0, x8, lsl #1]586; CHECK-NEXT: mov x8, #10 // =0xa587; CHECK-NEXT: ld1h { z3.d }, p0/z, [x0, x8, lsl #1]588; CHECK-NEXT: mov x8, #4 // =0x4589; CHECK-NEXT: fcvt z0.d, p0/m, z0.h590; CHECK-NEXT: ld1h { z4.d }, p0/z, [x0, x8, lsl #1]591; CHECK-NEXT: mov x8, #6 // =0x6592; CHECK-NEXT: fcvt z1.d, p0/m, z1.h593; CHECK-NEXT: ld1h { z5.d }, p0/z, [x0, x8, lsl #1]594; CHECK-NEXT: fcvt z2.d, p0/m, z2.h595; CHECK-NEXT: mov x8, #2 // =0x2596; CHECK-NEXT: fcvt z3.d, p0/m, z3.h597; CHECK-NEXT: ld1h { z7.d }, p0/z, [x0, x8, lsl #1]598; CHECK-NEXT: fcvt z4.d, p0/m, z4.h599; CHECK-NEXT: stp q0, q1, [x1, #96]600; CHECK-NEXT: movprfx z0, z5601; CHECK-NEXT: fcvt z0.d, p0/m, z5.h602; CHECK-NEXT: movprfx z1, z6603; CHECK-NEXT: fcvt z1.d, p0/m, z6.h604; CHECK-NEXT: stp q2, q3, [x1, #64]605; CHECK-NEXT: movprfx z2, z7606; CHECK-NEXT: fcvt z2.d, p0/m, z7.h607; CHECK-NEXT: stp q4, q0, [x1, #32]608; CHECK-NEXT: stp q1, q2, [x1]609; CHECK-NEXT: ret610;611; NONEON-NOSVE-LABEL: fcvt_v16f16_v16f64:612; NONEON-NOSVE: // %bb.0:613; NONEON-NOSVE-NEXT: sub sp, sp, #192614; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 192615; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]616; NONEON-NOSVE-NEXT: stp q0, q1, [sp]617; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]618; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]619; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16]620; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]621; NONEON-NOSVE-NEXT: ldr h0, [sp, #42]622; NONEON-NOSVE-NEXT: fcvt s0, h0623; NONEON-NOSVE-NEXT: fcvt d1, s0624; NONEON-NOSVE-NEXT: ldr h0, [sp, #40]625; NONEON-NOSVE-NEXT: fcvt s0, h0626; NONEON-NOSVE-NEXT: fcvt d0, s0627; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #112]628; NONEON-NOSVE-NEXT: ldr h0, [sp, #46]629; NONEON-NOSVE-NEXT: fcvt s0, h0630; NONEON-NOSVE-NEXT: fcvt d1, s0631; NONEON-NOSVE-NEXT: ldr h0, [sp, #44]632; NONEON-NOSVE-NEXT: fcvt s0, h0633; NONEON-NOSVE-NEXT: fcvt d0, s0634; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #96]635; NONEON-NOSVE-NEXT: ldr h0, [sp, #34]636; NONEON-NOSVE-NEXT: fcvt s0, h0637; NONEON-NOSVE-NEXT: fcvt d1, s0638; NONEON-NOSVE-NEXT: ldr h0, [sp, #32]639; NONEON-NOSVE-NEXT: fcvt s0, h0640; NONEON-NOSVE-NEXT: fcvt d0, s0641; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #80]642; NONEON-NOSVE-NEXT: ldr h0, [sp, #38]643; NONEON-NOSVE-NEXT: fcvt s0, h0644; NONEON-NOSVE-NEXT: fcvt d1, s0645; NONEON-NOSVE-NEXT: ldr h0, [sp, #36]646; NONEON-NOSVE-NEXT: fcvt s0, h0647; NONEON-NOSVE-NEXT: fcvt d0, s0648; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #64]649; NONEON-NOSVE-NEXT: ldr h0, [sp, #58]650; NONEON-NOSVE-NEXT: ldp q4, q3, [sp, #64]651; NONEON-NOSVE-NEXT: fcvt s0, h0652; NONEON-NOSVE-NEXT: fcvt d1, s0653; NONEON-NOSVE-NEXT: ldr h0, [sp, #56]654; NONEON-NOSVE-NEXT: fcvt s0, h0655; NONEON-NOSVE-NEXT: fcvt d0, s0656; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #176]657; NONEON-NOSVE-NEXT: ldr h0, [sp, #62]658; NONEON-NOSVE-NEXT: fcvt s0, h0659; NONEON-NOSVE-NEXT: fcvt d1, s0660; NONEON-NOSVE-NEXT: ldr h0, [sp, #60]661; NONEON-NOSVE-NEXT: fcvt s0, h0662; NONEON-NOSVE-NEXT: fcvt d0, s0663; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #160]664; NONEON-NOSVE-NEXT: ldr h0, [sp, #50]665; NONEON-NOSVE-NEXT: ldp q7, q6, [sp, #160]666; NONEON-NOSVE-NEXT: fcvt s0, h0667; NONEON-NOSVE-NEXT: fcvt d1, s0668; NONEON-NOSVE-NEXT: ldr h0, [sp, #48]669; NONEON-NOSVE-NEXT: fcvt s0, h0670; NONEON-NOSVE-NEXT: fcvt d0, s0671; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #144]672; NONEON-NOSVE-NEXT: ldr h0, [sp, #54]673; NONEON-NOSVE-NEXT: fcvt s0, h0674; NONEON-NOSVE-NEXT: fcvt d1, s0675; NONEON-NOSVE-NEXT: ldr h0, [sp, #52]676; NONEON-NOSVE-NEXT: fcvt s0, h0677; NONEON-NOSVE-NEXT: fcvt d0, s0678; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #128]679; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #96]680; NONEON-NOSVE-NEXT: ldp q2, q5, [sp, #128]681; NONEON-NOSVE-NEXT: stp q3, q4, [x1, #32]682; NONEON-NOSVE-NEXT: stp q6, q7, [x1, #64]683; NONEON-NOSVE-NEXT: stp q0, q1, [x1]684; NONEON-NOSVE-NEXT: stp q5, q2, [x1, #96]685; NONEON-NOSVE-NEXT: add sp, sp, #192686; NONEON-NOSVE-NEXT: ret687 %op1 = load <16 x half>, ptr %a688 %res = fpext <16 x half> %op1 to <16 x double>689 store <16 x double> %res, ptr %b690 ret void691}692 693;694; FCVT S -> D695;696 697define void @fcvt_v1f32_v1f64(ptr %a, ptr %b) {698; CHECK-LABEL: fcvt_v1f32_v1f64:699; CHECK: // %bb.0:700; CHECK-NEXT: ldr s0, [x0]701; CHECK-NEXT: fcvt d0, s0702; CHECK-NEXT: str d0, [x1]703; CHECK-NEXT: ret704;705; NONEON-NOSVE-LABEL: fcvt_v1f32_v1f64:706; NONEON-NOSVE: // %bb.0:707; NONEON-NOSVE-NEXT: ldr s0, [x0]708; NONEON-NOSVE-NEXT: fcvt d0, s0709; NONEON-NOSVE-NEXT: str d0, [x1]710; NONEON-NOSVE-NEXT: ret711 %op1 = load <1 x float>, ptr %a712 %res = fpext <1 x float> %op1 to <1 x double>713 store <1 x double> %res, ptr %b714 ret void715}716 717define void @fcvt_v2f32_v2f64(ptr %a, ptr %b) {718; CHECK-LABEL: fcvt_v2f32_v2f64:719; CHECK: // %bb.0:720; CHECK-NEXT: ptrue p0.d, vl2721; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]722; CHECK-NEXT: fcvt z0.d, p0/m, z0.s723; CHECK-NEXT: str q0, [x1]724; CHECK-NEXT: ret725;726; NONEON-NOSVE-LABEL: fcvt_v2f32_v2f64:727; NONEON-NOSVE: // %bb.0:728; NONEON-NOSVE-NEXT: sub sp, sp, #32729; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32730; NONEON-NOSVE-NEXT: ldr d0, [x0]731; NONEON-NOSVE-NEXT: str d0, [sp, #8]732; NONEON-NOSVE-NEXT: ldr s0, [sp, #12]733; NONEON-NOSVE-NEXT: fcvt d1, s0734; NONEON-NOSVE-NEXT: ldr s0, [sp, #8]735; NONEON-NOSVE-NEXT: fcvt d0, s0736; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]737; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]738; NONEON-NOSVE-NEXT: str q0, [x1]739; NONEON-NOSVE-NEXT: add sp, sp, #32740; NONEON-NOSVE-NEXT: ret741 %op1 = load <2 x float>, ptr %a742 %res = fpext <2 x float> %op1 to <2 x double>743 store <2 x double> %res, ptr %b744 ret void745}746 747define void @fcvt_v4f32_v4f64(ptr %a, ptr %b) {748; CHECK-LABEL: fcvt_v4f32_v4f64:749; CHECK: // %bb.0:750; CHECK-NEXT: ptrue p0.d, vl2751; CHECK-NEXT: mov x8, #2 // =0x2752; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, x8, lsl #2]753; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0]754; CHECK-NEXT: fcvt z0.d, p0/m, z0.s755; CHECK-NEXT: fcvt z1.d, p0/m, z1.s756; CHECK-NEXT: stp q1, q0, [x1]757; CHECK-NEXT: ret758;759; NONEON-NOSVE-LABEL: fcvt_v4f32_v4f64:760; NONEON-NOSVE: // %bb.0:761; NONEON-NOSVE-NEXT: ldr q0, [x0]762; NONEON-NOSVE-NEXT: str q0, [sp, #-64]!763; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64764; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]765; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]766; NONEON-NOSVE-NEXT: ldr s0, [sp, #28]767; NONEON-NOSVE-NEXT: fcvt d1, s0768; NONEON-NOSVE-NEXT: ldr s0, [sp, #24]769; NONEON-NOSVE-NEXT: fcvt d0, s0770; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]771; NONEON-NOSVE-NEXT: ldr s0, [sp, #20]772; NONEON-NOSVE-NEXT: fcvt d1, s0773; NONEON-NOSVE-NEXT: ldr s0, [sp, #16]774; NONEON-NOSVE-NEXT: fcvt d0, s0775; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]776; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]777; NONEON-NOSVE-NEXT: stp q1, q0, [x1]778; NONEON-NOSVE-NEXT: add sp, sp, #64779; NONEON-NOSVE-NEXT: ret780 %op1 = load <4 x float>, ptr %a781 %res = fpext <4 x float> %op1 to <4 x double>782 store <4 x double> %res, ptr %b783 ret void784}785 786define void @fcvt_v8f32_v8f64(ptr %a, ptr %b) {787; CHECK-LABEL: fcvt_v8f32_v8f64:788; CHECK: // %bb.0:789; CHECK-NEXT: ptrue p0.d, vl2790; CHECK-NEXT: mov x8, #4 // =0x4791; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, x8, lsl #2]792; CHECK-NEXT: mov x8, #6 // =0x6793; CHECK-NEXT: ld1w { z2.d }, p0/z, [x0]794; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0, x8, lsl #2]795; CHECK-NEXT: mov x8, #2 // =0x2796; CHECK-NEXT: ld1w { z3.d }, p0/z, [x0, x8, lsl #2]797; CHECK-NEXT: fcvt z0.d, p0/m, z0.s798; CHECK-NEXT: fcvt z2.d, p0/m, z2.s799; CHECK-NEXT: fcvt z1.d, p0/m, z1.s800; CHECK-NEXT: fcvt z3.d, p0/m, z3.s801; CHECK-NEXT: stp q0, q1, [x1, #32]802; CHECK-NEXT: stp q2, q3, [x1]803; CHECK-NEXT: ret804;805; NONEON-NOSVE-LABEL: fcvt_v8f32_v8f64:806; NONEON-NOSVE: // %bb.0:807; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]808; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-128]!809; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128810; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]811; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]812; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16]813; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]814; NONEON-NOSVE-NEXT: ldr s0, [sp, #44]815; NONEON-NOSVE-NEXT: fcvt d1, s0816; NONEON-NOSVE-NEXT: ldr s0, [sp, #40]817; NONEON-NOSVE-NEXT: fcvt d0, s0818; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #80]819; NONEON-NOSVE-NEXT: ldr s0, [sp, #36]820; NONEON-NOSVE-NEXT: fcvt d1, s0821; NONEON-NOSVE-NEXT: ldr s0, [sp, #32]822; NONEON-NOSVE-NEXT: fcvt d0, s0823; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #64]824; NONEON-NOSVE-NEXT: ldr s0, [sp, #60]825; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64]826; NONEON-NOSVE-NEXT: fcvt d1, s0827; NONEON-NOSVE-NEXT: ldr s0, [sp, #56]828; NONEON-NOSVE-NEXT: fcvt d0, s0829; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #112]830; NONEON-NOSVE-NEXT: ldr s0, [sp, #52]831; NONEON-NOSVE-NEXT: fcvt d1, s0832; NONEON-NOSVE-NEXT: ldr s0, [sp, #48]833; NONEON-NOSVE-NEXT: fcvt d0, s0834; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #96]835; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]836; NONEON-NOSVE-NEXT: stp q2, q3, [x1]837; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32]838; NONEON-NOSVE-NEXT: add sp, sp, #128839; NONEON-NOSVE-NEXT: ret840 %op1 = load <8 x float>, ptr %a841 %res = fpext <8 x float> %op1 to <8 x double>842 store <8 x double> %res, ptr %b843 ret void844}845 846;847; FCVT S -> H848;849 850define void @fcvt_v2f32_v2f16(ptr %a, ptr %b) {851; CHECK-LABEL: fcvt_v2f32_v2f16:852; CHECK: // %bb.0:853; CHECK-NEXT: ptrue p0.s, vl2854; CHECK-NEXT: ldr d0, [x0]855; CHECK-NEXT: fcvt z0.h, p0/m, z0.s856; CHECK-NEXT: st1h { z0.s }, p0, [x1]857; CHECK-NEXT: ret858;859; NONEON-NOSVE-LABEL: fcvt_v2f32_v2f16:860; NONEON-NOSVE: // %bb.0:861; NONEON-NOSVE-NEXT: sub sp, sp, #32862; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32863; NONEON-NOSVE-NEXT: ldr d0, [x0]864; NONEON-NOSVE-NEXT: str d0, [sp, #8]865; NONEON-NOSVE-NEXT: ldr s0, [sp, #12]866; NONEON-NOSVE-NEXT: fcvt h0, s0867; NONEON-NOSVE-NEXT: str h0, [sp, #18]868; NONEON-NOSVE-NEXT: ldr s0, [sp, #8]869; NONEON-NOSVE-NEXT: fcvt h0, s0870; NONEON-NOSVE-NEXT: str h0, [sp, #16]871; NONEON-NOSVE-NEXT: ldr d0, [sp, #16]872; NONEON-NOSVE-NEXT: str d0, [sp, #24]873; NONEON-NOSVE-NEXT: ldr w8, [sp, #24]874; NONEON-NOSVE-NEXT: str w8, [x1]875; NONEON-NOSVE-NEXT: add sp, sp, #32876; NONEON-NOSVE-NEXT: ret877 %op1 = load <2 x float>, ptr %a878 %res = fptrunc <2 x float> %op1 to <2 x half>879 store <2 x half> %res, ptr %b880 ret void881}882 883define void @fcvt_v4f32_v4f16(ptr %a, ptr %b) {884; CHECK-LABEL: fcvt_v4f32_v4f16:885; CHECK: // %bb.0:886; CHECK-NEXT: ptrue p0.s, vl4887; CHECK-NEXT: ldr q0, [x0]888; CHECK-NEXT: fcvt z0.h, p0/m, z0.s889; CHECK-NEXT: st1h { z0.s }, p0, [x1]890; CHECK-NEXT: ret891;892; NONEON-NOSVE-LABEL: fcvt_v4f32_v4f16:893; NONEON-NOSVE: // %bb.0:894; NONEON-NOSVE-NEXT: ldr q0, [x0]895; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!896; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32897; NONEON-NOSVE-NEXT: ldr s0, [sp, #12]898; NONEON-NOSVE-NEXT: fcvt h0, s0899; NONEON-NOSVE-NEXT: str h0, [sp, #30]900; NONEON-NOSVE-NEXT: ldr s0, [sp, #8]901; NONEON-NOSVE-NEXT: fcvt h0, s0902; NONEON-NOSVE-NEXT: str h0, [sp, #28]903; NONEON-NOSVE-NEXT: ldr s0, [sp, #4]904; NONEON-NOSVE-NEXT: fcvt h0, s0905; NONEON-NOSVE-NEXT: str h0, [sp, #26]906; NONEON-NOSVE-NEXT: ldr s0, [sp]907; NONEON-NOSVE-NEXT: fcvt h0, s0908; NONEON-NOSVE-NEXT: str h0, [sp, #24]909; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]910; NONEON-NOSVE-NEXT: str d0, [x1]911; NONEON-NOSVE-NEXT: add sp, sp, #32912; NONEON-NOSVE-NEXT: ret913 %op1 = load <4 x float>, ptr %a914 %res = fptrunc <4 x float> %op1 to <4 x half>915 store <4 x half> %res, ptr %b916 ret void917}918 919define void @fcvt_v8f32_v8f16(ptr %a, ptr %b) {920; CHECK-LABEL: fcvt_v8f32_v8f16:921; CHECK: // %bb.0:922; CHECK-NEXT: ldp q1, q0, [x0]923; CHECK-NEXT: ptrue p0.s, vl4924; CHECK-NEXT: mov x8, #4 // =0x4925; CHECK-NEXT: fcvt z0.h, p0/m, z0.s926; CHECK-NEXT: fcvt z1.h, p0/m, z1.s927; CHECK-NEXT: st1h { z0.s }, p0, [x1, x8, lsl #1]928; CHECK-NEXT: st1h { z1.s }, p0, [x1]929; CHECK-NEXT: ret930;931; NONEON-NOSVE-LABEL: fcvt_v8f32_v8f16:932; NONEON-NOSVE: // %bb.0:933; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]934; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-48]!935; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48936; NONEON-NOSVE-NEXT: ldr s0, [sp, #28]937; NONEON-NOSVE-NEXT: fcvt h0, s0938; NONEON-NOSVE-NEXT: str h0, [sp, #46]939; NONEON-NOSVE-NEXT: ldr s0, [sp, #24]940; NONEON-NOSVE-NEXT: fcvt h0, s0941; NONEON-NOSVE-NEXT: str h0, [sp, #44]942; NONEON-NOSVE-NEXT: ldr s0, [sp, #20]943; NONEON-NOSVE-NEXT: fcvt h0, s0944; NONEON-NOSVE-NEXT: str h0, [sp, #42]945; NONEON-NOSVE-NEXT: ldr s0, [sp, #16]946; NONEON-NOSVE-NEXT: fcvt h0, s0947; NONEON-NOSVE-NEXT: str h0, [sp, #40]948; NONEON-NOSVE-NEXT: ldr s0, [sp, #12]949; NONEON-NOSVE-NEXT: fcvt h0, s0950; NONEON-NOSVE-NEXT: str h0, [sp, #38]951; NONEON-NOSVE-NEXT: ldr s0, [sp, #8]952; NONEON-NOSVE-NEXT: fcvt h0, s0953; NONEON-NOSVE-NEXT: str h0, [sp, #36]954; NONEON-NOSVE-NEXT: ldr s0, [sp, #4]955; NONEON-NOSVE-NEXT: fcvt h0, s0956; NONEON-NOSVE-NEXT: str h0, [sp, #34]957; NONEON-NOSVE-NEXT: ldr s0, [sp]958; NONEON-NOSVE-NEXT: fcvt h0, s0959; NONEON-NOSVE-NEXT: str h0, [sp, #32]960; NONEON-NOSVE-NEXT: ldr q0, [sp, #32]961; NONEON-NOSVE-NEXT: str q0, [x1]962; NONEON-NOSVE-NEXT: add sp, sp, #48963; NONEON-NOSVE-NEXT: ret964 %op1 = load <8 x float>, ptr %a965 %res = fptrunc <8 x float> %op1 to <8 x half>966 store <8 x half> %res, ptr %b967 ret void968}969 970;971; FCVT D -> H972;973 974define void @fcvt_v1f64_v1f16(ptr %a, ptr %b) {975; CHECK-LABEL: fcvt_v1f64_v1f16:976; CHECK: // %bb.0:977; CHECK-NEXT: ptrue p0.d, vl1978; CHECK-NEXT: ldr d0, [x0]979; CHECK-NEXT: fcvt z0.h, p0/m, z0.d980; CHECK-NEXT: st1h { z0.d }, p0, [x1]981; CHECK-NEXT: ret982;983; NONEON-NOSVE-LABEL: fcvt_v1f64_v1f16:984; NONEON-NOSVE: // %bb.0:985; NONEON-NOSVE-NEXT: ldr d0, [x0]986; NONEON-NOSVE-NEXT: fcvt h0, d0987; NONEON-NOSVE-NEXT: str h0, [x1]988; NONEON-NOSVE-NEXT: ret989 %op1 = load <1 x double>, ptr %a990 %res = fptrunc <1 x double> %op1 to <1 x half>991 store <1 x half> %res, ptr %b992 ret void993}994 995define void @fcvt_v2f64_v2f16(ptr %a, ptr %b) {996; CHECK-LABEL: fcvt_v2f64_v2f16:997; CHECK: // %bb.0:998; CHECK-NEXT: ptrue p0.d, vl2999; CHECK-NEXT: ldr q0, [x0]1000; CHECK-NEXT: fcvt z0.h, p0/m, z0.d1001; CHECK-NEXT: st1h { z0.d }, p0, [x1]1002; CHECK-NEXT: ret1003;1004; NONEON-NOSVE-LABEL: fcvt_v2f64_v2f16:1005; NONEON-NOSVE: // %bb.0:1006; NONEON-NOSVE-NEXT: ldr q0, [x0]1007; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!1008; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 321009; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]1010; NONEON-NOSVE-NEXT: fcvt h0, d01011; NONEON-NOSVE-NEXT: str h0, [sp, #18]1012; NONEON-NOSVE-NEXT: ldr d0, [sp]1013; NONEON-NOSVE-NEXT: fcvt h0, d01014; NONEON-NOSVE-NEXT: str h0, [sp, #16]1015; NONEON-NOSVE-NEXT: ldr d0, [sp, #16]1016; NONEON-NOSVE-NEXT: str d0, [sp, #24]1017; NONEON-NOSVE-NEXT: ldr w8, [sp, #24]1018; NONEON-NOSVE-NEXT: str w8, [x1]1019; NONEON-NOSVE-NEXT: add sp, sp, #321020; NONEON-NOSVE-NEXT: ret1021 %op1 = load <2 x double>, ptr %a1022 %res = fptrunc <2 x double> %op1 to <2 x half>1023 store <2 x half> %res, ptr %b1024 ret void1025}1026 1027define void @fcvt_v4f64_v4f16(ptr %a, ptr %b) {1028; CHECK-LABEL: fcvt_v4f64_v4f16:1029; CHECK: // %bb.0:1030; CHECK-NEXT: ldp q1, q0, [x0]1031; CHECK-NEXT: ptrue p0.d, vl21032; CHECK-NEXT: mov x8, #2 // =0x21033; CHECK-NEXT: fcvt z0.h, p0/m, z0.d1034; CHECK-NEXT: fcvt z1.h, p0/m, z1.d1035; CHECK-NEXT: st1h { z0.d }, p0, [x1, x8, lsl #1]1036; CHECK-NEXT: st1h { z1.d }, p0, [x1]1037; CHECK-NEXT: ret1038;1039; NONEON-NOSVE-LABEL: fcvt_v4f64_v4f16:1040; NONEON-NOSVE: // %bb.0:1041; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]1042; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-48]!1043; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 481044; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]1045; NONEON-NOSVE-NEXT: fcvt h0, d01046; NONEON-NOSVE-NEXT: str h0, [sp, #46]1047; NONEON-NOSVE-NEXT: ldr d0, [sp, #16]1048; NONEON-NOSVE-NEXT: fcvt h0, d01049; NONEON-NOSVE-NEXT: str h0, [sp, #44]1050; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]1051; NONEON-NOSVE-NEXT: fcvt h0, d01052; NONEON-NOSVE-NEXT: str h0, [sp, #42]1053; NONEON-NOSVE-NEXT: ldr d0, [sp]1054; NONEON-NOSVE-NEXT: fcvt h0, d01055; NONEON-NOSVE-NEXT: str h0, [sp, #40]1056; NONEON-NOSVE-NEXT: ldr d0, [sp, #40]1057; NONEON-NOSVE-NEXT: str d0, [x1]1058; NONEON-NOSVE-NEXT: add sp, sp, #481059; NONEON-NOSVE-NEXT: ret1060 %op1 = load <4 x double>, ptr %a1061 %res = fptrunc <4 x double> %op1 to <4 x half>1062 store <4 x half> %res, ptr %b1063 ret void1064}1065 1066;1067; FCVT D -> S1068;1069 1070define void @fcvt_v1f64_v1f32(<1 x double> %op1, ptr %b) {1071; CHECK-LABEL: fcvt_v1f64_v1f32:1072; CHECK: // %bb.0:1073; CHECK-NEXT: ptrue p0.d, vl11074; CHECK-NEXT: // kill: def $d0 killed $d0 def $z01075; CHECK-NEXT: fcvt z0.s, p0/m, z0.d1076; CHECK-NEXT: st1w { z0.d }, p0, [x0]1077; CHECK-NEXT: ret1078;1079; NONEON-NOSVE-LABEL: fcvt_v1f64_v1f32:1080; NONEON-NOSVE: // %bb.0:1081; NONEON-NOSVE-NEXT: fcvt s0, d01082; NONEON-NOSVE-NEXT: str s0, [x0]1083; NONEON-NOSVE-NEXT: ret1084 %res = fptrunc <1 x double> %op1 to <1 x float>1085 store <1 x float> %res, ptr %b1086 ret void1087}1088 1089define void @fcvt_v2f64_v2f32(<2 x double> %op1, ptr %b) {1090; CHECK-LABEL: fcvt_v2f64_v2f32:1091; CHECK: // %bb.0:1092; CHECK-NEXT: ptrue p0.d, vl21093; CHECK-NEXT: // kill: def $q0 killed $q0 def $z01094; CHECK-NEXT: fcvt z0.s, p0/m, z0.d1095; CHECK-NEXT: st1w { z0.d }, p0, [x0]1096; CHECK-NEXT: ret1097;1098; NONEON-NOSVE-LABEL: fcvt_v2f64_v2f32:1099; NONEON-NOSVE: // %bb.0:1100; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!1101; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 321102; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]1103; NONEON-NOSVE-NEXT: fcvt s1, d01104; NONEON-NOSVE-NEXT: ldr d0, [sp]1105; NONEON-NOSVE-NEXT: fcvt s0, d01106; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #24]1107; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]1108; NONEON-NOSVE-NEXT: str d0, [x0]1109; NONEON-NOSVE-NEXT: add sp, sp, #321110; NONEON-NOSVE-NEXT: ret1111 %res = fptrunc <2 x double> %op1 to <2 x float>1112 store <2 x float> %res, ptr %b1113 ret void1114}1115 1116define void @fcvt_v4f64_v4f32(ptr %a, ptr %b) {1117; CHECK-LABEL: fcvt_v4f64_v4f32:1118; CHECK: // %bb.0:1119; CHECK-NEXT: ldp q1, q0, [x0]1120; CHECK-NEXT: ptrue p0.d, vl21121; CHECK-NEXT: mov x8, #2 // =0x21122; CHECK-NEXT: fcvt z0.s, p0/m, z0.d1123; CHECK-NEXT: fcvt z1.s, p0/m, z1.d1124; CHECK-NEXT: st1w { z0.d }, p0, [x1, x8, lsl #2]1125; CHECK-NEXT: st1w { z1.d }, p0, [x1]1126; CHECK-NEXT: ret1127;1128; NONEON-NOSVE-LABEL: fcvt_v4f64_v4f32:1129; NONEON-NOSVE: // %bb.0:1130; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]1131; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-48]!1132; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 481133; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]1134; NONEON-NOSVE-NEXT: fcvt s1, d01135; NONEON-NOSVE-NEXT: ldr d0, [sp, #16]1136; NONEON-NOSVE-NEXT: fcvt s0, d01137; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #40]1138; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]1139; NONEON-NOSVE-NEXT: fcvt s1, d01140; NONEON-NOSVE-NEXT: ldr d0, [sp]1141; NONEON-NOSVE-NEXT: fcvt s0, d01142; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #32]1143; NONEON-NOSVE-NEXT: ldr q0, [sp, #32]1144; NONEON-NOSVE-NEXT: str q0, [x1]1145; NONEON-NOSVE-NEXT: add sp, sp, #481146; NONEON-NOSVE-NEXT: ret1147 %op1 = load <4 x double>, ptr %a1148 %res = fptrunc <4 x double> %op1 to <4 x float>1149 store <4 x float> %res, ptr %b1150 ret void1151}1152