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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s3; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s4; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE5 6 7target triple = "aarch64-unknown-linux-gnu"8 9define <2 x i64> @masked_gather_v2i64(ptr %a, ptr %b) vscale_range(2, 2) {10; CHECK-LABEL: masked_gather_v2i64:11; CHECK: // %bb.0:12; CHECK-NEXT: sub sp, sp, #1613; CHECK-NEXT: .cfi_def_cfa_offset 1614; CHECK-NEXT: ptrue p0.d, vl215; CHECK-NEXT: ldr q0, [x0]16; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #017; CHECK-NEXT: index z0.d, #1, #118; CHECK-NEXT: mov z1.d, p1/z, #-1 // =0xffffffffffffffff19; CHECK-NEXT: and z0.d, z1.d, z0.d20; CHECK-NEXT: ldr q1, [x1]21; CHECK-NEXT: uaddv d0, p0, z0.d22; CHECK-NEXT: ptrue p0.d23; CHECK-NEXT: str b0, [sp, #12]24; CHECK-NEXT: ldrb w8, [sp, #12]25; CHECK-NEXT: tbz w8, #0, .LBB0_226; CHECK-NEXT: // %bb.1: // %cond.load27; CHECK-NEXT: fmov x9, d128; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x9]29; CHECK-NEXT: tbnz w8, #1, .LBB0_330; CHECK-NEXT: b .LBB0_431; CHECK-NEXT: .LBB0_2:32; CHECK-NEXT: adrp x9, .LCPI0_033; CHECK-NEXT: ldr q0, [x9, :lo12:.LCPI0_0]34; CHECK-NEXT: tbz w8, #1, .LBB0_435; CHECK-NEXT: .LBB0_3: // %cond.load136; CHECK-NEXT: mov w8, #1 // =0x137; CHECK-NEXT: index z2.d, #0, #138; CHECK-NEXT: mov z1.d, z1.d[1]39; CHECK-NEXT: mov z3.d, x840; CHECK-NEXT: fmov x8, d141; CHECK-NEXT: cmpeq p0.d, p0/z, z2.d, z3.d42; CHECK-NEXT: ldr x8, [x8]43; CHECK-NEXT: mov z0.d, p0/m, x844; CHECK-NEXT: .LBB0_4: // %else245; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z046; CHECK-NEXT: add sp, sp, #1647; CHECK-NEXT: ret48;49; NONEON-NOSVE-LABEL: masked_gather_v2i64:50; NONEON-NOSVE: // %bb.0:51; NONEON-NOSVE-NEXT: sub sp, sp, #14452; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 14453; NONEON-NOSVE-NEXT: ldr q0, [x0]54; NONEON-NOSVE-NEXT: ldr q1, [x1]55; NONEON-NOSVE-NEXT: mov w8, #2 // =0x256; NONEON-NOSVE-NEXT: str q0, [sp, #112]57; NONEON-NOSVE-NEXT: ldp x10, x9, [sp, #112]58; NONEON-NOSVE-NEXT: cmp x9, #059; NONEON-NOSVE-NEXT: csel x8, x8, xzr, eq60; NONEON-NOSVE-NEXT: cmp x10, #061; NONEON-NOSVE-NEXT: csetm x9, eq62; NONEON-NOSVE-NEXT: sub w8, w8, w963; NONEON-NOSVE-NEXT: strb w8, [sp, #140]64; NONEON-NOSVE-NEXT: and w8, w8, #0xff65; NONEON-NOSVE-NEXT: tbz w8, #0, .LBB0_266; NONEON-NOSVE-NEXT: // %bb.1: // %cond.load67; NONEON-NOSVE-NEXT: str q1, [sp, #96]68; NONEON-NOSVE-NEXT: ldr x9, [sp, #96]69; NONEON-NOSVE-NEXT: ldr x9, [x9]70; NONEON-NOSVE-NEXT: str x9, [sp, #80]71; NONEON-NOSVE-NEXT: ldr q0, [sp, #80]72; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB0_373; NONEON-NOSVE-NEXT: b .LBB0_474; NONEON-NOSVE-NEXT: .LBB0_2:75; NONEON-NOSVE-NEXT: adrp x9, .LCPI0_076; NONEON-NOSVE-NEXT: ldr q0, [x9, :lo12:.LCPI0_0]77; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB0_478; NONEON-NOSVE-NEXT: .LBB0_3: // %cond.load179; NONEON-NOSVE-NEXT: str q1, [sp, #64]80; NONEON-NOSVE-NEXT: ldr x8, [sp, #72]81; NONEON-NOSVE-NEXT: ldr x8, [x8]82; NONEON-NOSVE-NEXT: str q0, [sp]83; NONEON-NOSVE-NEXT: ldr x9, [sp]84; NONEON-NOSVE-NEXT: str x8, [sp, #48]85; NONEON-NOSVE-NEXT: ldr q0, [sp, #48]86; NONEON-NOSVE-NEXT: str q0, [sp, #16]87; NONEON-NOSVE-NEXT: ldr x8, [sp, #16]88; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #32]89; NONEON-NOSVE-NEXT: ldr q0, [sp, #32]90; NONEON-NOSVE-NEXT: .LBB0_4: // %else291; NONEON-NOSVE-NEXT: add sp, sp, #14492; NONEON-NOSVE-NEXT: ret93 %vals = load <2 x i64>, ptr %a94 %ptrs = load <2 x ptr>, ptr %b95 %mask = icmp eq <2 x i64> %vals, zeroinitializer96 %res = call <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr> %ptrs, i32 8, <2 x i1> %mask, <2 x i64> poison)97 ret <2 x i64> %res98}99 100define void @masked_scatter_v2i64(ptr %a, ptr %b) vscale_range(2, 2) {101; CHECK-LABEL: masked_scatter_v2i64:102; CHECK: // %bb.0:103; CHECK-NEXT: sub sp, sp, #16104; CHECK-NEXT: .cfi_def_cfa_offset 16105; CHECK-NEXT: ptrue p0.d, vl2106; CHECK-NEXT: ldr q0, [x0]107; CHECK-NEXT: index z1.d, #1, #1108; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #0109; CHECK-NEXT: mov z2.d, p1/z, #-1 // =0xffffffffffffffff110; CHECK-NEXT: and z1.d, z2.d, z1.d111; CHECK-NEXT: uaddv d2, p0, z1.d112; CHECK-NEXT: ldr q1, [x1]113; CHECK-NEXT: str b2, [sp, #12]114; CHECK-NEXT: ldrb w8, [sp, #12]115; CHECK-NEXT: tbnz w8, #0, .LBB1_3116; CHECK-NEXT: // %bb.1: // %else117; CHECK-NEXT: tbnz w8, #1, .LBB1_4118; CHECK-NEXT: .LBB1_2: // %else2119; CHECK-NEXT: add sp, sp, #16120; CHECK-NEXT: ret121; CHECK-NEXT: .LBB1_3: // %cond.store122; CHECK-NEXT: fmov x9, d1123; CHECK-NEXT: str d0, [x9]124; CHECK-NEXT: tbz w8, #1, .LBB1_2125; CHECK-NEXT: .LBB1_4: // %cond.store1126; CHECK-NEXT: mov z1.d, z1.d[1]127; CHECK-NEXT: mov z0.d, z0.d[1]128; CHECK-NEXT: fmov x8, d1129; CHECK-NEXT: str d0, [x8]130; CHECK-NEXT: add sp, sp, #16131; CHECK-NEXT: ret132;133; NONEON-NOSVE-LABEL: masked_scatter_v2i64:134; NONEON-NOSVE: // %bb.0:135; NONEON-NOSVE-NEXT: sub sp, sp, #96136; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96137; NONEON-NOSVE-NEXT: ldr q1, [x0]138; NONEON-NOSVE-NEXT: ldr q0, [x1]139; NONEON-NOSVE-NEXT: mov w8, #2 // =0x2140; NONEON-NOSVE-NEXT: str q1, [sp, #64]141; NONEON-NOSVE-NEXT: ldp x10, x9, [sp, #64]142; NONEON-NOSVE-NEXT: cmp x9, #0143; NONEON-NOSVE-NEXT: csel x8, x8, xzr, eq144; NONEON-NOSVE-NEXT: cmp x10, #0145; NONEON-NOSVE-NEXT: csetm x9, eq146; NONEON-NOSVE-NEXT: sub w8, w8, w9147; NONEON-NOSVE-NEXT: strb w8, [sp, #92]148; NONEON-NOSVE-NEXT: and w8, w8, #0xff149; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB1_3150; NONEON-NOSVE-NEXT: // %bb.1: // %else151; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB1_4152; NONEON-NOSVE-NEXT: .LBB1_2: // %else2153; NONEON-NOSVE-NEXT: add sp, sp, #96154; NONEON-NOSVE-NEXT: ret155; NONEON-NOSVE-NEXT: .LBB1_3: // %cond.store156; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #32]157; NONEON-NOSVE-NEXT: ldr x9, [sp, #32]158; NONEON-NOSVE-NEXT: ldr x10, [sp, #48]159; NONEON-NOSVE-NEXT: str x9, [x10]160; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB1_2161; NONEON-NOSVE-NEXT: .LBB1_4: // %cond.store1162; NONEON-NOSVE-NEXT: stp q1, q0, [sp]163; NONEON-NOSVE-NEXT: ldr x8, [sp, #8]164; NONEON-NOSVE-NEXT: ldr x9, [sp, #24]165; NONEON-NOSVE-NEXT: str x8, [x9]166; NONEON-NOSVE-NEXT: add sp, sp, #96167; NONEON-NOSVE-NEXT: ret168 %vals = load <2 x i64>, ptr %a169 %ptrs = load <2 x ptr>, ptr %b170 %mask = icmp eq <2 x i64> %vals, zeroinitializer171 call void @llvm.masked.scatter.v2i64(<2 x i64> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask)172 ret void173}174 175declare void @llvm.masked.scatter.v2i64(<2 x i64>, <2 x ptr>, i32, <2 x i1>)176declare <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr>, i32, <2 x i1>, <2 x i64>)177