471 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s3; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s4; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE5 6 7; Test we can code generater patterns of the form:8; fixed_length_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 09; scalable_vector = ISD::INSERT_SUBVECTOR scalable_vector, fixed_length_vector, 010;11; NOTE: Currently shufflevector does not support scalable vectors so it cannot12; be used to model the above operations. Instead these tests rely on knowing13; how fixed length operation are lowered to scalable ones, with multiple blocks14; ensuring insert/extract sequences are not folded away.15 16target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"17target triple = "aarch64-unknown-linux-gnu"18 19; i820define void @subvector_v4i8(ptr %in, ptr %out) {21; CHECK-LABEL: subvector_v4i8:22; CHECK: // %bb.0: // %bb123; CHECK-NEXT: ptrue p0.h, vl424; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]25; CHECK-NEXT: st1b { z0.h }, p0, [x1]26; CHECK-NEXT: ret27;28; NONEON-NOSVE-LABEL: subvector_v4i8:29; NONEON-NOSVE: // %bb.0: // %bb130; NONEON-NOSVE-NEXT: ldrh w8, [x0, #2]31; NONEON-NOSVE-NEXT: ldrb w9, [x0, #1]32; NONEON-NOSVE-NEXT: ldrb w10, [x0]33; NONEON-NOSVE-NEXT: strh w8, [x1, #2]34; NONEON-NOSVE-NEXT: strb w9, [x1, #1]35; NONEON-NOSVE-NEXT: strb w10, [x1]36; NONEON-NOSVE-NEXT: ret37 %a = load <4 x i8>, ptr %in38 br label %bb139 40bb1:41 store <4 x i8> %a, ptr %out42 ret void43}44 45define void @subvector_v8i8(ptr %in, ptr %out) {46; CHECK-LABEL: subvector_v8i8:47; CHECK: // %bb.0: // %bb148; CHECK-NEXT: ldr d0, [x0]49; CHECK-NEXT: str d0, [x1]50; CHECK-NEXT: ret51;52; NONEON-NOSVE-LABEL: subvector_v8i8:53; NONEON-NOSVE: // %bb.0: // %bb154; NONEON-NOSVE-NEXT: ldr d0, [x0]55; NONEON-NOSVE-NEXT: str d0, [x1]56; NONEON-NOSVE-NEXT: ret57 %a = load <8 x i8>, ptr %in58 br label %bb159 60bb1:61 store <8 x i8> %a, ptr %out62 ret void63}64 65define void @subvector_v16i8(ptr %in, ptr %out) {66; CHECK-LABEL: subvector_v16i8:67; CHECK: // %bb.0: // %bb168; CHECK-NEXT: ldr q0, [x0]69; CHECK-NEXT: str q0, [x1]70; CHECK-NEXT: ret71;72; NONEON-NOSVE-LABEL: subvector_v16i8:73; NONEON-NOSVE: // %bb.0: // %bb174; NONEON-NOSVE-NEXT: ldr q0, [x0]75; NONEON-NOSVE-NEXT: str q0, [x1]76; NONEON-NOSVE-NEXT: ret77 %a = load <16 x i8>, ptr %in78 br label %bb179 80bb1:81 store <16 x i8> %a, ptr %out82 ret void83}84 85define void @subvector_v32i8(ptr %in, ptr %out) {86; CHECK-LABEL: subvector_v32i8:87; CHECK: // %bb.0: // %bb188; CHECK-NEXT: ldp q0, q1, [x0]89; CHECK-NEXT: stp q0, q1, [x1]90; CHECK-NEXT: ret91;92; NONEON-NOSVE-LABEL: subvector_v32i8:93; NONEON-NOSVE: // %bb.0: // %bb194; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]95; NONEON-NOSVE-NEXT: stp q0, q1, [x1]96; NONEON-NOSVE-NEXT: ret97 %a = load <32 x i8>, ptr %in98 br label %bb199 100bb1:101 store <32 x i8> %a, ptr %out102 ret void103}104 105; i16106define void @subvector_v2i16(ptr %in, ptr %out) {107; CHECK-LABEL: subvector_v2i16:108; CHECK: // %bb.0: // %bb1109; CHECK-NEXT: ptrue p0.s, vl2110; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]111; CHECK-NEXT: st1h { z0.s }, p0, [x1]112; CHECK-NEXT: ret113;114; NONEON-NOSVE-LABEL: subvector_v2i16:115; NONEON-NOSVE: // %bb.0: // %bb1116; NONEON-NOSVE-NEXT: ldr w8, [x0]117; NONEON-NOSVE-NEXT: str w8, [x1]118; NONEON-NOSVE-NEXT: ret119 %a = load <2 x i16>, ptr %in120 br label %bb1121 122bb1:123 store <2 x i16> %a, ptr %out124 ret void125}126 127define void @subvector_v4i16(ptr %in, ptr %out) {128; CHECK-LABEL: subvector_v4i16:129; CHECK: // %bb.0: // %bb1130; CHECK-NEXT: ldr d0, [x0]131; CHECK-NEXT: str d0, [x1]132; CHECK-NEXT: ret133;134; NONEON-NOSVE-LABEL: subvector_v4i16:135; NONEON-NOSVE: // %bb.0: // %bb1136; NONEON-NOSVE-NEXT: ldr d0, [x0]137; NONEON-NOSVE-NEXT: str d0, [x1]138; NONEON-NOSVE-NEXT: ret139 %a = load <4 x i16>, ptr %in140 br label %bb1141 142bb1:143 store <4 x i16> %a, ptr %out144 ret void145}146 147define void @subvector_v8i16(ptr %in, ptr %out) {148; CHECK-LABEL: subvector_v8i16:149; CHECK: // %bb.0: // %bb1150; CHECK-NEXT: ldr q0, [x0]151; CHECK-NEXT: str q0, [x1]152; CHECK-NEXT: ret153;154; NONEON-NOSVE-LABEL: subvector_v8i16:155; NONEON-NOSVE: // %bb.0: // %bb1156; NONEON-NOSVE-NEXT: ldr q0, [x0]157; NONEON-NOSVE-NEXT: str q0, [x1]158; NONEON-NOSVE-NEXT: ret159 %a = load <8 x i16>, ptr %in160 br label %bb1161 162bb1:163 store <8 x i16> %a, ptr %out164 ret void165}166 167define void @subvector_v16i16(ptr %in, ptr %out) {168; CHECK-LABEL: subvector_v16i16:169; CHECK: // %bb.0: // %bb1170; CHECK-NEXT: ldp q0, q1, [x0]171; CHECK-NEXT: stp q0, q1, [x1]172; CHECK-NEXT: ret173;174; NONEON-NOSVE-LABEL: subvector_v16i16:175; NONEON-NOSVE: // %bb.0: // %bb1176; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]177; NONEON-NOSVE-NEXT: stp q0, q1, [x1]178; NONEON-NOSVE-NEXT: ret179 %a = load <16 x i16>, ptr %in180 br label %bb1181 182bb1:183 store <16 x i16> %a, ptr %out184 ret void185}186 187; i32188define void @subvector_v2i32(ptr %in, ptr %out) {189; CHECK-LABEL: subvector_v2i32:190; CHECK: // %bb.0: // %bb1191; CHECK-NEXT: ldr d0, [x0]192; CHECK-NEXT: str d0, [x1]193; CHECK-NEXT: ret194;195; NONEON-NOSVE-LABEL: subvector_v2i32:196; NONEON-NOSVE: // %bb.0: // %bb1197; NONEON-NOSVE-NEXT: ldr d0, [x0]198; NONEON-NOSVE-NEXT: str d0, [x1]199; NONEON-NOSVE-NEXT: ret200 %a = load <2 x i32>, ptr %in201 br label %bb1202 203bb1:204 store <2 x i32> %a, ptr %out205 ret void206}207 208define void @subvector_v4i32(ptr %in, ptr %out) {209; CHECK-LABEL: subvector_v4i32:210; CHECK: // %bb.0: // %bb1211; CHECK-NEXT: ldr q0, [x0]212; CHECK-NEXT: str q0, [x1]213; CHECK-NEXT: ret214;215; NONEON-NOSVE-LABEL: subvector_v4i32:216; NONEON-NOSVE: // %bb.0: // %bb1217; NONEON-NOSVE-NEXT: ldr q0, [x0]218; NONEON-NOSVE-NEXT: str q0, [x1]219; NONEON-NOSVE-NEXT: ret220 %a = load <4 x i32>, ptr %in221 br label %bb1222 223bb1:224 store <4 x i32> %a, ptr %out225 ret void226}227 228define void @subvector_v8i32(ptr %in, ptr %out) {229; CHECK-LABEL: subvector_v8i32:230; CHECK: // %bb.0: // %bb1231; CHECK-NEXT: ldp q0, q1, [x0]232; CHECK-NEXT: stp q0, q1, [x1]233; CHECK-NEXT: ret234;235; NONEON-NOSVE-LABEL: subvector_v8i32:236; NONEON-NOSVE: // %bb.0: // %bb1237; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]238; NONEON-NOSVE-NEXT: stp q0, q1, [x1]239; NONEON-NOSVE-NEXT: ret240 %a = load <8 x i32>, ptr %in241 br label %bb1242 243bb1:244 store <8 x i32> %a, ptr %out245 ret void246}247 248; i64249define void @subvector_v2i64(ptr %in, ptr %out) {250; CHECK-LABEL: subvector_v2i64:251; CHECK: // %bb.0: // %bb1252; CHECK-NEXT: ldr q0, [x0]253; CHECK-NEXT: str q0, [x1]254; CHECK-NEXT: ret255;256; NONEON-NOSVE-LABEL: subvector_v2i64:257; NONEON-NOSVE: // %bb.0: // %bb1258; NONEON-NOSVE-NEXT: ldr q0, [x0]259; NONEON-NOSVE-NEXT: str q0, [x1]260; NONEON-NOSVE-NEXT: ret261 %a = load <2 x i64>, ptr %in262 br label %bb1263 264bb1:265 store <2 x i64> %a, ptr %out266 ret void267}268 269define void @subvector_v4i64(ptr %in, ptr %out) {270; CHECK-LABEL: subvector_v4i64:271; CHECK: // %bb.0: // %bb1272; CHECK-NEXT: ldp q0, q1, [x0]273; CHECK-NEXT: stp q0, q1, [x1]274; CHECK-NEXT: ret275;276; NONEON-NOSVE-LABEL: subvector_v4i64:277; NONEON-NOSVE: // %bb.0: // %bb1278; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]279; NONEON-NOSVE-NEXT: stp q0, q1, [x1]280; NONEON-NOSVE-NEXT: ret281 %a = load <4 x i64>, ptr %in282 br label %bb1283 284bb1:285 store <4 x i64> %a, ptr %out286 ret void287}288 289; f16290define void @subvector_v2f16(ptr %in, ptr %out) {291; CHECK-LABEL: subvector_v2f16:292; CHECK: // %bb.0: // %bb1293; CHECK-NEXT: ldr w8, [x0]294; CHECK-NEXT: str w8, [x1]295; CHECK-NEXT: ret296;297; NONEON-NOSVE-LABEL: subvector_v2f16:298; NONEON-NOSVE: // %bb.0: // %bb1299; NONEON-NOSVE-NEXT: ldr w8, [x0]300; NONEON-NOSVE-NEXT: str w8, [x1]301; NONEON-NOSVE-NEXT: ret302 %a = load <2 x half>, ptr %in303 br label %bb1304 305bb1:306 store <2 x half> %a, ptr %out307 ret void308}309 310define void @subvector_v4f16(ptr %in, ptr %out) {311; CHECK-LABEL: subvector_v4f16:312; CHECK: // %bb.0: // %bb1313; CHECK-NEXT: ldr d0, [x0]314; CHECK-NEXT: str d0, [x1]315; CHECK-NEXT: ret316;317; NONEON-NOSVE-LABEL: subvector_v4f16:318; NONEON-NOSVE: // %bb.0: // %bb1319; NONEON-NOSVE-NEXT: ldr d0, [x0]320; NONEON-NOSVE-NEXT: str d0, [x1]321; NONEON-NOSVE-NEXT: ret322 %a = load <4 x half>, ptr %in323 br label %bb1324 325bb1:326 store <4 x half> %a, ptr %out327 ret void328}329 330define void @subvector_v8f16(ptr %in, ptr %out) {331; CHECK-LABEL: subvector_v8f16:332; CHECK: // %bb.0: // %bb1333; CHECK-NEXT: ldr q0, [x0]334; CHECK-NEXT: str q0, [x1]335; CHECK-NEXT: ret336;337; NONEON-NOSVE-LABEL: subvector_v8f16:338; NONEON-NOSVE: // %bb.0: // %bb1339; NONEON-NOSVE-NEXT: ldr q0, [x0]340; NONEON-NOSVE-NEXT: str q0, [x1]341; NONEON-NOSVE-NEXT: ret342 %a = load <8 x half>, ptr %in343 br label %bb1344 345bb1:346 store <8 x half> %a, ptr %out347 ret void348}349 350define void @subvector_v16f16(ptr %in, ptr %out) {351; CHECK-LABEL: subvector_v16f16:352; CHECK: // %bb.0: // %bb1353; CHECK-NEXT: ldp q0, q1, [x0]354; CHECK-NEXT: stp q0, q1, [x1]355; CHECK-NEXT: ret356;357; NONEON-NOSVE-LABEL: subvector_v16f16:358; NONEON-NOSVE: // %bb.0: // %bb1359; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]360; NONEON-NOSVE-NEXT: stp q0, q1, [x1]361; NONEON-NOSVE-NEXT: ret362 %a = load <16 x half>, ptr %in363 br label %bb1364 365bb1:366 store <16 x half> %a, ptr %out367 ret void368}369 370; f32371define void @subvector_v2f32(ptr %in, ptr %out) {372; CHECK-LABEL: subvector_v2f32:373; CHECK: // %bb.0: // %bb1374; CHECK-NEXT: ldr d0, [x0]375; CHECK-NEXT: str d0, [x1]376; CHECK-NEXT: ret377;378; NONEON-NOSVE-LABEL: subvector_v2f32:379; NONEON-NOSVE: // %bb.0: // %bb1380; NONEON-NOSVE-NEXT: ldr d0, [x0]381; NONEON-NOSVE-NEXT: str d0, [x1]382; NONEON-NOSVE-NEXT: ret383 %a = load <2 x float>, ptr %in384 br label %bb1385 386bb1:387 store <2 x float> %a, ptr %out388 ret void389}390 391define void @subvector_v4f32(ptr %in, ptr %out) {392; CHECK-LABEL: subvector_v4f32:393; CHECK: // %bb.0: // %bb1394; CHECK-NEXT: ldr q0, [x0]395; CHECK-NEXT: str q0, [x1]396; CHECK-NEXT: ret397;398; NONEON-NOSVE-LABEL: subvector_v4f32:399; NONEON-NOSVE: // %bb.0: // %bb1400; NONEON-NOSVE-NEXT: ldr q0, [x0]401; NONEON-NOSVE-NEXT: str q0, [x1]402; NONEON-NOSVE-NEXT: ret403 %a = load <4 x float>, ptr %in404 br label %bb1405 406bb1:407 store <4 x float> %a, ptr %out408 ret void409}410 411define void @subvector_v8f32(ptr %in, ptr %out) {412; CHECK-LABEL: subvector_v8f32:413; CHECK: // %bb.0: // %bb1414; CHECK-NEXT: ldp q0, q1, [x0]415; CHECK-NEXT: stp q0, q1, [x1]416; CHECK-NEXT: ret417;418; NONEON-NOSVE-LABEL: subvector_v8f32:419; NONEON-NOSVE: // %bb.0: // %bb1420; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]421; NONEON-NOSVE-NEXT: stp q0, q1, [x1]422; NONEON-NOSVE-NEXT: ret423 %a = load <8 x float>,ptr %in424 br label %bb1425 426bb1:427 store <8 x float> %a, ptr %out428 ret void429}430 431; f64432define void @subvector_v2f64(ptr %in, ptr %out) {433; CHECK-LABEL: subvector_v2f64:434; CHECK: // %bb.0: // %bb1435; CHECK-NEXT: ldr q0, [x0]436; CHECK-NEXT: str q0, [x1]437; CHECK-NEXT: ret438;439; NONEON-NOSVE-LABEL: subvector_v2f64:440; NONEON-NOSVE: // %bb.0: // %bb1441; NONEON-NOSVE-NEXT: ldr q0, [x0]442; NONEON-NOSVE-NEXT: str q0, [x1]443; NONEON-NOSVE-NEXT: ret444 %a = load <2 x double>, ptr %in445 br label %bb1446 447bb1:448 store <2 x double> %a, ptr %out449 ret void450}451 452define void @subvector_v4f64(ptr %in, ptr %out) {453; CHECK-LABEL: subvector_v4f64:454; CHECK: // %bb.0: // %bb1455; CHECK-NEXT: ldp q0, q1, [x0]456; CHECK-NEXT: stp q0, q1, [x1]457; CHECK-NEXT: ret458;459; NONEON-NOSVE-LABEL: subvector_v4f64:460; NONEON-NOSVE: // %bb.0: // %bb1461; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]462; NONEON-NOSVE-NEXT: stp q0, q1, [x1]463; NONEON-NOSVE-NEXT: ret464 %a = load <4 x double>, ptr %in465 br label %bb1466 467bb1:468 store <4 x double> %a, ptr %out469 ret void470}471