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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s3 4declare { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)5 6define <vscale x 2 x i8> @umulo_nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y) {7; CHECK-LABEL: umulo_nxv2i8:8; CHECK: // %bb.0:9; CHECK-NEXT: and z1.d, z1.d, #0xff10; CHECK-NEXT: and z0.d, z0.d, #0xff11; CHECK-NEXT: ptrue p0.d12; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d13; CHECK-NEXT: lsr z1.d, z0.d, #814; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #015; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x016; CHECK-NEXT: ret17 %a = call { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y)18 %b = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 019 %c = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 120 %d = select <vscale x 2 x i1> %c, <vscale x 2 x i8> zeroinitializer, <vscale x 2 x i8> %b21 ret <vscale x 2 x i8> %d22}23 24declare { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)25 26define <vscale x 4 x i8> @umulo_nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y) {27; CHECK-LABEL: umulo_nxv4i8:28; CHECK: // %bb.0:29; CHECK-NEXT: and z1.s, z1.s, #0xff30; CHECK-NEXT: and z0.s, z0.s, #0xff31; CHECK-NEXT: ptrue p0.s32; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s33; CHECK-NEXT: lsr z1.s, z0.s, #834; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, #035; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x036; CHECK-NEXT: ret37 %a = call { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y)38 %b = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 039 %c = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 140 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i8> zeroinitializer, <vscale x 4 x i8> %b41 ret <vscale x 4 x i8> %d42}43 44declare { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)45 46define <vscale x 8 x i8> @umulo_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {47; CHECK-LABEL: umulo_nxv8i8:48; CHECK: // %bb.0:49; CHECK-NEXT: and z1.h, z1.h, #0xff50; CHECK-NEXT: and z0.h, z0.h, #0xff51; CHECK-NEXT: ptrue p0.h52; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h53; CHECK-NEXT: lsr z1.h, z0.h, #854; CHECK-NEXT: cmpne p0.h, p0/z, z1.h, #055; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x056; CHECK-NEXT: ret57 %a = call { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y)58 %b = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 059 %c = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 160 %d = select <vscale x 8 x i1> %c, <vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> %b61 ret <vscale x 8 x i8> %d62}63 64declare { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)65 66define <vscale x 16 x i8> @umulo_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {67; CHECK-LABEL: umulo_nxv16i8:68; CHECK: // %bb.0:69; CHECK-NEXT: ptrue p0.b70; CHECK-NEXT: movprfx z2, z071; CHECK-NEXT: umulh z2.b, p0/m, z2.b, z1.b72; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b73; CHECK-NEXT: cmpne p0.b, p0/z, z2.b, #074; CHECK-NEXT: mov z0.b, p0/m, #0 // =0x075; CHECK-NEXT: ret76 %a = call { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)77 %b = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 078 %c = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 179 %d = select <vscale x 16 x i1> %c, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %b80 ret <vscale x 16 x i8> %d81}82 83declare { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.umul.with.overflow.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>)84 85define <vscale x 32 x i8> @umulo_nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y) {86; CHECK-LABEL: umulo_nxv32i8:87; CHECK: // %bb.0:88; CHECK-NEXT: ptrue p0.b89; CHECK-NEXT: movprfx z4, z190; CHECK-NEXT: umulh z4.b, p0/m, z4.b, z3.b91; CHECK-NEXT: movprfx z5, z092; CHECK-NEXT: umulh z5.b, p0/m, z5.b, z2.b93; CHECK-NEXT: mul z1.b, p0/m, z1.b, z3.b94; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b95; CHECK-NEXT: cmpne p1.b, p0/z, z4.b, #096; CHECK-NEXT: cmpne p0.b, p0/z, z5.b, #097; CHECK-NEXT: mov z0.b, p0/m, #0 // =0x098; CHECK-NEXT: mov z1.b, p1/m, #0 // =0x099; CHECK-NEXT: ret100 %a = call { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.umul.with.overflow.nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y)101 %b = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 0102 %c = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 1103 %d = select <vscale x 32 x i1> %c, <vscale x 32 x i8> zeroinitializer, <vscale x 32 x i8> %b104 ret <vscale x 32 x i8> %d105}106 107declare { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.umul.with.overflow.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>)108 109define <vscale x 64 x i8> @umulo_nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y) {110; CHECK-LABEL: umulo_nxv64i8:111; CHECK: // %bb.0:112; CHECK-NEXT: ptrue p0.b113; CHECK-NEXT: movprfx z24, z3114; CHECK-NEXT: umulh z24.b, p0/m, z24.b, z7.b115; CHECK-NEXT: movprfx z25, z0116; CHECK-NEXT: umulh z25.b, p0/m, z25.b, z4.b117; CHECK-NEXT: movprfx z26, z2118; CHECK-NEXT: umulh z26.b, p0/m, z26.b, z6.b119; CHECK-NEXT: movprfx z27, z1120; CHECK-NEXT: umulh z27.b, p0/m, z27.b, z5.b121; CHECK-NEXT: mul z3.b, p0/m, z3.b, z7.b122; CHECK-NEXT: mul z2.b, p0/m, z2.b, z6.b123; CHECK-NEXT: mul z1.b, p0/m, z1.b, z5.b124; CHECK-NEXT: mul z0.b, p0/m, z0.b, z4.b125; CHECK-NEXT: cmpne p1.b, p0/z, z25.b, #0126; CHECK-NEXT: cmpne p2.b, p0/z, z24.b, #0127; CHECK-NEXT: cmpne p3.b, p0/z, z26.b, #0128; CHECK-NEXT: cmpne p0.b, p0/z, z27.b, #0129; CHECK-NEXT: mov z0.b, p1/m, #0 // =0x0130; CHECK-NEXT: mov z2.b, p3/m, #0 // =0x0131; CHECK-NEXT: mov z3.b, p2/m, #0 // =0x0132; CHECK-NEXT: mov z1.b, p0/m, #0 // =0x0133; CHECK-NEXT: ret134 %a = call { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.umul.with.overflow.nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y)135 %b = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 0136 %c = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 1137 %d = select <vscale x 64 x i1> %c, <vscale x 64 x i8> zeroinitializer, <vscale x 64 x i8> %b138 ret <vscale x 64 x i8> %d139}140 141declare { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)142 143define <vscale x 2 x i16> @umulo_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y) {144; CHECK-LABEL: umulo_nxv2i16:145; CHECK: // %bb.0:146; CHECK-NEXT: and z1.d, z1.d, #0xffff147; CHECK-NEXT: and z0.d, z0.d, #0xffff148; CHECK-NEXT: ptrue p0.d149; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d150; CHECK-NEXT: lsr z1.d, z0.d, #16151; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0152; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0153; CHECK-NEXT: ret154 %a = call { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y)155 %b = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 0156 %c = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 1157 %d = select <vscale x 2 x i1> %c, <vscale x 2 x i16> zeroinitializer, <vscale x 2 x i16> %b158 ret <vscale x 2 x i16> %d159}160 161declare { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)162 163define <vscale x 4 x i16> @umulo_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y) {164; CHECK-LABEL: umulo_nxv4i16:165; CHECK: // %bb.0:166; CHECK-NEXT: and z1.s, z1.s, #0xffff167; CHECK-NEXT: and z0.s, z0.s, #0xffff168; CHECK-NEXT: ptrue p0.s169; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s170; CHECK-NEXT: lsr z1.s, z0.s, #16171; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, #0172; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0173; CHECK-NEXT: ret174 %a = call { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y)175 %b = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 0176 %c = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 1177 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i16> zeroinitializer, <vscale x 4 x i16> %b178 ret <vscale x 4 x i16> %d179}180 181declare { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)182 183define <vscale x 8 x i16> @umulo_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {184; CHECK-LABEL: umulo_nxv8i16:185; CHECK: // %bb.0:186; CHECK-NEXT: ptrue p0.h187; CHECK-NEXT: movprfx z2, z0188; CHECK-NEXT: umulh z2.h, p0/m, z2.h, z1.h189; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h190; CHECK-NEXT: cmpne p0.h, p0/z, z2.h, #0191; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x0192; CHECK-NEXT: ret193 %a = call { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)194 %b = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 0195 %c = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 1196 %d = select <vscale x 8 x i1> %c, <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i16> %b197 ret <vscale x 8 x i16> %d198}199 200declare { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)201 202define <vscale x 16 x i16> @umulo_nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y) {203; CHECK-LABEL: umulo_nxv16i16:204; CHECK: // %bb.0:205; CHECK-NEXT: ptrue p0.h206; CHECK-NEXT: movprfx z4, z1207; CHECK-NEXT: umulh z4.h, p0/m, z4.h, z3.h208; CHECK-NEXT: movprfx z5, z0209; CHECK-NEXT: umulh z5.h, p0/m, z5.h, z2.h210; CHECK-NEXT: mul z1.h, p0/m, z1.h, z3.h211; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h212; CHECK-NEXT: cmpne p1.h, p0/z, z4.h, #0213; CHECK-NEXT: cmpne p0.h, p0/z, z5.h, #0214; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x0215; CHECK-NEXT: mov z1.h, p1/m, #0 // =0x0216; CHECK-NEXT: ret217 %a = call { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y)218 %b = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 0219 %c = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 1220 %d = select <vscale x 16 x i1> %c, <vscale x 16 x i16> zeroinitializer, <vscale x 16 x i16> %b221 ret <vscale x 16 x i16> %d222}223 224declare { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.umul.with.overflow.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>)225 226define <vscale x 32 x i16> @umulo_nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y) {227; CHECK-LABEL: umulo_nxv32i16:228; CHECK: // %bb.0:229; CHECK-NEXT: ptrue p0.h230; CHECK-NEXT: movprfx z24, z3231; CHECK-NEXT: umulh z24.h, p0/m, z24.h, z7.h232; CHECK-NEXT: movprfx z25, z0233; CHECK-NEXT: umulh z25.h, p0/m, z25.h, z4.h234; CHECK-NEXT: movprfx z26, z2235; CHECK-NEXT: umulh z26.h, p0/m, z26.h, z6.h236; CHECK-NEXT: movprfx z27, z1237; CHECK-NEXT: umulh z27.h, p0/m, z27.h, z5.h238; CHECK-NEXT: mul z3.h, p0/m, z3.h, z7.h239; CHECK-NEXT: mul z2.h, p0/m, z2.h, z6.h240; CHECK-NEXT: mul z1.h, p0/m, z1.h, z5.h241; CHECK-NEXT: mul z0.h, p0/m, z0.h, z4.h242; CHECK-NEXT: cmpne p1.h, p0/z, z25.h, #0243; CHECK-NEXT: cmpne p2.h, p0/z, z24.h, #0244; CHECK-NEXT: cmpne p3.h, p0/z, z26.h, #0245; CHECK-NEXT: cmpne p0.h, p0/z, z27.h, #0246; CHECK-NEXT: mov z0.h, p1/m, #0 // =0x0247; CHECK-NEXT: mov z2.h, p3/m, #0 // =0x0248; CHECK-NEXT: mov z3.h, p2/m, #0 // =0x0249; CHECK-NEXT: mov z1.h, p0/m, #0 // =0x0250; CHECK-NEXT: ret251 %a = call { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.umul.with.overflow.nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y)252 %b = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 0253 %c = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 1254 %d = select <vscale x 32 x i1> %c, <vscale x 32 x i16> zeroinitializer, <vscale x 32 x i16> %b255 ret <vscale x 32 x i16> %d256}257 258declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)259 260define <vscale x 2 x i32> @umulo_nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {261; CHECK-LABEL: umulo_nxv2i32:262; CHECK: // %bb.0:263; CHECK-NEXT: and z1.d, z1.d, #0xffffffff264; CHECK-NEXT: and z0.d, z0.d, #0xffffffff265; CHECK-NEXT: ptrue p0.d266; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d267; CHECK-NEXT: lsr z1.d, z0.d, #32268; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0269; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0270; CHECK-NEXT: ret271 %a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)272 %b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0273 %c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1274 %d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b275 ret <vscale x 2 x i32> %d276}277 278declare { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)279 280define <vscale x 4 x i32> @umulo_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {281; CHECK-LABEL: umulo_nxv4i32:282; CHECK: // %bb.0:283; CHECK-NEXT: ptrue p0.s284; CHECK-NEXT: movprfx z2, z0285; CHECK-NEXT: umulh z2.s, p0/m, z2.s, z1.s286; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s287; CHECK-NEXT: cmpne p0.s, p0/z, z2.s, #0288; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0289; CHECK-NEXT: ret290 %a = call { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)291 %b = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 0292 %c = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 1293 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> %b294 ret <vscale x 4 x i32> %d295}296 297declare { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)298 299define <vscale x 8 x i32> @umulo_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {300; CHECK-LABEL: umulo_nxv8i32:301; CHECK: // %bb.0:302; CHECK-NEXT: ptrue p0.s303; CHECK-NEXT: movprfx z4, z1304; CHECK-NEXT: umulh z4.s, p0/m, z4.s, z3.s305; CHECK-NEXT: movprfx z5, z0306; CHECK-NEXT: umulh z5.s, p0/m, z5.s, z2.s307; CHECK-NEXT: mul z1.s, p0/m, z1.s, z3.s308; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s309; CHECK-NEXT: cmpne p1.s, p0/z, z4.s, #0310; CHECK-NEXT: cmpne p0.s, p0/z, z5.s, #0311; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0312; CHECK-NEXT: mov z1.s, p1/m, #0 // =0x0313; CHECK-NEXT: ret314 %a = call { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y)315 %b = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 0316 %c = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 1317 %d = select <vscale x 8 x i1> %c, <vscale x 8 x i32> zeroinitializer, <vscale x 8 x i32> %b318 ret <vscale x 8 x i32> %d319}320 321declare { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)322 323define <vscale x 16 x i32> @umulo_nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y) {324; CHECK-LABEL: umulo_nxv16i32:325; CHECK: // %bb.0:326; CHECK-NEXT: ptrue p0.s327; CHECK-NEXT: movprfx z24, z3328; CHECK-NEXT: umulh z24.s, p0/m, z24.s, z7.s329; CHECK-NEXT: movprfx z25, z0330; CHECK-NEXT: umulh z25.s, p0/m, z25.s, z4.s331; CHECK-NEXT: movprfx z26, z2332; CHECK-NEXT: umulh z26.s, p0/m, z26.s, z6.s333; CHECK-NEXT: movprfx z27, z1334; CHECK-NEXT: umulh z27.s, p0/m, z27.s, z5.s335; CHECK-NEXT: mul z3.s, p0/m, z3.s, z7.s336; CHECK-NEXT: mul z2.s, p0/m, z2.s, z6.s337; CHECK-NEXT: mul z1.s, p0/m, z1.s, z5.s338; CHECK-NEXT: mul z0.s, p0/m, z0.s, z4.s339; CHECK-NEXT: cmpne p1.s, p0/z, z25.s, #0340; CHECK-NEXT: cmpne p2.s, p0/z, z24.s, #0341; CHECK-NEXT: cmpne p3.s, p0/z, z26.s, #0342; CHECK-NEXT: cmpne p0.s, p0/z, z27.s, #0343; CHECK-NEXT: mov z0.s, p1/m, #0 // =0x0344; CHECK-NEXT: mov z2.s, p3/m, #0 // =0x0345; CHECK-NEXT: mov z3.s, p2/m, #0 // =0x0346; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0347; CHECK-NEXT: ret348 %a = call { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y)349 %b = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 0350 %c = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 1351 %d = select <vscale x 16 x i1> %c, <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i32> %b352 ret <vscale x 16 x i32> %d353}354 355declare { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)356 357define <vscale x 2 x i64> @umulo_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {358; CHECK-LABEL: umulo_nxv2i64:359; CHECK: // %bb.0:360; CHECK-NEXT: ptrue p0.d361; CHECK-NEXT: movprfx z2, z0362; CHECK-NEXT: umulh z2.d, p0/m, z2.d, z1.d363; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d364; CHECK-NEXT: cmpne p0.d, p0/z, z2.d, #0365; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0366; CHECK-NEXT: ret367 %a = call { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)368 %b = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 0369 %c = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 1370 %d = select <vscale x 2 x i1> %c, <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i64> %b371 ret <vscale x 2 x i64> %d372}373 374declare { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)375 376define <vscale x 4 x i64> @umulo_nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y) {377; CHECK-LABEL: umulo_nxv4i64:378; CHECK: // %bb.0:379; CHECK-NEXT: ptrue p0.d380; CHECK-NEXT: movprfx z4, z1381; CHECK-NEXT: umulh z4.d, p0/m, z4.d, z3.d382; CHECK-NEXT: movprfx z5, z0383; CHECK-NEXT: umulh z5.d, p0/m, z5.d, z2.d384; CHECK-NEXT: mul z1.d, p0/m, z1.d, z3.d385; CHECK-NEXT: mul z0.d, p0/m, z0.d, z2.d386; CHECK-NEXT: cmpne p1.d, p0/z, z4.d, #0387; CHECK-NEXT: cmpne p0.d, p0/z, z5.d, #0388; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0389; CHECK-NEXT: mov z1.d, p1/m, #0 // =0x0390; CHECK-NEXT: ret391 %a = call { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y)392 %b = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 0393 %c = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 1394 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> zeroinitializer, <vscale x 4 x i64> %b395 ret <vscale x 4 x i64> %d396}397 398declare { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)399 400define <vscale x 8 x i64> @umulo_nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {401; CHECK-LABEL: umulo_nxv8i64:402; CHECK: // %bb.0:403; CHECK-NEXT: ptrue p0.d404; CHECK-NEXT: movprfx z24, z3405; CHECK-NEXT: umulh z24.d, p0/m, z24.d, z7.d406; CHECK-NEXT: movprfx z25, z0407; CHECK-NEXT: umulh z25.d, p0/m, z25.d, z4.d408; CHECK-NEXT: movprfx z26, z2409; CHECK-NEXT: umulh z26.d, p0/m, z26.d, z6.d410; CHECK-NEXT: movprfx z27, z1411; CHECK-NEXT: umulh z27.d, p0/m, z27.d, z5.d412; CHECK-NEXT: mul z3.d, p0/m, z3.d, z7.d413; CHECK-NEXT: mul z2.d, p0/m, z2.d, z6.d414; CHECK-NEXT: mul z1.d, p0/m, z1.d, z5.d415; CHECK-NEXT: mul z0.d, p0/m, z0.d, z4.d416; CHECK-NEXT: cmpne p1.d, p0/z, z25.d, #0417; CHECK-NEXT: cmpne p2.d, p0/z, z24.d, #0418; CHECK-NEXT: cmpne p3.d, p0/z, z26.d, #0419; CHECK-NEXT: cmpne p0.d, p0/z, z27.d, #0420; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0421; CHECK-NEXT: mov z2.d, p3/m, #0 // =0x0422; CHECK-NEXT: mov z3.d, p2/m, #0 // =0x0423; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0424; CHECK-NEXT: ret425 %a = call { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y)426 %b = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 0427 %c = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 1428 %d = select <vscale x 8 x i1> %c, <vscale x 8 x i64> zeroinitializer, <vscale x 8 x i64> %b429 ret <vscale x 8 x i64> %d430}431