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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6;7; ABS (sve_int_un_pred_arit_0)8;9 10; Check movprfx is inserted when no passthru/predicate is present11define <vscale x 16 x i8> @abs_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {12; CHECK-LABEL: abs_i8:13; CHECK: // %bb.0:14; CHECK-NEXT: ptrue p0.b15; CHECK-NEXT: movprfx z0, z116; CHECK-NEXT: abs z0.b, p0/m, z1.b17; CHECK-NEXT: ret18 %ret = tail call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %b, i1 0)19 ret <vscale x 16 x i8> %ret20}21 22; Check movprfx is not inserted when dstReg == srcReg23define <vscale x 16 x i8> @abs_i8_dupreg(<vscale x 16 x i8> %a) #0 {24; CHECK-LABEL: abs_i8_dupreg:25; CHECK: // %bb.0:26; CHECK-NEXT: ptrue p0.b27; CHECK-NEXT: abs z0.b, p0/m, z0.b28; CHECK-NEXT: ret29 %ret = tail call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %a, i1 0)30 ret <vscale x 16 x i8> %ret31}32 33; Check movprfx is inserted when passthru is undef34define <vscale x 16 x i8> @abs_i8_undef(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {35; CHECK-LABEL: abs_i8_undef:36; CHECK: // %bb.0:37; CHECK-NEXT: ptrue p0.b38; CHECK-NEXT: movprfx z0, z139; CHECK-NEXT: abs z0.b, p0/m, z1.b40; CHECK-NEXT: ret41 %pg = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)42 %ret = tail call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b)43 ret <vscale x 16 x i8> %ret44}45 46; Check movprfx is inserted when predicate is all active, making the passthru dead47define <vscale x 16 x i8> @abs_i8_active(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {48; CHECK-LABEL: abs_i8_active:49; CHECK: // %bb.0:50; CHECK-NEXT: ptrue p0.b51; CHECK-NEXT: movprfx z0, z152; CHECK-NEXT: abs z0.b, p0/m, z1.b53; CHECK-NEXT: ret54 %pg = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)55 %ret = tail call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b)56 ret <vscale x 16 x i8> %ret57}58 59; Check movprfx is not inserted when predicate is not all active, making the passthru used60define <vscale x 16 x i8> @abs_i8_not_active(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {61; CHECK-LABEL: abs_i8_not_active:62; CHECK: // %bb.0:63; CHECK-NEXT: ptrue p0.d64; CHECK-NEXT: abs z0.b, p0/m, z1.b65; CHECK-NEXT: ret66 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)67 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)68 %ret = tail call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg.to, <vscale x 16 x i8> %b)69 ret <vscale x 16 x i8> %ret70}71 72define <vscale x 8 x i16> @abs_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {73; CHECK-LABEL: abs_i16:74; CHECK: // %bb.0:75; CHECK-NEXT: ptrue p0.h76; CHECK-NEXT: movprfx z0, z177; CHECK-NEXT: abs z0.h, p0/m, z1.h78; CHECK-NEXT: ret79 %ret = tail call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %b, i1 0)80 ret <vscale x 8 x i16> %ret81}82 83define <vscale x 8 x i16> @abs_i16_dupreg(<vscale x 8 x i16> %a) #0 {84; CHECK-LABEL: abs_i16_dupreg:85; CHECK: // %bb.0:86; CHECK-NEXT: ptrue p0.h87; CHECK-NEXT: abs z0.h, p0/m, z0.h88; CHECK-NEXT: ret89 %ret = tail call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %a, i1 0)90 ret <vscale x 8 x i16> %ret91}92 93define <vscale x 8 x i16> @abs_i16_undef(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {94; CHECK-LABEL: abs_i16_undef:95; CHECK: // %bb.0:96; CHECK-NEXT: ptrue p0.h97; CHECK-NEXT: movprfx z0, z198; CHECK-NEXT: abs z0.h, p0/m, z1.h99; CHECK-NEXT: ret100 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)101 %ret = tail call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b)102 ret <vscale x 8 x i16> %ret103}104 105define <vscale x 8 x i16> @abs_i16_active(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {106; CHECK-LABEL: abs_i16_active:107; CHECK: // %bb.0:108; CHECK-NEXT: ptrue p0.h109; CHECK-NEXT: movprfx z0, z1110; CHECK-NEXT: abs z0.h, p0/m, z1.h111; CHECK-NEXT: ret112 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)113 %ret = tail call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b)114 ret <vscale x 8 x i16> %ret115}116 117define <vscale x 8 x i16> @abs_i16_not_active(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {118; CHECK-LABEL: abs_i16_not_active:119; CHECK: // %bb.0:120; CHECK-NEXT: ptrue p0.d121; CHECK-NEXT: abs z0.h, p0/m, z1.h122; CHECK-NEXT: ret123 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)124 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)125 %pg.from = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg.to)126 %ret = tail call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg.from, <vscale x 8 x i16> %b)127 ret <vscale x 8 x i16> %ret128}129 130define <vscale x 4 x i32> @abs_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {131; CHECK-LABEL: abs_i32:132; CHECK: // %bb.0:133; CHECK-NEXT: ptrue p0.s134; CHECK-NEXT: movprfx z0, z1135; CHECK-NEXT: abs z0.s, p0/m, z1.s136; CHECK-NEXT: ret137 %ret = tail call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %b, i1 0)138 ret <vscale x 4 x i32> %ret139}140 141define <vscale x 4 x i32> @abs_i32_dupreg(<vscale x 4 x i32> %a) #0 {142; CHECK-LABEL: abs_i32_dupreg:143; CHECK: // %bb.0:144; CHECK-NEXT: ptrue p0.s145; CHECK-NEXT: abs z0.s, p0/m, z0.s146; CHECK-NEXT: ret147 %ret = tail call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %a, i1 0)148 ret <vscale x 4 x i32> %ret149}150 151define <vscale x 4 x i32> @abs_i32_undef(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {152; CHECK-LABEL: abs_i32_undef:153; CHECK: // %bb.0:154; CHECK-NEXT: ptrue p0.s155; CHECK-NEXT: movprfx z0, z1156; CHECK-NEXT: abs z0.s, p0/m, z1.s157; CHECK-NEXT: ret158 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)159 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b)160 ret <vscale x 4 x i32> %ret161}162 163define <vscale x 4 x i32> @abs_i32_active(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {164; CHECK-LABEL: abs_i32_active:165; CHECK: // %bb.0:166; CHECK-NEXT: ptrue p0.s167; CHECK-NEXT: movprfx z0, z1168; CHECK-NEXT: abs z0.s, p0/m, z1.s169; CHECK-NEXT: ret170 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)171 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b)172 ret <vscale x 4 x i32> %ret173}174 175define <vscale x 4 x i32> @abs_i32_not_active(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {176; CHECK-LABEL: abs_i32_not_active:177; CHECK: // %bb.0:178; CHECK-NEXT: ptrue p0.d179; CHECK-NEXT: abs z0.s, p0/m, z1.s180; CHECK-NEXT: ret181 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)182 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)183 %pg.from = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.to)184 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg.from, <vscale x 4 x i32> %b)185 ret <vscale x 4 x i32> %ret186}187 188define <vscale x 2 x i64> @abs_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {189; CHECK-LABEL: abs_i64:190; CHECK: // %bb.0:191; CHECK-NEXT: ptrue p0.d192; CHECK-NEXT: movprfx z0, z1193; CHECK-NEXT: abs z0.d, p0/m, z1.d194; CHECK-NEXT: ret195 %ret = tail call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %b, i1 0)196 ret <vscale x 2 x i64> %ret197}198 199define <vscale x 2 x i64> @abs_i64_dupreg(<vscale x 2 x i64> %a) #0 {200; CHECK-LABEL: abs_i64_dupreg:201; CHECK: // %bb.0:202; CHECK-NEXT: ptrue p0.d203; CHECK-NEXT: abs z0.d, p0/m, z0.d204; CHECK-NEXT: ret205 %ret = tail call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %a, i1 0)206 ret <vscale x 2 x i64> %ret207}208 209define <vscale x 2 x i64> @abs_i64_undef(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {210; CHECK-LABEL: abs_i64_undef:211; CHECK: // %bb.0:212; CHECK-NEXT: ptrue p0.d213; CHECK-NEXT: movprfx z0, z1214; CHECK-NEXT: abs z0.d, p0/m, z1.d215; CHECK-NEXT: ret216 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)217 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)218 ret <vscale x 2 x i64> %ret219}220 221define <vscale x 2 x i64> @abs_i64_active(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {222; CHECK-LABEL: abs_i64_active:223; CHECK: // %bb.0:224; CHECK-NEXT: ptrue p0.d225; CHECK-NEXT: movprfx z0, z1226; CHECK-NEXT: abs z0.d, p0/m, z1.d227; CHECK-NEXT: ret228 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)229 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)230 ret <vscale x 2 x i64> %ret231}232 233define <vscale x 2 x i64> @abs_i64_not_active(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %pg) #0 {234; CHECK-LABEL: abs_i64_not_active:235; CHECK: // %bb.0:236; CHECK-NEXT: abs z0.d, p0/m, z1.d237; CHECK-NEXT: ret238 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)239 ret <vscale x 2 x i64> %ret240}241 242;243; CLS (sve_int_un_pred_arit_1)244;245 246define <vscale x 16 x i8> @cls_i8_dupreg(<vscale x 16 x i8> %a) #0 {247; CHECK-LABEL: cls_i8_dupreg:248; CHECK: // %bb.0:249; CHECK-NEXT: ptrue p0.b250; CHECK-NEXT: cls z0.b, p0/m, z0.b251; CHECK-NEXT: ret252 %pg = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)253 %ret = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a)254 ret <vscale x 16 x i8> %ret255}256 257define <vscale x 16 x i8> @cls_i8_undef(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {258; CHECK-LABEL: cls_i8_undef:259; CHECK: // %bb.0:260; CHECK-NEXT: ptrue p0.b261; CHECK-NEXT: movprfx z0, z1262; CHECK-NEXT: cls z0.b, p0/m, z1.b263; CHECK-NEXT: ret264 %pg = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)265 %ret = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> poison, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b)266 ret <vscale x 16 x i8> %ret267}268 269define <vscale x 16 x i8> @cls_i8_active(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {270; CHECK-LABEL: cls_i8_active:271; CHECK: // %bb.0:272; CHECK-NEXT: ptrue p0.b273; CHECK-NEXT: movprfx z0, z1274; CHECK-NEXT: cls z0.b, p0/m, z1.b275; CHECK-NEXT: ret276 %pg = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)277 %ret = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b)278 ret <vscale x 16 x i8> %ret279}280 281define <vscale x 16 x i8> @cls_i8_not_active(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {282; CHECK-LABEL: cls_i8_not_active:283; CHECK: // %bb.0:284; CHECK-NEXT: ptrue p0.d285; CHECK-NEXT: cls z0.b, p0/m, z1.b286; CHECK-NEXT: ret287 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)288 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)289 %ret = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg.to, <vscale x 16 x i8> %b)290 ret <vscale x 16 x i8> %ret291}292 293define <vscale x 8 x i16> @cls_i16_dupreg(<vscale x 8 x i16> %a) #0 {294; CHECK-LABEL: cls_i16_dupreg:295; CHECK: // %bb.0:296; CHECK-NEXT: ptrue p0.h297; CHECK-NEXT: cls z0.h, p0/m, z0.h298; CHECK-NEXT: ret299 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)300 %ret = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a)301 ret <vscale x 8 x i16> %ret302}303 304define <vscale x 8 x i16> @cls_i16_undef(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {305; CHECK-LABEL: cls_i16_undef:306; CHECK: // %bb.0:307; CHECK-NEXT: ptrue p0.h308; CHECK-NEXT: movprfx z0, z1309; CHECK-NEXT: cls z0.h, p0/m, z1.h310; CHECK-NEXT: ret311 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)312 %ret = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b)313 ret <vscale x 8 x i16> %ret314}315 316define <vscale x 8 x i16> @cls_i16_active(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {317; CHECK-LABEL: cls_i16_active:318; CHECK: // %bb.0:319; CHECK-NEXT: ptrue p0.h320; CHECK-NEXT: movprfx z0, z1321; CHECK-NEXT: cls z0.h, p0/m, z1.h322; CHECK-NEXT: ret323 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)324 %ret = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b)325 ret <vscale x 8 x i16> %ret326}327 328define <vscale x 8 x i16> @cls_i16_not_active(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {329; CHECK-LABEL: cls_i16_not_active:330; CHECK: // %bb.0:331; CHECK-NEXT: ptrue p0.d332; CHECK-NEXT: cls z0.h, p0/m, z1.h333; CHECK-NEXT: ret334 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)335 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)336 %pg.from = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg.to)337 %ret = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg.from, <vscale x 8 x i16> %b)338 ret <vscale x 8 x i16> %ret339}340 341define <vscale x 4 x i32> @cls_i32_dupreg(<vscale x 4 x i32> %a) #0 {342; CHECK-LABEL: cls_i32_dupreg:343; CHECK: // %bb.0:344; CHECK-NEXT: ptrue p0.s345; CHECK-NEXT: cls z0.s, p0/m, z0.s346; CHECK-NEXT: ret347 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)348 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a)349 ret <vscale x 4 x i32> %ret350}351 352define <vscale x 4 x i32> @cls_i32_undef(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {353; CHECK-LABEL: cls_i32_undef:354; CHECK: // %bb.0:355; CHECK-NEXT: ptrue p0.s356; CHECK-NEXT: movprfx z0, z1357; CHECK-NEXT: cls z0.s, p0/m, z1.s358; CHECK-NEXT: ret359 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)360 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b)361 ret <vscale x 4 x i32> %ret362}363 364define <vscale x 4 x i32> @cls_i32_active(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {365; CHECK-LABEL: cls_i32_active:366; CHECK: // %bb.0:367; CHECK-NEXT: ptrue p0.s368; CHECK-NEXT: movprfx z0, z1369; CHECK-NEXT: cls z0.s, p0/m, z1.s370; CHECK-NEXT: ret371 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)372 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b)373 ret <vscale x 4 x i32> %ret374}375 376define <vscale x 4 x i32> @cls_i32_not_active(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {377; CHECK-LABEL: cls_i32_not_active:378; CHECK: // %bb.0:379; CHECK-NEXT: ptrue p0.d380; CHECK-NEXT: cls z0.s, p0/m, z1.s381; CHECK-NEXT: ret382 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)383 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)384 %pg.from = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.to)385 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg.from, <vscale x 4 x i32> %b)386 ret <vscale x 4 x i32> %ret387}388 389define <vscale x 2 x i64> @cls_i64_dupreg(<vscale x 2 x i64> %a) #0 {390; CHECK-LABEL: cls_i64_dupreg:391; CHECK: // %bb.0:392; CHECK-NEXT: ptrue p0.d393; CHECK-NEXT: cls z0.d, p0/m, z0.d394; CHECK-NEXT: ret395 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)396 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)397 ret <vscale x 2 x i64> %ret398}399 400define <vscale x 2 x i64> @cls_i64_undef(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {401; CHECK-LABEL: cls_i64_undef:402; CHECK: // %bb.0:403; CHECK-NEXT: ptrue p0.d404; CHECK-NEXT: movprfx z0, z1405; CHECK-NEXT: cls z0.d, p0/m, z1.d406; CHECK-NEXT: ret407 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)408 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)409 ret <vscale x 2 x i64> %ret410}411 412define <vscale x 2 x i64> @cls_i64_active(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {413; CHECK-LABEL: cls_i64_active:414; CHECK: // %bb.0:415; CHECK-NEXT: ptrue p0.d416; CHECK-NEXT: movprfx z0, z1417; CHECK-NEXT: cls z0.d, p0/m, z1.d418; CHECK-NEXT: ret419 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)420 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)421 ret <vscale x 2 x i64> %ret422}423 424define <vscale x 2 x i64> @cls_i64_not_active(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %pg) #0 {425; CHECK-LABEL: cls_i64_not_active:426; CHECK: // %bb.0:427; CHECK-NEXT: cls z0.d, p0/m, z1.d428; CHECK-NEXT: ret429 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)430 ret <vscale x 2 x i64> %ret431}432 433;434; FABS (sve_int_un_pred_arit_1_fp)435;436 437define <vscale x 8 x half> @fabs_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {438; CHECK-LABEL: fabs_f16:439; CHECK: // %bb.0:440; CHECK-NEXT: ptrue p0.h441; CHECK-NEXT: movprfx z0, z1442; CHECK-NEXT: fabs z0.h, p0/m, z1.h443; CHECK-NEXT: ret444 %ret = tail call <vscale x 8 x half> @llvm.fabs.nxv8f16(<vscale x 8 x half> %b)445 ret <vscale x 8 x half> %ret446}447 448define <vscale x 8 x half> @fabs_f16_dupreg(<vscale x 8 x half> %a) #0 {449; CHECK-LABEL: fabs_f16_dupreg:450; CHECK: // %bb.0:451; CHECK-NEXT: ptrue p0.h452; CHECK-NEXT: fabs z0.h, p0/m, z0.h453; CHECK-NEXT: ret454 %ret = tail call <vscale x 8 x half> @llvm.fabs.nxv8f16(<vscale x 8 x half> %a)455 ret <vscale x 8 x half> %ret456}457 458define <vscale x 8 x half> @fabs_f16_undef(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {459; CHECK-LABEL: fabs_f16_undef:460; CHECK: // %bb.0:461; CHECK-NEXT: ptrue p0.h462; CHECK-NEXT: movprfx z0, z1463; CHECK-NEXT: fabs z0.h, p0/m, z1.h464; CHECK-NEXT: ret465 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)466 %ret = tail call <vscale x 8 x half> @llvm.aarch64.sve.fabs.nxv8f16(<vscale x 8 x half> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %b)467 ret <vscale x 8 x half> %ret468}469 470define <vscale x 8 x half> @fabs_f16_active(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {471; CHECK-LABEL: fabs_f16_active:472; CHECK: // %bb.0:473; CHECK-NEXT: ptrue p0.h474; CHECK-NEXT: movprfx z0, z1475; CHECK-NEXT: fabs z0.h, p0/m, z1.h476; CHECK-NEXT: ret477 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)478 %ret = tail call <vscale x 8 x half> @llvm.aarch64.sve.fabs.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x i1> %pg, <vscale x 8 x half> %b)479 ret <vscale x 8 x half> %ret480}481 482define <vscale x 8 x half> @fabs_f16_not_active(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {483; CHECK-LABEL: fabs_f16_not_active:484; CHECK: // %bb.0:485; CHECK-NEXT: ptrue p0.d486; CHECK-NEXT: fabs z0.h, p0/m, z1.h487; CHECK-NEXT: ret488 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)489 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)490 %pg.from = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg.to)491 %ret = tail call <vscale x 8 x half> @llvm.aarch64.sve.fabs.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x i1> %pg.from, <vscale x 8 x half> %b)492 ret <vscale x 8 x half> %ret493}494 495define <vscale x 4 x float> @fabs_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {496; CHECK-LABEL: fabs_f32:497; CHECK: // %bb.0:498; CHECK-NEXT: ptrue p0.s499; CHECK-NEXT: movprfx z0, z1500; CHECK-NEXT: fabs z0.s, p0/m, z1.s501; CHECK-NEXT: ret502 %ret = tail call <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float> %b)503 ret <vscale x 4 x float> %ret504}505 506define <vscale x 4 x float> @fabs_f32_dupreg(<vscale x 4 x float> %a) #0 {507; CHECK-LABEL: fabs_f32_dupreg:508; CHECK: // %bb.0:509; CHECK-NEXT: ptrue p0.s510; CHECK-NEXT: fabs z0.s, p0/m, z0.s511; CHECK-NEXT: ret512 %ret = tail call <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float> %a)513 ret <vscale x 4 x float> %ret514}515 516define <vscale x 4 x float> @fabs_f32_undef(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {517; CHECK-LABEL: fabs_f32_undef:518; CHECK: // %bb.0:519; CHECK-NEXT: ptrue p0.s520; CHECK-NEXT: movprfx z0, z1521; CHECK-NEXT: fabs z0.s, p0/m, z1.s522; CHECK-NEXT: ret523 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)524 %ret = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b)525 ret <vscale x 4 x float> %ret526}527 528define <vscale x 4 x float> @fabs_f32_active(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {529; CHECK-LABEL: fabs_f32_active:530; CHECK: // %bb.0:531; CHECK-NEXT: ptrue p0.s532; CHECK-NEXT: movprfx z0, z1533; CHECK-NEXT: fabs z0.s, p0/m, z1.s534; CHECK-NEXT: ret535 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)536 %ret = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b)537 ret <vscale x 4 x float> %ret538}539 540define <vscale x 4 x float> @fabs_f32_not_active(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {541; CHECK-LABEL: fabs_f32_not_active:542; CHECK: // %bb.0:543; CHECK-NEXT: ptrue p0.d544; CHECK-NEXT: fabs z0.s, p0/m, z1.s545; CHECK-NEXT: ret546 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)547 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)548 %pg.from = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.to)549 %ret = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> %pg.from, <vscale x 4 x float> %b)550 ret <vscale x 4 x float> %ret551}552 553define <vscale x 2 x double> @fabs_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {554; CHECK-LABEL: fabs_f64:555; CHECK: // %bb.0:556; CHECK-NEXT: ptrue p0.d557; CHECK-NEXT: movprfx z0, z1558; CHECK-NEXT: fabs z0.d, p0/m, z1.d559; CHECK-NEXT: ret560 %ret = tail call <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double> %b)561 ret <vscale x 2 x double> %ret562}563 564define <vscale x 2 x double> @fabs_f64_dupreg(<vscale x 2 x double> %a) #0 {565; CHECK-LABEL: fabs_f64_dupreg:566; CHECK: // %bb.0:567; CHECK-NEXT: ptrue p0.d568; CHECK-NEXT: fabs z0.d, p0/m, z0.d569; CHECK-NEXT: ret570 %ret = tail call <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double> %a)571 ret <vscale x 2 x double> %ret572}573 574define <vscale x 2 x double> @fabs_f64_undef(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {575; CHECK-LABEL: fabs_f64_undef:576; CHECK: // %bb.0:577; CHECK-NEXT: ptrue p0.d578; CHECK-NEXT: movprfx z0, z1579; CHECK-NEXT: fabs z0.d, p0/m, z1.d580; CHECK-NEXT: ret581 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)582 %ret = tail call <vscale x 2 x double> @llvm.aarch64.sve.fabs.nxv2f64(<vscale x 2 x double> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b)583 ret <vscale x 2 x double> %ret584}585 586define <vscale x 2 x double> @fabs_f64_active(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {587; CHECK-LABEL: fabs_f64_active:588; CHECK: // %bb.0:589; CHECK-NEXT: ptrue p0.d590; CHECK-NEXT: movprfx z0, z1591; CHECK-NEXT: fabs z0.d, p0/m, z1.d592; CHECK-NEXT: ret593 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)594 %ret = tail call <vscale x 2 x double> @llvm.aarch64.sve.fabs.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b)595 ret <vscale x 2 x double> %ret596}597 598define <vscale x 2 x double> @fabs_f64_not_active(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x i1> %pg) #0 {599; CHECK-LABEL: fabs_f64_not_active:600; CHECK: // %bb.0:601; CHECK-NEXT: fabs z0.d, p0/m, z1.d602; CHECK-NEXT: ret603 %ret = tail call <vscale x 2 x double> @llvm.aarch64.sve.fabs.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b)604 ret <vscale x 2 x double> %ret605}606 607;608; FSQRT (sve_fp_2op_p_zd_HSD)609;610 611define <vscale x 8 x half> @fsqrt_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {612; CHECK-LABEL: fsqrt_f16:613; CHECK: // %bb.0:614; CHECK-NEXT: ptrue p0.h615; CHECK-NEXT: movprfx z0, z1616; CHECK-NEXT: fsqrt z0.h, p0/m, z1.h617; CHECK-NEXT: ret618 %ret = tail call <vscale x 8 x half> @llvm.sqrt.nxv8f16(<vscale x 8 x half> %b)619 ret <vscale x 8 x half> %ret620}621 622define <vscale x 8 x half> @fsqrt_f16_dupreg(<vscale x 8 x half> %a) #0 {623; CHECK-LABEL: fsqrt_f16_dupreg:624; CHECK: // %bb.0:625; CHECK-NEXT: ptrue p0.h626; CHECK-NEXT: fsqrt z0.h, p0/m, z0.h627; CHECK-NEXT: ret628 %ret = tail call <vscale x 8 x half> @llvm.sqrt.nxv8f16(<vscale x 8 x half> %a)629 ret <vscale x 8 x half> %ret630}631 632define <vscale x 8 x half> @fsqrt_f16_undef(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {633; CHECK-LABEL: fsqrt_f16_undef:634; CHECK: // %bb.0:635; CHECK-NEXT: ptrue p0.h636; CHECK-NEXT: movprfx z0, z1637; CHECK-NEXT: fsqrt z0.h, p0/m, z1.h638; CHECK-NEXT: ret639 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)640 %ret = tail call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %b)641 ret <vscale x 8 x half> %ret642}643 644define <vscale x 8 x half> @fsqrt_f16_active(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {645; CHECK-LABEL: fsqrt_f16_active:646; CHECK: // %bb.0:647; CHECK-NEXT: ptrue p0.h648; CHECK-NEXT: movprfx z0, z1649; CHECK-NEXT: fsqrt z0.h, p0/m, z1.h650; CHECK-NEXT: ret651 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)652 %ret = tail call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x i1> %pg, <vscale x 8 x half> %b)653 ret <vscale x 8 x half> %ret654}655 656define <vscale x 8 x half> @fsqrt_f16_not_active(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {657; CHECK-LABEL: fsqrt_f16_not_active:658; CHECK: // %bb.0:659; CHECK-NEXT: ptrue p0.d660; CHECK-NEXT: fsqrt z0.h, p0/m, z1.h661; CHECK-NEXT: ret662 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)663 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)664 %pg.from = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg.to)665 %ret = tail call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x i1> %pg.from, <vscale x 8 x half> %b)666 ret <vscale x 8 x half> %ret667}668 669define <vscale x 4 x float> @fsqrt_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {670; CHECK-LABEL: fsqrt_f32:671; CHECK: // %bb.0:672; CHECK-NEXT: ptrue p0.s673; CHECK-NEXT: movprfx z0, z1674; CHECK-NEXT: fsqrt z0.s, p0/m, z1.s675; CHECK-NEXT: ret676 %ret = tail call <vscale x 4 x float> @llvm.sqrt.nxv4f32(<vscale x 4 x float> %b)677 ret <vscale x 4 x float> %ret678}679 680define <vscale x 4 x float> @fsqrt_f32_dupreg(<vscale x 4 x float> %a) #0 {681; CHECK-LABEL: fsqrt_f32_dupreg:682; CHECK: // %bb.0:683; CHECK-NEXT: ptrue p0.s684; CHECK-NEXT: fsqrt z0.s, p0/m, z0.s685; CHECK-NEXT: ret686 %ret = tail call <vscale x 4 x float> @llvm.sqrt.nxv4f32(<vscale x 4 x float> %a)687 ret <vscale x 4 x float> %ret688}689 690define <vscale x 4 x float> @fsqrt_f32_undef(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {691; CHECK-LABEL: fsqrt_f32_undef:692; CHECK: // %bb.0:693; CHECK-NEXT: ptrue p0.s694; CHECK-NEXT: movprfx z0, z1695; CHECK-NEXT: fsqrt z0.s, p0/m, z1.s696; CHECK-NEXT: ret697 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)698 %ret = tail call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b)699 ret <vscale x 4 x float> %ret700}701 702define <vscale x 4 x float> @fsqrt_f32_active(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {703; CHECK-LABEL: fsqrt_f32_active:704; CHECK: // %bb.0:705; CHECK-NEXT: ptrue p0.s706; CHECK-NEXT: movprfx z0, z1707; CHECK-NEXT: fsqrt z0.s, p0/m, z1.s708; CHECK-NEXT: ret709 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)710 %ret = tail call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b)711 ret <vscale x 4 x float> %ret712}713 714define <vscale x 4 x float> @fsqrt_f32_not_active(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {715; CHECK-LABEL: fsqrt_f32_not_active:716; CHECK: // %bb.0:717; CHECK-NEXT: ptrue p0.d718; CHECK-NEXT: fsqrt z0.s, p0/m, z1.s719; CHECK-NEXT: ret720 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)721 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)722 %pg.from = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.to)723 %ret = tail call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> %pg.from, <vscale x 4 x float> %b)724 ret <vscale x 4 x float> %ret725}726 727define <vscale x 2 x double> @fsqrt_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {728; CHECK-LABEL: fsqrt_f64:729; CHECK: // %bb.0:730; CHECK-NEXT: ptrue p0.d731; CHECK-NEXT: movprfx z0, z1732; CHECK-NEXT: fsqrt z0.d, p0/m, z1.d733; CHECK-NEXT: ret734 %ret = tail call <vscale x 2 x double> @llvm.sqrt.nxv2f64(<vscale x 2 x double> %b)735 ret <vscale x 2 x double> %ret736}737 738define <vscale x 2 x double> @fsqrt_f64_dupreg(<vscale x 2 x double> %a) #0 {739; CHECK-LABEL: fsqrt_f64_dupreg:740; CHECK: // %bb.0:741; CHECK-NEXT: ptrue p0.d742; CHECK-NEXT: fsqrt z0.d, p0/m, z0.d743; CHECK-NEXT: ret744 %ret = tail call <vscale x 2 x double> @llvm.sqrt.nxv2f64(<vscale x 2 x double> %a)745 ret <vscale x 2 x double> %ret746}747 748define <vscale x 2 x double> @fsqrt_f64_undef(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {749; CHECK-LABEL: fsqrt_f64_undef:750; CHECK: // %bb.0:751; CHECK-NEXT: ptrue p0.d752; CHECK-NEXT: movprfx z0, z1753; CHECK-NEXT: fsqrt z0.d, p0/m, z1.d754; CHECK-NEXT: ret755 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)756 %ret = tail call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b)757 ret <vscale x 2 x double> %ret758}759 760define <vscale x 2 x double> @fsqrt_f64_active(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {761; CHECK-LABEL: fsqrt_f64_active:762; CHECK: // %bb.0:763; CHECK-NEXT: ptrue p0.d764; CHECK-NEXT: movprfx z0, z1765; CHECK-NEXT: fsqrt z0.d, p0/m, z1.d766; CHECK-NEXT: ret767 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)768 %ret = tail call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b)769 ret <vscale x 2 x double> %ret770}771 772define <vscale x 2 x double> @fsqrt_f64_not_active(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x i1> %pg) #0 {773; CHECK-LABEL: fsqrt_f64_not_active:774; CHECK: // %bb.0:775; CHECK-NEXT: fsqrt z0.d, p0/m, z1.d776; CHECK-NEXT: ret777 %ret = tail call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b)778 ret <vscale x 2 x double> %ret779}780 781;782; SXTB (sve_int_un_pred_arit_0_h)783;784 785define <vscale x 8 x i16> @sxtb_i16(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 {786; CHECK-LABEL: sxtb_i16:787; CHECK: // %bb.0:788; CHECK-NEXT: ptrue p0.h789; CHECK-NEXT: movprfx z0, z1790; CHECK-NEXT: sxtb z0.h, p0/m, z1.h791; CHECK-NEXT: ret792 %ret = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>793 ret <vscale x 8 x i16> %ret794}795 796define <vscale x 8 x i16> @sxtb_i16_dupreg(<vscale x 8 x i8> %a) #0 {797; CHECK-LABEL: sxtb_i16_dupreg:798; CHECK: // %bb.0:799; CHECK-NEXT: ptrue p0.h800; CHECK-NEXT: sxtb z0.h, p0/m, z0.h801; CHECK-NEXT: ret802 %ret = sext <vscale x 8 x i8> %a to <vscale x 8 x i16>803 ret <vscale x 8 x i16> %ret804}805 806define <vscale x 8 x i16> @sxtb_i16_undef(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {807; CHECK-LABEL: sxtb_i16_undef:808; CHECK: // %bb.0:809; CHECK-NEXT: ptrue p0.h810; CHECK-NEXT: movprfx z0, z1811; CHECK-NEXT: sxtb z0.h, p0/m, z1.h812; CHECK-NEXT: ret813 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)814 %ret = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b)815 ret <vscale x 8 x i16> %ret816}817 818define <vscale x 8 x i16> @sxtb_i16_active(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {819; CHECK-LABEL: sxtb_i16_active:820; CHECK: // %bb.0:821; CHECK-NEXT: ptrue p0.h822; CHECK-NEXT: movprfx z0, z1823; CHECK-NEXT: sxtb z0.h, p0/m, z1.h824; CHECK-NEXT: ret825 %pg = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)826 %ret = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b)827 ret <vscale x 8 x i16> %ret828}829 830define <vscale x 8 x i16> @sxtb_i16_not_active(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {831; CHECK-LABEL: sxtb_i16_not_active:832; CHECK: // %bb.0:833; CHECK-NEXT: ptrue p0.d834; CHECK-NEXT: sxtb z0.h, p0/m, z1.h835; CHECK-NEXT: ret836 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)837 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)838 %pg.from = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg.to)839 %ret = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg.from, <vscale x 8 x i16> %b)840 ret <vscale x 8 x i16> %ret841}842 843define <vscale x 4 x i32> @sxtb_i32(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 {844; CHECK-LABEL: sxtb_i32:845; CHECK: // %bb.0:846; CHECK-NEXT: ptrue p0.s847; CHECK-NEXT: movprfx z0, z1848; CHECK-NEXT: sxtb z0.s, p0/m, z1.s849; CHECK-NEXT: ret850 %ret = sext <vscale x 4 x i8> %b to <vscale x 4 x i32>851 ret <vscale x 4 x i32> %ret852}853 854define <vscale x 4 x i32> @sxtb_i32_dupreg(<vscale x 4 x i8> %a) #0 {855; CHECK-LABEL: sxtb_i32_dupreg:856; CHECK: // %bb.0:857; CHECK-NEXT: ptrue p0.s858; CHECK-NEXT: sxtb z0.s, p0/m, z0.s859; CHECK-NEXT: ret860 %ret = sext <vscale x 4 x i8> %a to <vscale x 4 x i32>861 ret <vscale x 4 x i32> %ret862}863 864define <vscale x 4 x i32> @sxtb_i32_undef(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {865; CHECK-LABEL: sxtb_i32_undef:866; CHECK: // %bb.0:867; CHECK-NEXT: ptrue p0.s868; CHECK-NEXT: movprfx z0, z1869; CHECK-NEXT: sxtb z0.s, p0/m, z1.s870; CHECK-NEXT: ret871 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)872 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b)873 ret <vscale x 4 x i32> %ret874}875 876define <vscale x 4 x i32> @sxtb_i32_active(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {877; CHECK-LABEL: sxtb_i32_active:878; CHECK: // %bb.0:879; CHECK-NEXT: ptrue p0.s880; CHECK-NEXT: movprfx z0, z1881; CHECK-NEXT: sxtb z0.s, p0/m, z1.s882; CHECK-NEXT: ret883 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)884 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b)885 ret <vscale x 4 x i32> %ret886}887 888define <vscale x 4 x i32> @sxtb_i32_not_active(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {889; CHECK-LABEL: sxtb_i32_not_active:890; CHECK: // %bb.0:891; CHECK-NEXT: ptrue p0.d892; CHECK-NEXT: sxtb z0.s, p0/m, z1.s893; CHECK-NEXT: ret894 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)895 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)896 %pg.from = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.to)897 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg.from, <vscale x 4 x i32> %b)898 ret <vscale x 4 x i32> %ret899}900 901define <vscale x 2 x i64> @sxtb_i64(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {902; CHECK-LABEL: sxtb_i64:903; CHECK: // %bb.0:904; CHECK-NEXT: ptrue p0.d905; CHECK-NEXT: movprfx z0, z1906; CHECK-NEXT: sxtb z0.d, p0/m, z1.d907; CHECK-NEXT: ret908 %ret = sext <vscale x 2 x i8> %b to <vscale x 2 x i64>909 ret <vscale x 2 x i64> %ret910}911 912define <vscale x 2 x i64> @sxtb_i64_dupreg(<vscale x 2 x i8> %a) #0 {913; CHECK-LABEL: sxtb_i64_dupreg:914; CHECK: // %bb.0:915; CHECK-NEXT: ptrue p0.d916; CHECK-NEXT: sxtb z0.d, p0/m, z0.d917; CHECK-NEXT: ret918 %ret = sext <vscale x 2 x i8> %a to <vscale x 2 x i64>919 ret <vscale x 2 x i64> %ret920}921 922define <vscale x 2 x i64> @sxtb_i64_undef(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {923; CHECK-LABEL: sxtb_i64_undef:924; CHECK: // %bb.0:925; CHECK-NEXT: ptrue p0.d926; CHECK-NEXT: movprfx z0, z1927; CHECK-NEXT: sxtb z0.d, p0/m, z1.d928; CHECK-NEXT: ret929 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)930 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)931 ret <vscale x 2 x i64> %ret932}933 934define <vscale x 2 x i64> @sxtb_i64_active(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {935; CHECK-LABEL: sxtb_i64_active:936; CHECK: // %bb.0:937; CHECK-NEXT: ptrue p0.d938; CHECK-NEXT: movprfx z0, z1939; CHECK-NEXT: sxtb z0.d, p0/m, z1.d940; CHECK-NEXT: ret941 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)942 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)943 ret <vscale x 2 x i64> %ret944}945 946define <vscale x 2 x i64> @sxtb_i64_not_active(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %pg) #0 {947; CHECK-LABEL: sxtb_i64_not_active:948; CHECK: // %bb.0:949; CHECK-NEXT: sxtb z0.d, p0/m, z1.d950; CHECK-NEXT: ret951 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)952 ret <vscale x 2 x i64> %ret953}954 955;956; SXTH (sve_int_un_pred_arit_0_w)957;958 959define <vscale x 4 x i32> @sxth_i32(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 {960; CHECK-LABEL: sxth_i32:961; CHECK: // %bb.0:962; CHECK-NEXT: ptrue p0.s963; CHECK-NEXT: movprfx z0, z1964; CHECK-NEXT: sxth z0.s, p0/m, z1.s965; CHECK-NEXT: ret966 %ret = sext <vscale x 4 x i16> %b to <vscale x 4 x i32>967 ret <vscale x 4 x i32> %ret968}969 970define <vscale x 4 x i32> @sxth_i32_dupreg(<vscale x 4 x i16> %a) #0 {971; CHECK-LABEL: sxth_i32_dupreg:972; CHECK: // %bb.0:973; CHECK-NEXT: ptrue p0.s974; CHECK-NEXT: sxth z0.s, p0/m, z0.s975; CHECK-NEXT: ret976 %ret = sext <vscale x 4 x i16> %a to <vscale x 4 x i32>977 ret <vscale x 4 x i32> %ret978}979 980define <vscale x 4 x i32> @sxth_i32_undef(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {981; CHECK-LABEL: sxth_i32_undef:982; CHECK: // %bb.0:983; CHECK-NEXT: ptrue p0.s984; CHECK-NEXT: movprfx z0, z1985; CHECK-NEXT: sxth z0.s, p0/m, z1.s986; CHECK-NEXT: ret987 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)988 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b)989 ret <vscale x 4 x i32> %ret990}991 992define <vscale x 4 x i32> @sxth_i32_active(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {993; CHECK-LABEL: sxth_i32_active:994; CHECK: // %bb.0:995; CHECK-NEXT: ptrue p0.s996; CHECK-NEXT: movprfx z0, z1997; CHECK-NEXT: sxth z0.s, p0/m, z1.s998; CHECK-NEXT: ret999 %pg = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)1000 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b)1001 ret <vscale x 4 x i32> %ret1002}1003 1004define <vscale x 4 x i32> @sxth_i32_not_active(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1005; CHECK-LABEL: sxth_i32_not_active:1006; CHECK: // %bb.0:1007; CHECK-NEXT: ptrue p0.d1008; CHECK-NEXT: sxth z0.s, p0/m, z1.s1009; CHECK-NEXT: ret1010 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)1011 %pg.to = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg)1012 %pg.from = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.to)1013 %ret = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg.from, <vscale x 4 x i32> %b)1014 ret <vscale x 4 x i32> %ret1015}1016 1017define <vscale x 2 x i64> @sxth_i64(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 {1018; CHECK-LABEL: sxth_i64:1019; CHECK: // %bb.0:1020; CHECK-NEXT: ptrue p0.d1021; CHECK-NEXT: movprfx z0, z11022; CHECK-NEXT: sxth z0.d, p0/m, z1.d1023; CHECK-NEXT: ret1024 %ret = sext <vscale x 2 x i16> %b to <vscale x 2 x i64>1025 ret <vscale x 2 x i64> %ret1026}1027 1028define <vscale x 2 x i64> @sxth_i64_dupreg(<vscale x 2 x i16> %a) #0 {1029; CHECK-LABEL: sxth_i64_dupreg:1030; CHECK: // %bb.0:1031; CHECK-NEXT: ptrue p0.d1032; CHECK-NEXT: sxth z0.d, p0/m, z0.d1033; CHECK-NEXT: ret1034 %ret = sext <vscale x 2 x i16> %a to <vscale x 2 x i64>1035 ret <vscale x 2 x i64> %ret1036}1037 1038define <vscale x 2 x i64> @sxth_i64_undef(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {1039; CHECK-LABEL: sxth_i64_undef:1040; CHECK: // %bb.0:1041; CHECK-NEXT: ptrue p0.d1042; CHECK-NEXT: movprfx z0, z11043; CHECK-NEXT: sxth z0.d, p0/m, z1.d1044; CHECK-NEXT: ret1045 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)1046 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)1047 ret <vscale x 2 x i64> %ret1048}1049 1050define <vscale x 2 x i64> @sxth_i64_active(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {1051; CHECK-LABEL: sxth_i64_active:1052; CHECK: // %bb.0:1053; CHECK-NEXT: ptrue p0.d1054; CHECK-NEXT: movprfx z0, z11055; CHECK-NEXT: sxth z0.d, p0/m, z1.d1056; CHECK-NEXT: ret1057 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)1058 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)1059 ret <vscale x 2 x i64> %ret1060}1061 1062define <vscale x 2 x i64> @sxth_i64_not_active(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %pg) #0 {1063; CHECK-LABEL: sxth_i64_not_active:1064; CHECK: // %bb.0:1065; CHECK-NEXT: sxth z0.d, p0/m, z1.d1066; CHECK-NEXT: ret1067 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)1068 ret <vscale x 2 x i64> %ret1069}1070 1071;1072; SXTW (sve_int_un_pred_arit_0_d)1073;1074 1075define <vscale x 2 x i64> @sxtw_i64(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {1076; CHECK-LABEL: sxtw_i64:1077; CHECK: // %bb.0:1078; CHECK-NEXT: ptrue p0.d1079; CHECK-NEXT: movprfx z0, z11080; CHECK-NEXT: sxtw z0.d, p0/m, z1.d1081; CHECK-NEXT: ret1082 %ret = sext <vscale x 2 x i32> %b to <vscale x 2 x i64>1083 ret <vscale x 2 x i64> %ret1084}1085 1086define <vscale x 2 x i64> @sxtw_i64_dupreg(<vscale x 2 x i32> %a) #0 {1087; CHECK-LABEL: sxtw_i64_dupreg:1088; CHECK: // %bb.0:1089; CHECK-NEXT: ptrue p0.d1090; CHECK-NEXT: sxtw z0.d, p0/m, z0.d1091; CHECK-NEXT: ret1092 %ret = sext <vscale x 2 x i32> %a to <vscale x 2 x i64>1093 ret <vscale x 2 x i64> %ret1094}1095 1096define <vscale x 2 x i64> @sxtw_i64_undef(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {1097; CHECK-LABEL: sxtw_i64_undef:1098; CHECK: // %bb.0:1099; CHECK-NEXT: ptrue p0.d1100; CHECK-NEXT: movprfx z0, z11101; CHECK-NEXT: sxtw z0.d, p0/m, z1.d1102; CHECK-NEXT: ret1103 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)1104 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)1105 ret <vscale x 2 x i64> %ret1106}1107 1108define <vscale x 2 x i64> @sxtw_i64_active(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {1109; CHECK-LABEL: sxtw_i64_active:1110; CHECK: // %bb.0:1111; CHECK-NEXT: ptrue p0.d1112; CHECK-NEXT: movprfx z0, z11113; CHECK-NEXT: sxtw z0.d, p0/m, z1.d1114; CHECK-NEXT: ret1115 %pg = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)1116 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)1117 ret <vscale x 2 x i64> %ret1118}1119 1120define <vscale x 2 x i64> @sxtw_i64_not_active(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %pg) #0 {1121; CHECK-LABEL: sxtw_i64_not_active:1122; CHECK: // %bb.0:1123; CHECK-NEXT: sxtw z0.d, p0/m, z1.d1124; CHECK-NEXT: ret1125 %ret = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b)1126 ret <vscale x 2 x i64> %ret1127}1128 1129declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)1130declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)1131declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)1132declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)1133 1134declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>)1135declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)1136declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>)1137 1138declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>)1139declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)1140declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)1141 1142declare <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)1143declare <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)1144declare <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)1145declare <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)1146 1147declare <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8>, i1)1148declare <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16>, i1)1149declare <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32>, i1)1150declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)1151 1152declare <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)1153declare <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)1154declare <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)1155declare <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)1156 1157declare <vscale x 8 x half> @llvm.aarch64.sve.fabs.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>)1158declare <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)1159declare <vscale x 2 x double> @llvm.aarch64.sve.fabs.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>)1160 1161declare <vscale x 8 x half> @llvm.fabs.nxv8f16(<vscale x 8 x half>)1162declare <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float>)1163declare <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double>)1164 1165declare <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>)1166declare <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)1167declare <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>)1168 1169declare <vscale x 8 x half> @llvm.sqrt.nxv8f16(<vscale x 8 x half>)1170declare <vscale x 4 x float> @llvm.sqrt.nxv4f32(<vscale x 4 x float>)1171declare <vscale x 2 x double> @llvm.sqrt.nxv2f64(<vscale x 2 x double>)1172 1173declare <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)1174declare <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)1175declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)1176 1177declare <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)1178declare <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)1179 1180declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)1181 1182attributes #0 = { nounwind "target-features"="+sve" }1183