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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; Check that we don't try and merge uunpklo/uzp1 with a load or store if we7; would end up creating a predicate that would be too large for the max VL.8 9; UUNPKLO + Load10 11define <vscale x 8 x i16> @uunpklo_i8_valid(ptr %b) #0 {12; CHECK-LABEL: uunpklo_i8_valid:13; CHECK: // %bb.0:14; CHECK-NEXT: ptrue p0.h, vl6415; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]16; CHECK-NEXT: ret17 %mask = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)18 %load = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8(ptr %b, i32 2, <vscale x 16 x i1> %mask, <vscale x 16 x i8> poison)19 %uzp = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8> %load)20 ret <vscale x 8 x i16> %uzp21}22 23define <vscale x 8 x i16> @uunpklo_i8_invalid(ptr %b) #0 {24; CHECK-LABEL: uunpklo_i8_invalid:25; CHECK: // %bb.0:26; CHECK-NEXT: ptrue p0.b, vl12827; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]28; CHECK-NEXT: uunpklo z0.h, z0.b29; CHECK-NEXT: ret30 %mask = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 12)31 %load = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8(ptr %b, i32 2, <vscale x 16 x i1> %mask, <vscale x 16 x i8> poison)32 %uzp = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8> %load)33 ret <vscale x 8 x i16> %uzp34}35 36define <vscale x 4 x i32> @uunpklo_i16_valid(ptr %b) #0 {37; CHECK-LABEL: uunpklo_i16_valid:38; CHECK: // %bb.0:39; CHECK-NEXT: ptrue p0.s, vl3240; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]41; CHECK-NEXT: ret42 %mask = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)43 %load = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16(ptr %b, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x i16> poison)44 %uzp = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16> %load)45 ret <vscale x 4 x i32> %uzp46}47 48define <vscale x 4 x i32> @uunpklo_i16_invalid(ptr %b) #0 {49; CHECK-LABEL: uunpklo_i16_invalid:50; CHECK: // %bb.0:51; CHECK-NEXT: ptrue p0.h, vl6452; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]53; CHECK-NEXT: uunpklo z0.s, z0.h54; CHECK-NEXT: ret55 %mask = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 11)56 %load = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16(ptr %b, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x i16> poison)57 %uzp = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16> %load)58 ret <vscale x 4 x i32> %uzp59}60 61define <vscale x 2 x i64> @uunpklo_i32_valid(ptr %b) #0 {62; CHECK-LABEL: uunpklo_i32_valid:63; CHECK: // %bb.0:64; CHECK-NEXT: ptrue p0.d, vl1665; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]66; CHECK-NEXT: ret67 %mask = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 9)68 %load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr %b, i32 2, <vscale x 4 x i1> %mask, <vscale x 4 x i32> poison)69 %uzp = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32> %load)70 ret <vscale x 2 x i64> %uzp71}72 73define <vscale x 2 x i64> @uunpklo_i32_invalid(ptr %b) #0 {74; CHECK-LABEL: uunpklo_i32_invalid:75; CHECK: // %bb.0:76; CHECK-NEXT: ptrue p0.s, vl3277; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]78; CHECK-NEXT: uunpklo z0.d, z0.s79; CHECK-NEXT: ret80 %mask = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)81 %load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr %b, i32 2, <vscale x 4 x i1> %mask, <vscale x 4 x i32> poison)82 %uzp = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32> %load)83 ret <vscale x 2 x i64> %uzp84}85 86define <vscale x 2 x i64> @uunpklo_invalid_all(ptr %b) #0 {87; CHECK-LABEL: uunpklo_invalid_all:88; CHECK: // %bb.0:89; CHECK-NEXT: ldr z0, [x0]90; CHECK-NEXT: uunpklo z0.d, z0.s91; CHECK-NEXT: ret92 %mask = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)93 %load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr %b, i32 2, <vscale x 4 x i1> %mask, <vscale x 4 x i32> poison)94 %uzp = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32> %load)95 ret <vscale x 2 x i64> %uzp96}97 98; UZP1 + Store99 100define void @uzp1_i8_valid(<vscale x 8 x i16> %a, ptr %b) #0 {101; CHECK-LABEL: uzp1_i8_valid:102; CHECK: // %bb.0:103; CHECK-NEXT: ptrue p0.h, vl64104; CHECK-NEXT: st1b { z0.h }, p0, [x0]105; CHECK-NEXT: ret106 %a.bc = bitcast <vscale x 8 x i16> %a to <vscale x 16 x i8>107 %uzp = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %a.bc, <vscale x 16 x i8> %a.bc)108 %mask = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)109 call void @llvm.masked.store.nxv16i8(<vscale x 16 x i8> %uzp, ptr %b, i32 2, <vscale x 16 x i1> %mask)110 ret void111}112 113define void @uzp1_i8_invalid(<vscale x 8 x i16> %a, ptr %b) #0 {114; CHECK-LABEL: uzp1_i8_invalid:115; CHECK: // %bb.0:116; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b117; CHECK-NEXT: ptrue p0.b, vl128118; CHECK-NEXT: st1b { z0.b }, p0, [x0]119; CHECK-NEXT: ret120 %a.bc = bitcast <vscale x 8 x i16> %a to <vscale x 16 x i8>121 %uzp = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %a.bc, <vscale x 16 x i8> %a.bc)122 %mask = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 12)123 call void @llvm.masked.store.nxv16i8(<vscale x 16 x i8> %uzp, ptr %b, i32 2, <vscale x 16 x i1> %mask)124 ret void125}126 127define void @uzp1_i16_valid(<vscale x 4 x i32> %a, ptr %b) #0 {128; CHECK-LABEL: uzp1_i16_valid:129; CHECK: // %bb.0:130; CHECK-NEXT: ptrue p0.s, vl32131; CHECK-NEXT: st1h { z0.s }, p0, [x0]132; CHECK-NEXT: ret133 %a.bc = bitcast <vscale x 4 x i32> %a to <vscale x 8 x i16>134 %uzp = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %a.bc, <vscale x 8 x i16> %a.bc)135 %mask = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)136 call void @llvm.masked.store.nxv8i16(<vscale x 8 x i16> %uzp, ptr %b, i32 2, <vscale x 8 x i1> %mask)137 ret void138}139 140define void @uzp1_i16_invalid(<vscale x 4 x i32> %a, ptr %b) #0 {141; CHECK-LABEL: uzp1_i16_invalid:142; CHECK: // %bb.0:143; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h144; CHECK-NEXT: ptrue p0.h, vl64145; CHECK-NEXT: st1h { z0.h }, p0, [x0]146; CHECK-NEXT: ret147 %a.bc = bitcast <vscale x 4 x i32> %a to <vscale x 8 x i16>148 %uzp = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %a.bc, <vscale x 8 x i16> %a.bc)149 %mask = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 11)150 call void @llvm.masked.store.nxv8i16(<vscale x 8 x i16> %uzp, ptr %b, i32 2, <vscale x 8 x i1> %mask)151 ret void152}153 154define void @uzp1_i32_valid(<vscale x 2 x i64> %a, ptr %b) #0 {155; CHECK-LABEL: uzp1_i32_valid:156; CHECK: // %bb.0:157; CHECK-NEXT: ptrue p0.d, vl16158; CHECK-NEXT: st1w { z0.d }, p0, [x0]159; CHECK-NEXT: ret160 %a.bc = bitcast <vscale x 2 x i64> %a to <vscale x 4 x i32>161 %uzp = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %a.bc, <vscale x 4 x i32> %a.bc)162 %mask = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 9)163 call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %uzp, ptr %b, i32 2, <vscale x 4 x i1> %mask)164 ret void165}166 167define void @uzp1_i32_invalid(<vscale x 2 x i64> %a, ptr %b) #0 {168; CHECK-LABEL: uzp1_i32_invalid:169; CHECK: // %bb.0:170; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s171; CHECK-NEXT: ptrue p0.s, vl32172; CHECK-NEXT: st1w { z0.s }, p0, [x0]173; CHECK-NEXT: ret174 %a.bc = bitcast <vscale x 2 x i64> %a to <vscale x 4 x i32>175 %uzp = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %a.bc, <vscale x 4 x i32> %a.bc)176 %mask = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)177 call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %uzp, ptr %b, i32 2, <vscale x 4 x i1> %mask)178 ret void179}180 181define void @uzp1_invalid_all(<vscale x 2 x i64> %a, ptr %b) #0 {182; CHECK-LABEL: uzp1_invalid_all:183; CHECK: // %bb.0:184; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s185; CHECK-NEXT: str z0, [x0]186; CHECK-NEXT: ret187 %a.bc = bitcast <vscale x 2 x i64> %a to <vscale x 4 x i32>188 %uzp = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %a.bc, <vscale x 4 x i32> %a.bc)189 %mask = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)190 call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %uzp, ptr %b, i32 2, <vscale x 4 x i1> %mask)191 ret void192}193 194declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 %pattern)195declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 %pattern)196declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 %pattern)197 198declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8>)199declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16>)200declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32>)201 202declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)203declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)204declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)205 206declare <vscale x 16 x i8> @llvm.masked.load.nxv16i8(ptr, i32, <vscale x 16 x i1>, <vscale x 16 x i8>)207declare <vscale x 8 x i16> @llvm.masked.load.nxv8i16(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x i16>)208declare <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x i32>)209 210declare void @llvm.masked.store.nxv16i8(<vscale x 16 x i8>, ptr, i32, <vscale x 16 x i1>)211declare void @llvm.masked.store.nxv8i16(<vscale x 8 x i16>, ptr, i32, <vscale x 8 x i1>)212declare void @llvm.masked.store.nxv4i32(<vscale x 4 x i32>, ptr, i32, <vscale x 4 x i1>)213 214attributes #0 = { "target-features"="+sve" vscale_range(8,0) }215