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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -mattr=+sve,+dotprod < %s | FileCheck %s3 4define i32 @test(<vscale x 32 x i8> %bin.rdx, <vscale x 32 x i8> %bin.rdx2) {5; CHECK-LABEL: test:6; CHECK: // %bb.0:7; CHECK-NEXT: sunpklo z4.h, z2.b8; CHECK-NEXT: sunpklo z5.h, z0.b9; CHECK-NEXT: sunpkhi z0.h, z0.b10; CHECK-NEXT: sunpkhi z2.h, z2.b11; CHECK-NEXT: sunpklo z6.h, z1.b12; CHECK-NEXT: sunpkhi z1.h, z1.b13; CHECK-NEXT: sunpklo z7.h, z3.b14; CHECK-NEXT: sunpkhi z3.h, z3.b15; CHECK-NEXT: ptrue p0.s16; CHECK-NEXT: sunpkhi z24.s, z5.h17; CHECK-NEXT: sunpklo z5.s, z5.h18; CHECK-NEXT: sunpklo z25.s, z4.h19; CHECK-NEXT: sunpklo z26.s, z0.h20; CHECK-NEXT: sunpkhi z4.s, z4.h21; CHECK-NEXT: sunpklo z27.s, z2.h22; CHECK-NEXT: sunpkhi z0.s, z0.h23; CHECK-NEXT: sunpkhi z2.s, z2.h24; CHECK-NEXT: sunpklo z28.s, z6.h25; CHECK-NEXT: sunpkhi z6.s, z6.h26; CHECK-NEXT: mul z5.s, p0/m, z5.s, z25.s27; CHECK-NEXT: sunpkhi z25.s, z1.h28; CHECK-NEXT: sunpklo z1.s, z1.h29; CHECK-NEXT: mul z26.s, p0/m, z26.s, z27.s30; CHECK-NEXT: mul z4.s, p0/m, z4.s, z24.s31; CHECK-NEXT: sunpkhi z24.s, z3.h32; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s33; CHECK-NEXT: sunpkhi z2.s, z7.h34; CHECK-NEXT: sunpklo z7.s, z7.h35; CHECK-NEXT: sunpklo z3.s, z3.h36; CHECK-NEXT: mla z0.s, p0/m, z25.s, z24.s37; CHECK-NEXT: mad z2.s, p0/m, z6.s, z4.s38; CHECK-NEXT: mad z1.s, p0/m, z3.s, z26.s39; CHECK-NEXT: mla z5.s, p0/m, z28.s, z7.s40; CHECK-NEXT: add z0.s, z2.s, z0.s41; CHECK-NEXT: add z1.s, z5.s, z1.s42; CHECK-NEXT: add z0.s, z1.s, z0.s43; CHECK-NEXT: uaddv d0, p0, z0.s44; CHECK-NEXT: fmov w0, s045; CHECK-NEXT: ret46 %a = sext <vscale x 32 x i8> %bin.rdx to <vscale x 32 x i32>47 %b = sext <vscale x 32 x i8> %bin.rdx2 to <vscale x 32 x i32>48 %c = mul <vscale x 32 x i32> %a, %b49 %r = call i32 @llvm.vector.reduce.add.nxv32i32(<vscale x 32 x i32> %c)50 ret i32 %r51}52declare i32 @llvm.vector.reduce.add.nxv32i32(<vscale x 32 x i32> )53