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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s3 4;5; OR reductions6;7 8define i1 @reduce_or_insert_subvec_into_zero(<vscale x 4 x i1> %in) {9; CHECK-LABEL: reduce_or_insert_subvec_into_zero:10; CHECK: // %bb.0:11; CHECK-NEXT: ptrue p1.s12; CHECK-NEXT: ptest p1, p0.b13; CHECK-NEXT: cset w0, ne14; CHECK-NEXT: ret15 %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> zeroinitializer, <vscale x 4 x i1> %in, i64 0)16 %res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t)17 ret i1 %res18}19 20define i1 @reduce_or_insert_subvec_into_poison(<vscale x 4 x i1> %in) {21; CHECK-LABEL: reduce_or_insert_subvec_into_poison:22; CHECK: // %bb.0:23; CHECK-NEXT: ptrue p1.s24; CHECK-NEXT: ptest p1, p0.b25; CHECK-NEXT: cset w0, ne26; CHECK-NEXT: ret27 %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %in, i64 0)28 %res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t)29 ret i1 %res30}31 32define i1 @reduce_or_insert_subvec_into_nonzero(<vscale x 4 x i1> %in, <vscale x 16 x i1> %vec) {33; CHECK-LABEL: reduce_or_insert_subvec_into_nonzero:34; CHECK: // %bb.0:35; CHECK-NEXT: punpklo p2.h, p1.b36; CHECK-NEXT: punpkhi p1.h, p1.b37; CHECK-NEXT: punpkhi p2.h, p2.b38; CHECK-NEXT: uzp1 p0.h, p0.h, p2.h39; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b40; CHECK-NEXT: ptest p0, p0.b41; CHECK-NEXT: cset w0, ne42; CHECK-NEXT: ret43 %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %in, i64 0)44 %res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t)45 ret i1 %res46}47 48;49; AND reductions50;51 52define i1 @reduce_and_insert_subvec_into_ones(<vscale x 4 x i1> %in) {53; CHECK-LABEL: reduce_and_insert_subvec_into_ones:54; CHECK: // %bb.0:55; CHECK-NEXT: ptrue p1.s56; CHECK-NEXT: nots p0.b, p1/z, p0.b57; CHECK-NEXT: cset w0, eq58; CHECK-NEXT: ret59 %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> splat(i1 true), <vscale x 4 x i1> %in, i64 0)60 %res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)61 ret i1 %res62}63 64define i1 @reduce_and_insert_subvec_into_poison(<vscale x 4 x i1> %in) {65; CHECK-LABEL: reduce_and_insert_subvec_into_poison:66; CHECK: // %bb.0:67; CHECK-NEXT: ptrue p1.s68; CHECK-NEXT: nots p0.b, p1/z, p0.b69; CHECK-NEXT: cset w0, eq70; CHECK-NEXT: ret71 %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %in, i64 0)72 %res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)73 ret i1 %res74}75 76define i1 @reduce_and_insert_subvec_into_var(<vscale x 4 x i1> %in, <vscale x 16 x i1> %vec) {77; CHECK-LABEL: reduce_and_insert_subvec_into_var:78; CHECK: // %bb.0:79; CHECK-NEXT: punpklo p3.h, p1.b80; CHECK-NEXT: punpkhi p1.h, p1.b81; CHECK-NEXT: punpkhi p3.h, p3.b82; CHECK-NEXT: ptrue p2.b83; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h84; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b85; CHECK-NEXT: nots p0.b, p2/z, p0.b86; CHECK-NEXT: cset w0, eq87; CHECK-NEXT: ret88 %t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %in, i64 0)89 %res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)90 ret i1 %res91}92 93declare i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1>)94declare i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1>)95declare <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i64)96