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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s --check-prefixes=CHECK,CHECK-NOARG3; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ARG4 5target triple = "aarch64-unknown-linux-gnu"6 7define void @func_vscale_none(ptr %a, ptr %b) #0 {8; CHECK-NOARG-LABEL: func_vscale_none:9; CHECK-NOARG: // %bb.0:10; CHECK-NOARG-NEXT: ldp q0, q3, [x1, #32]11; CHECK-NOARG-NEXT: ldp q1, q2, [x0, #32]12; CHECK-NOARG-NEXT: ldp q4, q6, [x1]13; CHECK-NOARG-NEXT: add v0.4s, v1.4s, v0.4s14; CHECK-NOARG-NEXT: ldp q1, q5, [x0]15; CHECK-NOARG-NEXT: add v2.4s, v2.4s, v3.4s16; CHECK-NOARG-NEXT: add v1.4s, v1.4s, v4.4s17; CHECK-NOARG-NEXT: add v3.4s, v5.4s, v6.4s18; CHECK-NOARG-NEXT: stp q0, q2, [x0, #32]19; CHECK-NOARG-NEXT: stp q1, q3, [x0]20; CHECK-NOARG-NEXT: ret21;22; CHECK-ARG-LABEL: func_vscale_none:23; CHECK-ARG: // %bb.0:24; CHECK-ARG-NEXT: ptrue p0.s, vl1625; CHECK-ARG-NEXT: ld1w { z0.s }, p0/z, [x0]26; CHECK-ARG-NEXT: ld1w { z1.s }, p0/z, [x1]27; CHECK-ARG-NEXT: add z0.s, z0.s, z1.s28; CHECK-ARG-NEXT: st1w { z0.s }, p0, [x0]29; CHECK-ARG-NEXT: ret30 %op1 = load <16 x i32>, ptr %a31 %op2 = load <16 x i32>, ptr %b32 %res = add <16 x i32> %op1, %op233 store <16 x i32> %res, ptr %a34 ret void35}36 37attributes #0 = { "target-features"="+sve" }38 39define void @func_vscale1_1(ptr %a, ptr %b) #1 {40; CHECK-LABEL: func_vscale1_1:41; CHECK: // %bb.0:42; CHECK-NEXT: ldp q0, q3, [x1, #32]43; CHECK-NEXT: ldp q1, q2, [x0, #32]44; CHECK-NEXT: ldp q4, q6, [x1]45; CHECK-NEXT: add v0.4s, v1.4s, v0.4s46; CHECK-NEXT: ldp q1, q5, [x0]47; CHECK-NEXT: add v2.4s, v2.4s, v3.4s48; CHECK-NEXT: add v1.4s, v1.4s, v4.4s49; CHECK-NEXT: add v3.4s, v5.4s, v6.4s50; CHECK-NEXT: stp q0, q2, [x0, #32]51; CHECK-NEXT: stp q1, q3, [x0]52; CHECK-NEXT: ret53 %op1 = load <16 x i32>, ptr %a54 %op2 = load <16 x i32>, ptr %b55 %res = add <16 x i32> %op1, %op256 store <16 x i32> %res, ptr %a57 ret void58}59 60attributes #1 = { "target-features"="+sve" vscale_range(1,1) }61 62define void @func_vscale2_2(ptr %a, ptr %b) #2 {63; CHECK-LABEL: func_vscale2_2:64; CHECK: // %bb.0:65; CHECK-NEXT: ldr z0, [x0]66; CHECK-NEXT: ldr z1, [x1]67; CHECK-NEXT: ldr z2, [x0, #1, mul vl]68; CHECK-NEXT: ldr z3, [x1, #1, mul vl]69; CHECK-NEXT: add z0.s, z0.s, z1.s70; CHECK-NEXT: add z1.s, z2.s, z3.s71; CHECK-NEXT: str z0, [x0]72; CHECK-NEXT: str z1, [x0, #1, mul vl]73; CHECK-NEXT: ret74 %op1 = load <16 x i32>, ptr %a75 %op2 = load <16 x i32>, ptr %b76 %res = add <16 x i32> %op1, %op277 store <16 x i32> %res, ptr %a78 ret void79}80 81attributes #2 = { "target-features"="+sve" vscale_range(2,2) }82 83define void @func_vscale2_4(ptr %a, ptr %b) #3 {84; CHECK-LABEL: func_vscale2_4:85; CHECK: // %bb.0:86; CHECK-NEXT: ptrue p0.s, vl887; CHECK-NEXT: mov x8, #8 // =0x888; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]89; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]90; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0]91; CHECK-NEXT: ld1w { z3.s }, p0/z, [x1]92; CHECK-NEXT: add z0.s, z0.s, z1.s93; CHECK-NEXT: add z1.s, z2.s, z3.s94; CHECK-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]95; CHECK-NEXT: st1w { z1.s }, p0, [x0]96; CHECK-NEXT: ret97 %op1 = load <16 x i32>, ptr %a98 %op2 = load <16 x i32>, ptr %b99 %res = add <16 x i32> %op1, %op2100 store <16 x i32> %res, ptr %a101 ret void102}103 104attributes #3 = { "target-features"="+sve" vscale_range(2,4) }105 106define void @func_vscale4_4(ptr %a, ptr %b) #4 {107; CHECK-LABEL: func_vscale4_4:108; CHECK: // %bb.0:109; CHECK-NEXT: ldr z0, [x0]110; CHECK-NEXT: ldr z1, [x1]111; CHECK-NEXT: add z0.s, z0.s, z1.s112; CHECK-NEXT: str z0, [x0]113; CHECK-NEXT: ret114 %op1 = load <16 x i32>, ptr %a115 %op2 = load <16 x i32>, ptr %b116 %res = add <16 x i32> %op1, %op2117 store <16 x i32> %res, ptr %a118 ret void119}120 121attributes #4 = { "target-features"="+sve" vscale_range(4,4) }122 123define void @func_vscale8_8(ptr %a, ptr %b) #5 {124; CHECK-LABEL: func_vscale8_8:125; CHECK: // %bb.0:126; CHECK-NEXT: ptrue p0.s, vl16127; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]128; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]129; CHECK-NEXT: add z0.s, z0.s, z1.s130; CHECK-NEXT: st1w { z0.s }, p0, [x0]131; CHECK-NEXT: ret132 %op1 = load <16 x i32>, ptr %a133 %op2 = load <16 x i32>, ptr %b134 %res = add <16 x i32> %op1, %op2135 store <16 x i32> %res, ptr %a136 ret void137}138 139attributes #5 = { "target-features"="+sve" vscale_range(8,8) }140