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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s3 4define <vscale x 16 x i8> @sel_8_positive(<vscale x 16 x i1> %p) {5; CHECK-LABEL: sel_8_positive:6; CHECK: // %bb.0:7; CHECK-NEXT: mov z0.b, p0/z, #3 // =0x38; CHECK-NEXT: ret9 %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> splat (i8 3), <vscale x 16 x i8> zeroinitializer10 ret <vscale x 16 x i8> %sel11}12 13define <vscale x 8 x i16> @sel_16_positive(<vscale x 8 x i1> %p) {14; CHECK-LABEL: sel_16_positive:15; CHECK: // %bb.0:16; CHECK-NEXT: mov z0.h, p0/z, #3 // =0x317; CHECK-NEXT: ret18 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 3), <vscale x 8 x i16> zeroinitializer19 ret <vscale x 8 x i16> %sel20}21 22define <vscale x 4 x i32> @sel_32_positive(<vscale x 4 x i1> %p) {23; CHECK-LABEL: sel_32_positive:24; CHECK: // %bb.0:25; CHECK-NEXT: mov z0.s, p0/z, #3 // =0x326; CHECK-NEXT: ret27 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> zeroinitializer28 ret <vscale x 4 x i32> %sel29}30 31define <vscale x 2 x i64> @sel_64_positive(<vscale x 2 x i1> %p) {32; CHECK-LABEL: sel_64_positive:33; CHECK: // %bb.0:34; CHECK-NEXT: mov z0.d, p0/z, #3 // =0x335; CHECK-NEXT: ret36 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 3), <vscale x 2 x i64> zeroinitializer37 ret <vscale x 2 x i64> %sel38}39 40define <vscale x 16 x i8> @sel_8_negative(<vscale x 16 x i1> %p) {41; CHECK-LABEL: sel_8_negative:42; CHECK: // %bb.0:43; CHECK-NEXT: mov z0.b, p0/z, #-128 // =0xffffffffffffff8044; CHECK-NEXT: ret45 %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> zeroinitializer46 ret <vscale x 16 x i8> %sel47}48 49define <vscale x 8 x i16> @sel_16_negative(<vscale x 8 x i1> %p) {50; CHECK-LABEL: sel_16_negative:51; CHECK: // %bb.0:52; CHECK-NEXT: mov z0.h, p0/z, #-128 // =0xffffffffffffff8053; CHECK-NEXT: ret54 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 -128), <vscale x 8 x i16> zeroinitializer55 ret <vscale x 8 x i16> %sel56}57 58define <vscale x 4 x i32> @sel_32_negative(<vscale x 4 x i1> %p) {59; CHECK-LABEL: sel_32_negative:60; CHECK: // %bb.0:61; CHECK-NEXT: mov z0.s, p0/z, #-128 // =0xffffffffffffff8062; CHECK-NEXT: ret63 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 -128), <vscale x 4 x i32> zeroinitializer64 ret <vscale x 4 x i32> %sel65}66 67define <vscale x 2 x i64> @sel_64_negative(<vscale x 2 x i1> %p) {68; CHECK-LABEL: sel_64_negative:69; CHECK: // %bb.0:70; CHECK-NEXT: mov z0.d, p0/z, #-128 // =0xffffffffffffff8071; CHECK-NEXT: ret72 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 -128), <vscale x 2 x i64> zeroinitializer73 ret <vscale x 2 x i64> %sel74}75 76define <vscale x 8 x i16> @sel_16_shifted(<vscale x 8 x i1> %p) {77; CHECK-LABEL: sel_16_shifted:78; CHECK: // %bb.0:79; CHECK-NEXT: mov z0.h, p0/z, #512 // =0x20080; CHECK-NEXT: ret81 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 512), <vscale x 8 x i16> zeroinitializer82 ret <vscale x 8 x i16> %sel83}84 85define <vscale x 4 x i32> @sel_32_shifted(<vscale x 4 x i1> %p) {86; CHECK-LABEL: sel_32_shifted:87; CHECK: // %bb.0:88; CHECK-NEXT: mov z0.s, p0/z, #512 // =0x20089; CHECK-NEXT: ret90 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 512), <vscale x 4 x i32> zeroinitializer91 ret <vscale x 4 x i32> %sel92}93 94define <vscale x 2 x i64> @sel_64_shifted(<vscale x 2 x i1> %p) {95; CHECK-LABEL: sel_64_shifted:96; CHECK: // %bb.0:97; CHECK-NEXT: mov z0.d, p0/z, #512 // =0x20098; CHECK-NEXT: ret99 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 512), <vscale x 2 x i64> zeroinitializer100 ret <vscale x 2 x i64> %sel101}102 103; TODO: We could actually use something like "cpy z0.b, p0/z, #-128". But it's104; a little tricky to prove correctness: we're using the predicate with the105; wrong width, so we'd have to prove the bits which would normally be unused106; are actually zero.107define <vscale x 8 x i16> @sel_16_illegal_wrong_extension(<vscale x 8 x i1> %p) {108; CHECK-LABEL: sel_16_illegal_wrong_extension:109; CHECK: // %bb.0:110; CHECK-NEXT: movi v0.2d, #0000000000000000111; CHECK-NEXT: mov z1.h, #128 // =0x80112; CHECK-NEXT: mov z0.h, p0/m, z1.h113; CHECK-NEXT: ret114 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 128), <vscale x 8 x i16> zeroinitializer115 ret <vscale x 8 x i16> %sel116}117 118define <vscale x 4 x i32> @sel_32_illegal_wrong_extension(<vscale x 4 x i1> %p) {119; CHECK-LABEL: sel_32_illegal_wrong_extension:120; CHECK: // %bb.0:121; CHECK-NEXT: movi v0.2d, #0000000000000000122; CHECK-NEXT: mov z1.s, #128 // =0x80123; CHECK-NEXT: mov z0.s, p0/m, z1.s124; CHECK-NEXT: ret125 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 128), <vscale x 4 x i32> zeroinitializer126 ret <vscale x 4 x i32> %sel127}128 129define <vscale x 2 x i64> @sel_64_illegal_wrong_extension(<vscale x 2 x i1> %p) {130; CHECK-LABEL: sel_64_illegal_wrong_extension:131; CHECK: // %bb.0:132; CHECK-NEXT: movi v0.2d, #0000000000000000133; CHECK-NEXT: mov z1.d, #128 // =0x80134; CHECK-NEXT: mov z0.d, p0/m, z1.d135; CHECK-NEXT: ret136 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 128), <vscale x 2 x i64> zeroinitializer137 ret <vscale x 2 x i64> %sel138}139 140define <vscale x 8 x i16> @sel_16_illegal_shifted(<vscale x 8 x i1> %p) {141; CHECK-LABEL: sel_16_illegal_shifted:142; CHECK: // %bb.0:143; CHECK-NEXT: movi v0.2d, #0000000000000000144; CHECK-NEXT: mov w8, #513 // =0x201145; CHECK-NEXT: mov z1.h, w8146; CHECK-NEXT: mov z0.h, p0/m, z1.h147; CHECK-NEXT: ret148 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 513), <vscale x 8 x i16> zeroinitializer149 ret <vscale x 8 x i16> %sel150}151 152define <vscale x 4 x i32> @sel_32_illegal_shifted(<vscale x 4 x i1> %p) {153; CHECK-LABEL: sel_32_illegal_shifted:154; CHECK: // %bb.0:155; CHECK-NEXT: movi v0.2d, #0000000000000000156; CHECK-NEXT: mov w8, #513 // =0x201157; CHECK-NEXT: mov z1.s, w8158; CHECK-NEXT: mov z0.s, p0/m, z1.s159; CHECK-NEXT: ret160 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 513), <vscale x 4 x i32> zeroinitializer161 ret <vscale x 4 x i32> %sel162}163 164define <vscale x 2 x i64> @sel_64_illegal_shifted(<vscale x 2 x i1> %p) {165; CHECK-LABEL: sel_64_illegal_shifted:166; CHECK: // %bb.0:167; CHECK-NEXT: movi v0.2d, #0000000000000000168; CHECK-NEXT: mov w8, #513 // =0x201169; CHECK-NEXT: mov z1.d, x8170; CHECK-NEXT: mov z0.d, p0/m, z1.d171; CHECK-NEXT: ret172 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 513), <vscale x 2 x i64> zeroinitializer173 ret <vscale x 2 x i64> %sel174}175 176define <vscale x 16 x i8> @sel_merge_8_positive(<vscale x 16 x i1> %p, <vscale x 16 x i8> %in) {177; CHECK-LABEL: sel_merge_8_positive:178; CHECK: // %bb.0:179; CHECK-NEXT: mov z0.b, p0/m, #3 // =0x3180; CHECK-NEXT: ret181 %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> splat (i8 3), <vscale x 16 x i8> %in182 ret <vscale x 16 x i8> %sel183}184 185define <vscale x 8 x i16> @sel_merge_16_positive(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) {186; CHECK-LABEL: sel_merge_16_positive:187; CHECK: // %bb.0:188; CHECK-NEXT: mov z0.h, p0/m, #3 // =0x3189; CHECK-NEXT: ret190 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 3), <vscale x 8 x i16> %in191 ret <vscale x 8 x i16> %sel192}193 194define <vscale x 4 x i32> @sel_merge_32_positive(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) {195; CHECK-LABEL: sel_merge_32_positive:196; CHECK: // %bb.0:197; CHECK-NEXT: mov z0.s, p0/m, #3 // =0x3198; CHECK-NEXT: ret199 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> %in200 ret <vscale x 4 x i32> %sel201}202 203define <vscale x 2 x i64> @sel_merge_64_positive(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) {204; CHECK-LABEL: sel_merge_64_positive:205; CHECK: // %bb.0:206; CHECK-NEXT: mov z0.d, p0/m, #3 // =0x3207; CHECK-NEXT: ret208 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 3), <vscale x 2 x i64> %in209 ret <vscale x 2 x i64> %sel210}211 212define <vscale x 16 x i8> @sel_merge_8_negative(<vscale x 16 x i1> %p, <vscale x 16 x i8> %in) {213; CHECK-LABEL: sel_merge_8_negative:214; CHECK: // %bb.0:215; CHECK-NEXT: mov z0.b, p0/m, #-128 // =0xffffffffffffff80216; CHECK-NEXT: ret217 %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> %in218 ret <vscale x 16 x i8> %sel219}220 221define <vscale x 8 x i16> @sel_merge_16_negative(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) {222; CHECK-LABEL: sel_merge_16_negative:223; CHECK: // %bb.0:224; CHECK-NEXT: mov z0.h, p0/m, #-128 // =0xffffffffffffff80225; CHECK-NEXT: ret226 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 -128), <vscale x 8 x i16> %in227 ret <vscale x 8 x i16> %sel228}229 230define <vscale x 4 x i32> @sel_merge_32_negative(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) {231; CHECK-LABEL: sel_merge_32_negative:232; CHECK: // %bb.0:233; CHECK-NEXT: mov z0.s, p0/m, #-128 // =0xffffffffffffff80234; CHECK-NEXT: ret235 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 -128), <vscale x 4 x i32> %in236 ret <vscale x 4 x i32> %sel237}238 239define <vscale x 2 x i64> @sel_merge_64_negative(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) {240; CHECK-LABEL: sel_merge_64_negative:241; CHECK: // %bb.0:242; CHECK-NEXT: mov z0.d, p0/m, #-128 // =0xffffffffffffff80243; CHECK-NEXT: ret244 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 -128), <vscale x 2 x i64> %in245 ret <vscale x 2 x i64> %sel246}247 248define <vscale x 16 x i8> @sel_merge_8_zero(<vscale x 16 x i1> %p, <vscale x 16 x i8> %in) {249; CHECK-LABEL: sel_merge_8_zero:250; CHECK: // %bb.0:251; CHECK-NEXT: mov z0.b, p0/m, #0 // =0x0252; CHECK-NEXT: ret253 %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %in254 ret <vscale x 16 x i8> %sel255}256 257define <vscale x 8 x i16> @sel_merge_16_zero(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) {258; CHECK-LABEL: sel_merge_16_zero:259; CHECK: // %bb.0:260; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x0261; CHECK-NEXT: ret262 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i16> %in263 ret <vscale x 8 x i16> %sel264}265 266define <vscale x 4 x i32> @sel_merge_32_zero(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) {267; CHECK-LABEL: sel_merge_32_zero:268; CHECK: // %bb.0:269; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0270; CHECK-NEXT: ret271 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> %in272 ret <vscale x 4 x i32> %sel273}274 275define <vscale x 2 x i64> @sel_merge_64_zero(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) {276; CHECK-LABEL: sel_merge_64_zero:277; CHECK: // %bb.0:278; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0279; CHECK-NEXT: ret280 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i64> %in281 ret <vscale x 2 x i64> %sel282}283 284define <vscale x 8 x half> @sel_merge_nxv8f16_zero(<vscale x 8 x i1> %p, <vscale x 8 x half> %in) {285; CHECK-LABEL: sel_merge_nxv8f16_zero:286; CHECK: // %bb.0:287; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x0288; CHECK-NEXT: ret289%sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> zeroinitializer, <vscale x 8 x half> %in290ret <vscale x 8 x half> %sel291}292 293define <vscale x 4 x half> @sel_merge_nx4f16_zero(<vscale x 4 x i1> %p, <vscale x 4 x half> %in) {294; CHECK-LABEL: sel_merge_nx4f16_zero:295; CHECK: // %bb.0:296; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0297; CHECK-NEXT: ret298%sel = select <vscale x 4 x i1> %p, <vscale x 4 x half> zeroinitializer, <vscale x 4 x half> %in299ret <vscale x 4 x half> %sel300}301 302define <vscale x 2 x half> @sel_merge_nx2f16_zero(<vscale x 2 x i1> %p, <vscale x 2 x half> %in) {303; CHECK-LABEL: sel_merge_nx2f16_zero:304; CHECK: // %bb.0:305; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0306; CHECK-NEXT: ret307%sel = select <vscale x 2 x i1> %p, <vscale x 2 x half> zeroinitializer, <vscale x 2 x half> %in308ret <vscale x 2 x half> %sel309}310 311define <vscale x 4 x float> @sel_merge_nx4f32_zero(<vscale x 4 x i1> %p, <vscale x 4 x float> %in) {312; CHECK-LABEL: sel_merge_nx4f32_zero:313; CHECK: // %bb.0:314; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0315; CHECK-NEXT: ret316%sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> zeroinitializer, <vscale x 4 x float> %in317ret <vscale x 4 x float> %sel318}319 320define <vscale x 2 x float> @sel_merge_nx2f32_zero(<vscale x 2 x i1> %p, <vscale x 2 x float> %in) {321; CHECK-LABEL: sel_merge_nx2f32_zero:322; CHECK: // %bb.0:323; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0324; CHECK-NEXT: ret325%sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> zeroinitializer, <vscale x 2 x float> %in326ret <vscale x 2 x float> %sel327}328 329define <vscale x 2 x double> @sel_merge_nx2f64_zero(<vscale x 2 x i1> %p, <vscale x 2 x double> %in) {330; CHECK-LABEL: sel_merge_nx2f64_zero:331; CHECK: // %bb.0:332; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0333; CHECK-NEXT: ret334%sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> zeroinitializer, <vscale x 2 x double> %in335ret <vscale x 2 x double> %sel336}337 338define <vscale x 8 x half> @sel_merge_nxv8f16_negative_zero(<vscale x 8 x i1> %p, <vscale x 8 x half> %in) {339; CHECK-LABEL: sel_merge_nxv8f16_negative_zero:340; CHECK: // %bb.0:341; CHECK-NEXT: dupm z1.h, #0x8000342; CHECK-NEXT: mov z0.h, p0/m, z1.h343; CHECK-NEXT: ret344%sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> splat (half -0.0), <vscale x 8 x half> %in345ret <vscale x 8 x half> %sel346}347 348define <vscale x 4 x half> @sel_merge_nx4f16_negative_zero(<vscale x 4 x i1> %p, <vscale x 4 x half> %in) {349; CHECK-LABEL: sel_merge_nx4f16_negative_zero:350; CHECK: // %bb.0:351; CHECK-NEXT: dupm z1.h, #0x8000352; CHECK-NEXT: mov z0.s, p0/m, z1.s353; CHECK-NEXT: ret354%sel = select <vscale x 4 x i1> %p, <vscale x 4 x half> splat (half -0.0), <vscale x 4 x half> %in355ret <vscale x 4 x half> %sel356}357 358define <vscale x 2 x half> @sel_merge_nx2f16_negative_zero(<vscale x 2 x i1> %p, <vscale x 2 x half> %in) {359; CHECK-LABEL: sel_merge_nx2f16_negative_zero:360; CHECK: // %bb.0:361; CHECK-NEXT: dupm z1.h, #0x8000362; CHECK-NEXT: mov z0.d, p0/m, z1.d363; CHECK-NEXT: ret364%sel = select <vscale x 2 x i1> %p, <vscale x 2 x half> splat (half -0.0), <vscale x 2 x half> %in365ret <vscale x 2 x half> %sel366}367 368define <vscale x 4 x float> @sel_merge_nx4f32_negative_zero(<vscale x 4 x i1> %p, <vscale x 4 x float> %in) {369; CHECK-LABEL: sel_merge_nx4f32_negative_zero:370; CHECK: // %bb.0:371; CHECK-NEXT: mov z1.s, #0x80000000372; CHECK-NEXT: mov z0.s, p0/m, z1.s373; CHECK-NEXT: ret374%sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> splat (float -0.0), <vscale x 4 x float> %in375ret <vscale x 4 x float> %sel376}377 378define <vscale x 2 x float> @sel_merge_nx2f32_negative_zero(<vscale x 2 x i1> %p, <vscale x 2 x float> %in) {379; CHECK-LABEL: sel_merge_nx2f32_negative_zero:380; CHECK: // %bb.0:381; CHECK-NEXT: mov z1.s, #0x80000000382; CHECK-NEXT: mov z0.d, p0/m, z1.d383; CHECK-NEXT: ret384%sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> splat (float -0.0), <vscale x 2 x float> %in385ret <vscale x 2 x float> %sel386}387 388define <vscale x 2 x double> @sel_merge_nx2f64_negative_zero(<vscale x 2 x i1> %p, <vscale x 2 x double> %in) {389; CHECK-LABEL: sel_merge_nx2f64_negative_zero:390; CHECK: // %bb.0:391; CHECK-NEXT: mov z1.d, #0x8000000000000000392; CHECK-NEXT: mov z0.d, p0/m, z1.d393; CHECK-NEXT: ret394%sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> splat (double -0.0), <vscale x 2 x double> %in395ret <vscale x 2 x double> %sel396}397 398define <vscale x 8 x i16> @sel_merge_16_shifted(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) {399; CHECK-LABEL: sel_merge_16_shifted:400; CHECK: // %bb.0:401; CHECK-NEXT: mov z0.h, p0/m, #512 // =0x200402; CHECK-NEXT: ret403 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 512), <vscale x 8 x i16> %in404 ret <vscale x 8 x i16> %sel405}406 407define <vscale x 4 x i32> @sel_merge_32_shifted(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) {408; CHECK-LABEL: sel_merge_32_shifted:409; CHECK: // %bb.0:410; CHECK-NEXT: mov z0.s, p0/m, #512 // =0x200411; CHECK-NEXT: ret412 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 512), <vscale x 4 x i32> %in413 ret <vscale x 4 x i32> %sel414}415 416define <vscale x 2 x i64> @sel_merge_64_shifted(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) {417; CHECK-LABEL: sel_merge_64_shifted:418; CHECK: // %bb.0:419; CHECK-NEXT: mov z0.d, p0/m, #512 // =0x200420; CHECK-NEXT: ret421 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 512), <vscale x 2 x i64> %in422 ret <vscale x 2 x i64> %sel423}424 425; TODO: We could actually use something like "cpy z0.b, p0/m, #-128". But it's426; a little tricky to prove correctness: we're using the predicate with the427; wrong width, so we'd have to prove the bits which would normally be unused428; are actually zero.429define <vscale x 8 x i16> @sel_merge_16_illegal_wrong_extension(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) {430; CHECK-LABEL: sel_merge_16_illegal_wrong_extension:431; CHECK: // %bb.0:432; CHECK-NEXT: mov z1.h, #128 // =0x80433; CHECK-NEXT: mov z0.h, p0/m, z1.h434; CHECK-NEXT: ret435 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 128), <vscale x 8 x i16> %in436 ret <vscale x 8 x i16> %sel437}438 439define <vscale x 4 x i32> @sel_merge_32_illegal_wrong_extension(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) {440; CHECK-LABEL: sel_merge_32_illegal_wrong_extension:441; CHECK: // %bb.0:442; CHECK-NEXT: mov z1.s, #128 // =0x80443; CHECK-NEXT: mov z0.s, p0/m, z1.s444; CHECK-NEXT: ret445 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 128), <vscale x 4 x i32> %in446 ret <vscale x 4 x i32> %sel447}448 449define <vscale x 2 x i64> @sel_merge_64_illegal_wrong_extension(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) {450; CHECK-LABEL: sel_merge_64_illegal_wrong_extension:451; CHECK: // %bb.0:452; CHECK-NEXT: mov z1.d, #128 // =0x80453; CHECK-NEXT: mov z0.d, p0/m, z1.d454; CHECK-NEXT: ret455 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 128), <vscale x 2 x i64> %in456 ret <vscale x 2 x i64> %sel457}458 459define <vscale x 8 x i16> @sel_merge_16_illegal_shifted(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) {460; CHECK-LABEL: sel_merge_16_illegal_shifted:461; CHECK: // %bb.0:462; CHECK-NEXT: mov w8, #513 // =0x201463; CHECK-NEXT: mov z1.h, w8464; CHECK-NEXT: mov z0.h, p0/m, z1.h465; CHECK-NEXT: ret466 %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 513), <vscale x 8 x i16> %in467 ret <vscale x 8 x i16> %sel468}469 470define <vscale x 4 x i32> @sel_merge_32_illegal_shifted(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) {471; CHECK-LABEL: sel_merge_32_illegal_shifted:472; CHECK: // %bb.0:473; CHECK-NEXT: mov w8, #513 // =0x201474; CHECK-NEXT: mov z1.s, w8475; CHECK-NEXT: mov z0.s, p0/m, z1.s476; CHECK-NEXT: ret477 %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 513), <vscale x 4 x i32> %in478 ret <vscale x 4 x i32> %sel479}480 481define <vscale x 2 x i64> @sel_merge_64_illegal_shifted(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) {482; CHECK-LABEL: sel_merge_64_illegal_shifted:483; CHECK: // %bb.0:484; CHECK-NEXT: mov w8, #513 // =0x201485; CHECK-NEXT: mov z1.d, x8486; CHECK-NEXT: mov z0.d, p0/m, z1.d487; CHECK-NEXT: ret488 %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 513), <vscale x 2 x i64> %in489 ret <vscale x 2 x i64> %sel490}491