144 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck --check-prefix=SVE %s3; RUN: llc -mtriple=aarch64 -mattr=+sve2 < %s -o - | FileCheck --check-prefix=SVE2 %s4 5define <vscale x 2 x i64> @bcax_nxv2i64_1(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2) {6; SVE-LABEL: bcax_nxv2i64_1:7; SVE: // %bb.0:8; SVE-NEXT: bic z1.d, z2.d, z1.d9; SVE-NEXT: eor z0.d, z1.d, z0.d10; SVE-NEXT: ret11;12; SVE2-LABEL: bcax_nxv2i64_1:13; SVE2: // %bb.0:14; SVE2-NEXT: bcax z0.d, z0.d, z2.d, z1.d15; SVE2-NEXT: ret16 %4 = xor <vscale x 2 x i64> %1, splat (i64 -1)17 %5 = and <vscale x 2 x i64> %4, %218 %6 = xor <vscale x 2 x i64> %5, %019 ret <vscale x 2 x i64> %620}21 22define <vscale x 2 x i64> @bcax_nxv2i64_2(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2) {23; SVE-LABEL: bcax_nxv2i64_2:24; SVE: // %bb.0:25; SVE-NEXT: bic z0.d, z0.d, z1.d26; SVE-NEXT: eor z0.d, z0.d, z2.d27; SVE-NEXT: ret28;29; SVE2-LABEL: bcax_nxv2i64_2:30; SVE2: // %bb.0:31; SVE2-NEXT: bcax z2.d, z2.d, z0.d, z1.d32; SVE2-NEXT: mov z0.d, z2.d33; SVE2-NEXT: ret34 %4 = xor <vscale x 2 x i64> %1, splat (i64 -1)35 %5 = and <vscale x 2 x i64> %4, %036 %6 = xor <vscale x 2 x i64> %5, %237 ret <vscale x 2 x i64> %638}39 40define <vscale x 4 x i32> @bcax_nxv4i32_1(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2) {41; SVE-LABEL: bcax_nxv4i32_1:42; SVE: // %bb.0:43; SVE-NEXT: bic z1.d, z2.d, z1.d44; SVE-NEXT: eor z0.d, z1.d, z0.d45; SVE-NEXT: ret46;47; SVE2-LABEL: bcax_nxv4i32_1:48; SVE2: // %bb.0:49; SVE2-NEXT: bcax z0.d, z0.d, z2.d, z1.d50; SVE2-NEXT: ret51 %4 = xor <vscale x 4 x i32> %1, splat (i32 -1)52 %5 = and <vscale x 4 x i32> %4, %253 %6 = xor <vscale x 4 x i32> %5, %054 ret <vscale x 4 x i32> %655}56 57define <vscale x 4 x i32> @bcax_nxv4i32_2(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2) {58; SVE-LABEL: bcax_nxv4i32_2:59; SVE: // %bb.0:60; SVE-NEXT: bic z0.d, z0.d, z1.d61; SVE-NEXT: eor z0.d, z0.d, z2.d62; SVE-NEXT: ret63;64; SVE2-LABEL: bcax_nxv4i32_2:65; SVE2: // %bb.0:66; SVE2-NEXT: bcax z2.d, z2.d, z0.d, z1.d67; SVE2-NEXT: mov z0.d, z2.d68; SVE2-NEXT: ret69 %4 = xor <vscale x 4 x i32> %1, splat (i32 -1)70 %5 = and <vscale x 4 x i32> %4, %071 %6 = xor <vscale x 4 x i32> %5, %272 ret <vscale x 4 x i32> %673}74 75define <vscale x 8 x i16> @bcax_nxv8i16_1(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2) {76; SVE-LABEL: bcax_nxv8i16_1:77; SVE: // %bb.0:78; SVE-NEXT: bic z1.d, z2.d, z1.d79; SVE-NEXT: eor z0.d, z1.d, z0.d80; SVE-NEXT: ret81;82; SVE2-LABEL: bcax_nxv8i16_1:83; SVE2: // %bb.0:84; SVE2-NEXT: bcax z0.d, z0.d, z2.d, z1.d85; SVE2-NEXT: ret86 %4 = xor <vscale x 8 x i16> %1, splat (i16 -1)87 %5 = and <vscale x 8 x i16> %4, %288 %6 = xor <vscale x 8 x i16> %5, %089 ret <vscale x 8 x i16> %690}91 92define <vscale x 8 x i16> @bcax_nxv8i16_2(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2) {93; SVE-LABEL: bcax_nxv8i16_2:94; SVE: // %bb.0:95; SVE-NEXT: bic z0.d, z0.d, z1.d96; SVE-NEXT: eor z0.d, z0.d, z2.d97; SVE-NEXT: ret98;99; SVE2-LABEL: bcax_nxv8i16_2:100; SVE2: // %bb.0:101; SVE2-NEXT: bcax z2.d, z2.d, z0.d, z1.d102; SVE2-NEXT: mov z0.d, z2.d103; SVE2-NEXT: ret104 %4 = xor <vscale x 8 x i16> %1, splat (i16 -1)105 %5 = and <vscale x 8 x i16> %4, %0106 %6 = xor <vscale x 8 x i16> %5, %2107 ret <vscale x 8 x i16> %6108}109 110define <vscale x 16 x i8> @bcax_nxv16i8_1(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {111; SVE-LABEL: bcax_nxv16i8_1:112; SVE: // %bb.0:113; SVE-NEXT: bic z1.d, z2.d, z1.d114; SVE-NEXT: eor z0.d, z1.d, z0.d115; SVE-NEXT: ret116;117; SVE2-LABEL: bcax_nxv16i8_1:118; SVE2: // %bb.0:119; SVE2-NEXT: bcax z0.d, z0.d, z2.d, z1.d120; SVE2-NEXT: ret121 %4 = xor <vscale x 16 x i8> %1, splat (i8 -1)122 %5 = and <vscale x 16 x i8> %4, %2123 %6 = xor <vscale x 16 x i8> %5, %0124 ret <vscale x 16 x i8> %6125}126 127define <vscale x 16 x i8> @bcax_nxv16i8_2(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {128; SVE-LABEL: bcax_nxv16i8_2:129; SVE: // %bb.0:130; SVE-NEXT: bic z0.d, z0.d, z1.d131; SVE-NEXT: eor z0.d, z0.d, z2.d132; SVE-NEXT: ret133;134; SVE2-LABEL: bcax_nxv16i8_2:135; SVE2: // %bb.0:136; SVE2-NEXT: bcax z2.d, z2.d, z0.d, z1.d137; SVE2-NEXT: mov z0.d, z2.d138; SVE2-NEXT: ret139 %4 = xor <vscale x 16 x i8> %1, splat (i8 -1)140 %5 = and <vscale x 16 x i8> %4, %0141 %6 = xor <vscale x 16 x i8> %5, %2142 ret <vscale x 16 x i8> %6143}144