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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mattr=+sve2                          < %s | FileCheck %s --check-prefixes=NOBF163; RUN: llc -mattr=+sve2 --enable-no-nans-fp-math < %s | FileCheck %s --check-prefixes=NOBF16NNAN4; RUN: llc -mattr=+sve2,+bf16                    < %s | FileCheck %s --check-prefixes=BF165; RUN: llc -mattr=+sme -force-streaming          < %s | FileCheck %s --check-prefixes=BF166 7target triple = "aarch64-unknown-linux-gnu"8 9define <vscale x 2 x bfloat> @fptrunc_nxv2f64_to_nxv2bf16(<vscale x 2 x double> %a) {10; NOBF16-LABEL: fptrunc_nxv2f64_to_nxv2bf16:11; NOBF16:       // %bb.0:12; NOBF16-NEXT:    ptrue p0.d13; NOBF16-NEXT:    mov z1.s, #32767 // =0x7fff14; NOBF16-NEXT:    fcvtx z0.s, p0/m, z0.d15; NOBF16-NEXT:    lsr z2.s, z0.s, #1616; NOBF16-NEXT:    add z1.s, z0.s, z1.s17; NOBF16-NEXT:    fcmuo p0.s, p0/z, z0.s, z0.s18; NOBF16-NEXT:    orr z0.s, z0.s, #0x40000019; NOBF16-NEXT:    and z2.s, z2.s, #0x120; NOBF16-NEXT:    add z1.s, z2.s, z1.s21; NOBF16-NEXT:    sel z0.s, p0, z0.s, z1.s22; NOBF16-NEXT:    lsr z0.s, z0.s, #1623; NOBF16-NEXT:    ret24;25; NOBF16NNAN-LABEL: fptrunc_nxv2f64_to_nxv2bf16:26; NOBF16NNAN:       // %bb.0:27; NOBF16NNAN-NEXT:    ptrue p0.d28; NOBF16NNAN-NEXT:    mov z1.s, #32767 // =0x7fff29; NOBF16NNAN-NEXT:    fcvtx z0.s, p0/m, z0.d30; NOBF16NNAN-NEXT:    lsr z2.s, z0.s, #1631; NOBF16NNAN-NEXT:    add z0.s, z0.s, z1.s32; NOBF16NNAN-NEXT:    and z2.s, z2.s, #0x133; NOBF16NNAN-NEXT:    add z0.s, z2.s, z0.s34; NOBF16NNAN-NEXT:    lsr z0.s, z0.s, #1635; NOBF16NNAN-NEXT:    ret36;37; BF16-LABEL: fptrunc_nxv2f64_to_nxv2bf16:38; BF16:       // %bb.0:39; BF16-NEXT:    ptrue p0.d40; BF16-NEXT:    fcvtx z0.s, p0/m, z0.d41; BF16-NEXT:    bfcvt z0.h, p0/m, z0.s42; BF16-NEXT:    ret43  %res = fptrunc <vscale x 2 x double> %a to <vscale x 2 x bfloat>44  ret <vscale x 2 x bfloat> %res45}46 47define <vscale x 4 x bfloat> @fptrunc_nxv4f64_to_nxv4bf16(<vscale x 4 x double> %a) {48; NOBF16-LABEL: fptrunc_nxv4f64_to_nxv4bf16:49; NOBF16:       // %bb.0:50; NOBF16-NEXT:    ptrue p0.d51; NOBF16-NEXT:    mov z2.s, #32767 // =0x7fff52; NOBF16-NEXT:    fcvtx z1.s, p0/m, z1.d53; NOBF16-NEXT:    fcvtx z0.s, p0/m, z0.d54; NOBF16-NEXT:    lsr z3.s, z1.s, #1655; NOBF16-NEXT:    lsr z5.s, z0.s, #1656; NOBF16-NEXT:    add z4.s, z1.s, z2.s57; NOBF16-NEXT:    add z2.s, z0.s, z2.s58; NOBF16-NEXT:    fcmuo p1.s, p0/z, z1.s, z1.s59; NOBF16-NEXT:    orr z1.s, z1.s, #0x40000060; NOBF16-NEXT:    and z3.s, z3.s, #0x161; NOBF16-NEXT:    and z5.s, z5.s, #0x162; NOBF16-NEXT:    fcmuo p0.s, p0/z, z0.s, z0.s63; NOBF16-NEXT:    orr z0.s, z0.s, #0x40000064; NOBF16-NEXT:    add z3.s, z3.s, z4.s65; NOBF16-NEXT:    add z2.s, z5.s, z2.s66; NOBF16-NEXT:    sel z1.s, p1, z1.s, z3.s67; NOBF16-NEXT:    sel z0.s, p0, z0.s, z2.s68; NOBF16-NEXT:    lsr z1.s, z1.s, #1669; NOBF16-NEXT:    lsr z0.s, z0.s, #1670; NOBF16-NEXT:    uzp1 z0.s, z0.s, z1.s71; NOBF16-NEXT:    ret72;73; NOBF16NNAN-LABEL: fptrunc_nxv4f64_to_nxv4bf16:74; NOBF16NNAN:       // %bb.0:75; NOBF16NNAN-NEXT:    ptrue p0.d76; NOBF16NNAN-NEXT:    mov z2.s, #32767 // =0x7fff77; NOBF16NNAN-NEXT:    fcvtx z1.s, p0/m, z1.d78; NOBF16NNAN-NEXT:    fcvtx z0.s, p0/m, z0.d79; NOBF16NNAN-NEXT:    lsr z3.s, z1.s, #1680; NOBF16NNAN-NEXT:    lsr z4.s, z0.s, #1681; NOBF16NNAN-NEXT:    add z1.s, z1.s, z2.s82; NOBF16NNAN-NEXT:    add z0.s, z0.s, z2.s83; NOBF16NNAN-NEXT:    and z3.s, z3.s, #0x184; NOBF16NNAN-NEXT:    and z4.s, z4.s, #0x185; NOBF16NNAN-NEXT:    add z1.s, z3.s, z1.s86; NOBF16NNAN-NEXT:    add z0.s, z4.s, z0.s87; NOBF16NNAN-NEXT:    lsr z1.s, z1.s, #1688; NOBF16NNAN-NEXT:    lsr z0.s, z0.s, #1689; NOBF16NNAN-NEXT:    uzp1 z0.s, z0.s, z1.s90; NOBF16NNAN-NEXT:    ret91;92; BF16-LABEL: fptrunc_nxv4f64_to_nxv4bf16:93; BF16:       // %bb.0:94; BF16-NEXT:    ptrue p0.d95; BF16-NEXT:    fcvtx z1.s, p0/m, z1.d96; BF16-NEXT:    fcvtx z0.s, p0/m, z0.d97; BF16-NEXT:    bfcvt z1.h, p0/m, z1.s98; BF16-NEXT:    bfcvt z0.h, p0/m, z0.s99; BF16-NEXT:    uzp1 z0.s, z0.s, z1.s100; BF16-NEXT:    ret101  %res = fptrunc <vscale x 4 x double> %a to <vscale x 4 x bfloat>102  ret <vscale x 4 x bfloat> %res103}104 105define <vscale x 8 x bfloat> @fptrunc_nxv8f64_to_nxv8bf16(<vscale x 8 x double> %a) {106; NOBF16-LABEL: fptrunc_nxv8f64_to_nxv8bf16:107; NOBF16:       // %bb.0:108; NOBF16-NEXT:    ptrue p0.d109; NOBF16-NEXT:    mov z4.s, #32767 // =0x7fff110; NOBF16-NEXT:    fcvtx z3.s, p0/m, z3.d111; NOBF16-NEXT:    fcvtx z2.s, p0/m, z2.d112; NOBF16-NEXT:    fcvtx z1.s, p0/m, z1.d113; NOBF16-NEXT:    fcvtx z0.s, p0/m, z0.d114; NOBF16-NEXT:    lsr z5.s, z3.s, #16115; NOBF16-NEXT:    lsr z6.s, z2.s, #16116; NOBF16-NEXT:    lsr z7.s, z1.s, #16117; NOBF16-NEXT:    lsr z24.s, z0.s, #16118; NOBF16-NEXT:    add z25.s, z3.s, z4.s119; NOBF16-NEXT:    add z26.s, z2.s, z4.s120; NOBF16-NEXT:    add z27.s, z1.s, z4.s121; NOBF16-NEXT:    add z4.s, z0.s, z4.s122; NOBF16-NEXT:    and z5.s, z5.s, #0x1123; NOBF16-NEXT:    and z6.s, z6.s, #0x1124; NOBF16-NEXT:    and z7.s, z7.s, #0x1125; NOBF16-NEXT:    and z24.s, z24.s, #0x1126; NOBF16-NEXT:    fcmuo p1.s, p0/z, z3.s, z3.s127; NOBF16-NEXT:    orr z3.s, z3.s, #0x400000128; NOBF16-NEXT:    fcmuo p2.s, p0/z, z2.s, z2.s129; NOBF16-NEXT:    add z5.s, z5.s, z25.s130; NOBF16-NEXT:    add z6.s, z6.s, z26.s131; NOBF16-NEXT:    fcmuo p3.s, p0/z, z1.s, z1.s132; NOBF16-NEXT:    add z7.s, z7.s, z27.s133; NOBF16-NEXT:    add z4.s, z24.s, z4.s134; NOBF16-NEXT:    fcmuo p0.s, p0/z, z0.s, z0.s135; NOBF16-NEXT:    orr z2.s, z2.s, #0x400000136; NOBF16-NEXT:    orr z1.s, z1.s, #0x400000137; NOBF16-NEXT:    orr z0.s, z0.s, #0x400000138; NOBF16-NEXT:    sel z3.s, p1, z3.s, z5.s139; NOBF16-NEXT:    sel z2.s, p2, z2.s, z6.s140; NOBF16-NEXT:    sel z1.s, p3, z1.s, z7.s141; NOBF16-NEXT:    sel z0.s, p0, z0.s, z4.s142; NOBF16-NEXT:    lsr z3.s, z3.s, #16143; NOBF16-NEXT:    lsr z2.s, z2.s, #16144; NOBF16-NEXT:    lsr z1.s, z1.s, #16145; NOBF16-NEXT:    lsr z0.s, z0.s, #16146; NOBF16-NEXT:    uzp1 z2.s, z2.s, z3.s147; NOBF16-NEXT:    uzp1 z0.s, z0.s, z1.s148; NOBF16-NEXT:    uzp1 z0.h, z0.h, z2.h149; NOBF16-NEXT:    ret150;151; NOBF16NNAN-LABEL: fptrunc_nxv8f64_to_nxv8bf16:152; NOBF16NNAN:       // %bb.0:153; NOBF16NNAN-NEXT:    ptrue p0.d154; NOBF16NNAN-NEXT:    mov z4.s, #32767 // =0x7fff155; NOBF16NNAN-NEXT:    fcvtx z3.s, p0/m, z3.d156; NOBF16NNAN-NEXT:    fcvtx z2.s, p0/m, z2.d157; NOBF16NNAN-NEXT:    fcvtx z1.s, p0/m, z1.d158; NOBF16NNAN-NEXT:    fcvtx z0.s, p0/m, z0.d159; NOBF16NNAN-NEXT:    lsr z5.s, z3.s, #16160; NOBF16NNAN-NEXT:    lsr z6.s, z2.s, #16161; NOBF16NNAN-NEXT:    lsr z7.s, z1.s, #16162; NOBF16NNAN-NEXT:    lsr z24.s, z0.s, #16163; NOBF16NNAN-NEXT:    add z3.s, z3.s, z4.s164; NOBF16NNAN-NEXT:    add z2.s, z2.s, z4.s165; NOBF16NNAN-NEXT:    add z1.s, z1.s, z4.s166; NOBF16NNAN-NEXT:    add z0.s, z0.s, z4.s167; NOBF16NNAN-NEXT:    and z5.s, z5.s, #0x1168; NOBF16NNAN-NEXT:    and z6.s, z6.s, #0x1169; NOBF16NNAN-NEXT:    and z7.s, z7.s, #0x1170; NOBF16NNAN-NEXT:    and z24.s, z24.s, #0x1171; NOBF16NNAN-NEXT:    add z3.s, z5.s, z3.s172; NOBF16NNAN-NEXT:    add z2.s, z6.s, z2.s173; NOBF16NNAN-NEXT:    add z1.s, z7.s, z1.s174; NOBF16NNAN-NEXT:    add z0.s, z24.s, z0.s175; NOBF16NNAN-NEXT:    lsr z3.s, z3.s, #16176; NOBF16NNAN-NEXT:    lsr z2.s, z2.s, #16177; NOBF16NNAN-NEXT:    lsr z1.s, z1.s, #16178; NOBF16NNAN-NEXT:    lsr z0.s, z0.s, #16179; NOBF16NNAN-NEXT:    uzp1 z2.s, z2.s, z3.s180; NOBF16NNAN-NEXT:    uzp1 z0.s, z0.s, z1.s181; NOBF16NNAN-NEXT:    uzp1 z0.h, z0.h, z2.h182; NOBF16NNAN-NEXT:    ret183;184; BF16-LABEL: fptrunc_nxv8f64_to_nxv8bf16:185; BF16:       // %bb.0:186; BF16-NEXT:    ptrue p0.d187; BF16-NEXT:    fcvtx z3.s, p0/m, z3.d188; BF16-NEXT:    fcvtx z2.s, p0/m, z2.d189; BF16-NEXT:    fcvtx z1.s, p0/m, z1.d190; BF16-NEXT:    fcvtx z0.s, p0/m, z0.d191; BF16-NEXT:    bfcvt z3.h, p0/m, z3.s192; BF16-NEXT:    bfcvt z2.h, p0/m, z2.s193; BF16-NEXT:    bfcvt z1.h, p0/m, z1.s194; BF16-NEXT:    bfcvt z0.h, p0/m, z0.s195; BF16-NEXT:    uzp1 z2.s, z2.s, z3.s196; BF16-NEXT:    uzp1 z0.s, z0.s, z1.s197; BF16-NEXT:    uzp1 z0.h, z0.h, z2.h198; BF16-NEXT:    ret199  %res = fptrunc <vscale x 8 x double> %a to <vscale x 8 x bfloat>200  ret <vscale x 8 x bfloat> %res201}202