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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck --check-prefix=SVE %s3; RUN: llc -mtriple=aarch64 -mattr=+sve2 < %s -o - | FileCheck --check-prefix=SVE2 %s4 5define <vscale x 16 x i8> @eor3_nxv16i8_left(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {6; SVE-LABEL: eor3_nxv16i8_left:7; SVE: // %bb.0:8; SVE-NEXT: eor z0.d, z0.d, z1.d9; SVE-NEXT: eor z0.d, z0.d, z2.d10; SVE-NEXT: ret11;12; SVE2-LABEL: eor3_nxv16i8_left:13; SVE2: // %bb.0:14; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d15; SVE2-NEXT: ret16 %4 = xor <vscale x 16 x i8> %0, %117 %5 = xor <vscale x 16 x i8> %4, %218 ret <vscale x 16 x i8> %519}20 21define <vscale x 16 x i8> @eor3_nxv16i8_right(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {22; SVE-LABEL: eor3_nxv16i8_right:23; SVE: // %bb.0:24; SVE-NEXT: eor z0.d, z0.d, z1.d25; SVE-NEXT: eor z0.d, z2.d, z0.d26; SVE-NEXT: ret27;28; SVE2-LABEL: eor3_nxv16i8_right:29; SVE2: // %bb.0:30; SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z1.d31; SVE2-NEXT: mov z0.d, z2.d32; SVE2-NEXT: ret33 %4 = xor <vscale x 16 x i8> %0, %134 %5 = xor <vscale x 16 x i8> %2, %435 ret <vscale x 16 x i8> %536}37 38define <vscale x 8 x i16> @eor3_nxv8i16_left(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2) {39; SVE-LABEL: eor3_nxv8i16_left:40; SVE: // %bb.0:41; SVE-NEXT: eor z0.d, z0.d, z1.d42; SVE-NEXT: eor z0.d, z0.d, z2.d43; SVE-NEXT: ret44;45; SVE2-LABEL: eor3_nxv8i16_left:46; SVE2: // %bb.0:47; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d48; SVE2-NEXT: ret49 %4 = xor <vscale x 8 x i16> %0, %150 %5 = xor <vscale x 8 x i16> %4, %251 ret <vscale x 8 x i16> %552}53 54define <vscale x 8 x i16> @eor3_nxv8i16_right(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2) {55; SVE-LABEL: eor3_nxv8i16_right:56; SVE: // %bb.0:57; SVE-NEXT: eor z0.d, z0.d, z1.d58; SVE-NEXT: eor z0.d, z2.d, z0.d59; SVE-NEXT: ret60;61; SVE2-LABEL: eor3_nxv8i16_right:62; SVE2: // %bb.0:63; SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z1.d64; SVE2-NEXT: mov z0.d, z2.d65; SVE2-NEXT: ret66 %4 = xor <vscale x 8 x i16> %0, %167 %5 = xor <vscale x 8 x i16> %2, %468 ret <vscale x 8 x i16> %569}70 71define <vscale x 4 x i32> @eor3_nxv4i32_left(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2) {72; SVE-LABEL: eor3_nxv4i32_left:73; SVE: // %bb.0:74; SVE-NEXT: eor z0.d, z0.d, z1.d75; SVE-NEXT: eor z0.d, z0.d, z2.d76; SVE-NEXT: ret77;78; SVE2-LABEL: eor3_nxv4i32_left:79; SVE2: // %bb.0:80; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d81; SVE2-NEXT: ret82 %4 = xor <vscale x 4 x i32> %0, %183 %5 = xor <vscale x 4 x i32> %4, %284 ret <vscale x 4 x i32> %585}86 87define <vscale x 4 x i32> @eor3_nxv4i32_right(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2) {88; SVE-LABEL: eor3_nxv4i32_right:89; SVE: // %bb.0:90; SVE-NEXT: eor z0.d, z0.d, z1.d91; SVE-NEXT: eor z0.d, z2.d, z0.d92; SVE-NEXT: ret93;94; SVE2-LABEL: eor3_nxv4i32_right:95; SVE2: // %bb.0:96; SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z1.d97; SVE2-NEXT: mov z0.d, z2.d98; SVE2-NEXT: ret99 %4 = xor <vscale x 4 x i32> %0, %1100 %5 = xor <vscale x 4 x i32> %2, %4101 ret <vscale x 4 x i32> %5102}103 104define <vscale x 2 x i64> @eor3_nxv2i64_left(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2) {105; SVE-LABEL: eor3_nxv2i64_left:106; SVE: // %bb.0:107; SVE-NEXT: eor z0.d, z0.d, z1.d108; SVE-NEXT: eor z0.d, z0.d, z2.d109; SVE-NEXT: ret110;111; SVE2-LABEL: eor3_nxv2i64_left:112; SVE2: // %bb.0:113; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d114; SVE2-NEXT: ret115 %4 = xor <vscale x 2 x i64> %0, %1116 %5 = xor <vscale x 2 x i64> %4, %2117 ret <vscale x 2 x i64> %5118}119 120define <vscale x 2 x i64> @eor3_nxv2i64_right(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2) {121; SVE-LABEL: eor3_nxv2i64_right:122; SVE: // %bb.0:123; SVE-NEXT: eor z0.d, z0.d, z1.d124; SVE-NEXT: eor z0.d, z2.d, z0.d125; SVE-NEXT: ret126;127; SVE2-LABEL: eor3_nxv2i64_right:128; SVE2: // %bb.0:129; SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z1.d130; SVE2-NEXT: mov z0.d, z2.d131; SVE2-NEXT: ret132 %4 = xor <vscale x 2 x i64> %0, %1133 %5 = xor <vscale x 2 x i64> %2, %4134 ret <vscale x 2 x i64> %5135}136 137define <vscale x 2 x i64> @eor3_vnot(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1) {138; SVE-LABEL: eor3_vnot:139; SVE: // %bb.0:140; SVE-NEXT: eor z0.d, z0.d, z1.d141; SVE-NEXT: ret142;143; SVE2-LABEL: eor3_vnot:144; SVE2: // %bb.0:145; SVE2-NEXT: eor z0.d, z0.d, z1.d146; SVE2-NEXT: ret147 %3 = xor <vscale x 2 x i64> %0, zeroinitializer148 %4 = xor <vscale x 2 x i64> %3, %1149 ret <vscale x 2 x i64> %4150}151 152