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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_2563; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5124; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_5125 6 7target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"8 9target triple = "aarch64-unknown-linux-gnu"10 11;============ f1612 13define void @test_copysign_v4f16_v4f16(ptr %ap, ptr %bp) vscale_range(2,0) #0 {14; CHECK-LABEL: test_copysign_v4f16_v4f16:15; CHECK: // %bb.0:16; CHECK-NEXT: mvni v0.4h, #128, lsl #817; CHECK-NEXT: ldr d1, [x0]18; CHECK-NEXT: ldr d2, [x1]19; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b20; CHECK-NEXT: str d0, [x0]21; CHECK-NEXT: ret22 %a = load <4 x half>, ptr %ap23 %b = load <4 x half>, ptr %bp24 %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b)25 store <4 x half> %r, ptr %ap26 ret void27}28 29define void @test_copysign_v8f16_v8f16(ptr %ap, ptr %bp) vscale_range(2,0) #0 {30; CHECK-LABEL: test_copysign_v8f16_v8f16:31; CHECK: // %bb.0:32; CHECK-NEXT: mvni v0.8h, #128, lsl #833; CHECK-NEXT: ldr q1, [x0]34; CHECK-NEXT: ldr q2, [x1]35; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b36; CHECK-NEXT: str q0, [x0]37; CHECK-NEXT: ret38 %a = load <8 x half>, ptr %ap39 %b = load <8 x half>, ptr %bp40 %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b)41 store <8 x half> %r, ptr %ap42 ret void43}44 45define void @test_copysign_v16f16_v16f16(ptr %ap, ptr %bp) vscale_range(2,0) #0 {46; CHECK-LABEL: test_copysign_v16f16_v16f16:47; CHECK: // %bb.0:48; CHECK-NEXT: ptrue p0.h, vl1649; CHECK-NEXT: mov z0.h, #32767 // =0x7fff50; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0]51; CHECK-NEXT: ld1h { z2.h }, p0/z, [x1]52; CHECK-NEXT: bsl z1.d, z1.d, z2.d, z0.d53; CHECK-NEXT: st1h { z1.h }, p0, [x0]54; CHECK-NEXT: ret55 %a = load <16 x half>, ptr %ap56 %b = load <16 x half>, ptr %bp57 %r = call <16 x half> @llvm.copysign.v16f16(<16 x half> %a, <16 x half> %b)58 store <16 x half> %r, ptr %ap59 ret void60}61 62define void @test_copysign_v32f16_v32f16(ptr %ap, ptr %bp) #0 {63; VBITS_GE_256-LABEL: test_copysign_v32f16_v32f16:64; VBITS_GE_256: // %bb.0:65; VBITS_GE_256-NEXT: ptrue p0.h, vl1666; VBITS_GE_256-NEXT: mov x8, #16 // =0x1067; VBITS_GE_256-NEXT: mov z0.h, #32767 // =0x7fff68; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1]69; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x1, x8, lsl #1]70; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x0]71; VBITS_GE_256-NEXT: ld1h { z4.h }, p0/z, [x1]72; VBITS_GE_256-NEXT: bsl z1.d, z1.d, z2.d, z0.d73; VBITS_GE_256-NEXT: bsl z3.d, z3.d, z4.d, z0.d74; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0, x8, lsl #1]75; VBITS_GE_256-NEXT: st1h { z3.h }, p0, [x0]76; VBITS_GE_256-NEXT: ret77;78; VBITS_GE_512-LABEL: test_copysign_v32f16_v32f16:79; VBITS_GE_512: // %bb.0:80; VBITS_GE_512-NEXT: ptrue p0.h, vl3281; VBITS_GE_512-NEXT: mov z0.h, #32767 // =0x7fff82; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x0]83; VBITS_GE_512-NEXT: ld1h { z2.h }, p0/z, [x1]84; VBITS_GE_512-NEXT: bsl z1.d, z1.d, z2.d, z0.d85; VBITS_GE_512-NEXT: st1h { z1.h }, p0, [x0]86; VBITS_GE_512-NEXT: ret87 %a = load <32 x half>, ptr %ap88 %b = load <32 x half>, ptr %bp89 %r = call <32 x half> @llvm.copysign.v32f16(<32 x half> %a, <32 x half> %b)90 store <32 x half> %r, ptr %ap91 ret void92}93 94define void @test_copysign_v64f16_v64f16(ptr %ap, ptr %bp) vscale_range(8,0) #0 {95; CHECK-LABEL: test_copysign_v64f16_v64f16:96; CHECK: // %bb.0:97; CHECK-NEXT: ptrue p0.h, vl6498; CHECK-NEXT: mov z0.h, #32767 // =0x7fff99; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0]100; CHECK-NEXT: ld1h { z2.h }, p0/z, [x1]101; CHECK-NEXT: bsl z1.d, z1.d, z2.d, z0.d102; CHECK-NEXT: st1h { z1.h }, p0, [x0]103; CHECK-NEXT: ret104 %a = load <64 x half>, ptr %ap105 %b = load <64 x half>, ptr %bp106 %r = call <64 x half> @llvm.copysign.v64f16(<64 x half> %a, <64 x half> %b)107 store <64 x half> %r, ptr %ap108 ret void109}110 111define void @test_copysign_v128f16_v128f16(ptr %ap, ptr %bp) vscale_range(16,0) #0 {112; CHECK-LABEL: test_copysign_v128f16_v128f16:113; CHECK: // %bb.0:114; CHECK-NEXT: ptrue p0.h, vl128115; CHECK-NEXT: mov z0.h, #32767 // =0x7fff116; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0]117; CHECK-NEXT: ld1h { z2.h }, p0/z, [x1]118; CHECK-NEXT: bsl z1.d, z1.d, z2.d, z0.d119; CHECK-NEXT: st1h { z1.h }, p0, [x0]120; CHECK-NEXT: ret121 %a = load <128 x half>, ptr %ap122 %b = load <128 x half>, ptr %bp123 %r = call <128 x half> @llvm.copysign.v128f16(<128 x half> %a, <128 x half> %b)124 store <128 x half> %r, ptr %ap125 ret void126}127 128;============ f32129 130define void @test_copysign_v2f32_v2f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {131; CHECK-LABEL: test_copysign_v2f32_v2f32:132; CHECK: // %bb.0:133; CHECK-NEXT: mvni v0.2s, #128, lsl #24134; CHECK-NEXT: ldr d1, [x0]135; CHECK-NEXT: ldr d2, [x1]136; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b137; CHECK-NEXT: str d0, [x0]138; CHECK-NEXT: ret139 %a = load <2 x float>, ptr %ap140 %b = load <2 x float>, ptr %bp141 %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b)142 store <2 x float> %r, ptr %ap143 ret void144}145 146define void @test_copysign_v4f32_v4f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {147; CHECK-LABEL: test_copysign_v4f32_v4f32:148; CHECK: // %bb.0:149; CHECK-NEXT: mvni v0.4s, #128, lsl #24150; CHECK-NEXT: ldr q1, [x0]151; CHECK-NEXT: ldr q2, [x1]152; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b153; CHECK-NEXT: str q0, [x0]154; CHECK-NEXT: ret155 %a = load <4 x float>, ptr %ap156 %b = load <4 x float>, ptr %bp157 %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b)158 store <4 x float> %r, ptr %ap159 ret void160}161 162define void @test_copysign_v8f32_v8f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {163; CHECK-LABEL: test_copysign_v8f32_v8f32:164; CHECK: // %bb.0:165; CHECK-NEXT: ptrue p0.s, vl8166; CHECK-NEXT: mov z0.s, #0x7fffffff167; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0]168; CHECK-NEXT: ld1w { z2.s }, p0/z, [x1]169; CHECK-NEXT: bsl z1.d, z1.d, z2.d, z0.d170; CHECK-NEXT: st1w { z1.s }, p0, [x0]171; CHECK-NEXT: ret172 %a = load <8 x float>, ptr %ap173 %b = load <8 x float>, ptr %bp174 %r = call <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b)175 store <8 x float> %r, ptr %ap176 ret void177}178 179define void @test_copysign_v16f32_v16f32(ptr %ap, ptr %bp) #0 {180; VBITS_GE_256-LABEL: test_copysign_v16f32_v16f32:181; VBITS_GE_256: // %bb.0:182; VBITS_GE_256-NEXT: ptrue p0.s, vl8183; VBITS_GE_256-NEXT: mov x8, #8 // =0x8184; VBITS_GE_256-NEXT: mov z0.s, #0x7fffffff185; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]186; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x1, x8, lsl #2]187; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x0]188; VBITS_GE_256-NEXT: ld1w { z4.s }, p0/z, [x1]189; VBITS_GE_256-NEXT: bsl z1.d, z1.d, z2.d, z0.d190; VBITS_GE_256-NEXT: bsl z3.d, z3.d, z4.d, z0.d191; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]192; VBITS_GE_256-NEXT: st1w { z3.s }, p0, [x0]193; VBITS_GE_256-NEXT: ret194;195; VBITS_GE_512-LABEL: test_copysign_v16f32_v16f32:196; VBITS_GE_512: // %bb.0:197; VBITS_GE_512-NEXT: ptrue p0.s, vl16198; VBITS_GE_512-NEXT: mov z0.s, #0x7fffffff199; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x0]200; VBITS_GE_512-NEXT: ld1w { z2.s }, p0/z, [x1]201; VBITS_GE_512-NEXT: bsl z1.d, z1.d, z2.d, z0.d202; VBITS_GE_512-NEXT: st1w { z1.s }, p0, [x0]203; VBITS_GE_512-NEXT: ret204 %a = load <16 x float>, ptr %ap205 %b = load <16 x float>, ptr %bp206 %r = call <16 x float> @llvm.copysign.v16f32(<16 x float> %a, <16 x float> %b)207 store <16 x float> %r, ptr %ap208 ret void209}210 211define void @test_copysign_v32f32_v32f32(ptr %ap, ptr %bp) vscale_range(8,0) #0 {212; CHECK-LABEL: test_copysign_v32f32_v32f32:213; CHECK: // %bb.0:214; CHECK-NEXT: ptrue p0.s, vl32215; CHECK-NEXT: mov z0.s, #0x7fffffff216; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0]217; CHECK-NEXT: ld1w { z2.s }, p0/z, [x1]218; CHECK-NEXT: bsl z1.d, z1.d, z2.d, z0.d219; CHECK-NEXT: st1w { z1.s }, p0, [x0]220; CHECK-NEXT: ret221 %a = load <32 x float>, ptr %ap222 %b = load <32 x float>, ptr %bp223 %r = call <32 x float> @llvm.copysign.v32f32(<32 x float> %a, <32 x float> %b)224 store <32 x float> %r, ptr %ap225 ret void226}227 228define void @test_copysign_v64f32_v64f32(ptr %ap, ptr %bp) vscale_range(16,0) #0 {229; CHECK-LABEL: test_copysign_v64f32_v64f32:230; CHECK: // %bb.0:231; CHECK-NEXT: ptrue p0.s, vl64232; CHECK-NEXT: mov z0.s, #0x7fffffff233; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0]234; CHECK-NEXT: ld1w { z2.s }, p0/z, [x1]235; CHECK-NEXT: bsl z1.d, z1.d, z2.d, z0.d236; CHECK-NEXT: st1w { z1.s }, p0, [x0]237; CHECK-NEXT: ret238 %a = load <64 x float>, ptr %ap239 %b = load <64 x float>, ptr %bp240 %r = call <64 x float> @llvm.copysign.v64f32(<64 x float> %a, <64 x float> %b)241 store <64 x float> %r, ptr %ap242 ret void243}244 245;============ f64246 247define void @test_copysign_v2f64_v2f64(ptr %ap, ptr %bp) vscale_range(2,0) #0 {248; CHECK-LABEL: test_copysign_v2f64_v2f64:249; CHECK: // %bb.0:250; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff251; CHECK-NEXT: ldr q1, [x0]252; CHECK-NEXT: ldr q2, [x1]253; CHECK-NEXT: fneg v0.2d, v0.2d254; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b255; CHECK-NEXT: str q0, [x0]256; CHECK-NEXT: ret257 %a = load <2 x double>, ptr %ap258 %b = load <2 x double>, ptr %bp259 %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b)260 store <2 x double> %r, ptr %ap261 ret void262}263 264define void @test_copysign_v4f64_v4f64(ptr %ap, ptr %bp) vscale_range(2,0) #0 {265; CHECK-LABEL: test_copysign_v4f64_v4f64:266; CHECK: // %bb.0:267; CHECK-NEXT: ptrue p0.d, vl4268; CHECK-NEXT: mov z0.d, #0x7fffffffffffffff269; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]270; CHECK-NEXT: ld1d { z2.d }, p0/z, [x1]271; CHECK-NEXT: bsl z1.d, z1.d, z2.d, z0.d272; CHECK-NEXT: st1d { z1.d }, p0, [x0]273; CHECK-NEXT: ret274 %a = load <4 x double>, ptr %ap275 %b = load <4 x double>, ptr %bp276 %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b)277 store <4 x double> %r, ptr %ap278 ret void279}280 281define void @test_copysign_v8f64_v8f64(ptr %ap, ptr %bp) #0 {282; VBITS_GE_256-LABEL: test_copysign_v8f64_v8f64:283; VBITS_GE_256: // %bb.0:284; VBITS_GE_256-NEXT: ptrue p0.d, vl4285; VBITS_GE_256-NEXT: mov x8, #4 // =0x4286; VBITS_GE_256-NEXT: mov z0.d, #0x7fffffffffffffff287; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0, x8, lsl #3]288; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x1, x8, lsl #3]289; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x0]290; VBITS_GE_256-NEXT: ld1d { z4.d }, p0/z, [x1]291; VBITS_GE_256-NEXT: bsl z1.d, z1.d, z2.d, z0.d292; VBITS_GE_256-NEXT: bsl z3.d, z3.d, z4.d, z0.d293; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0, x8, lsl #3]294; VBITS_GE_256-NEXT: st1d { z3.d }, p0, [x0]295; VBITS_GE_256-NEXT: ret296;297; VBITS_GE_512-LABEL: test_copysign_v8f64_v8f64:298; VBITS_GE_512: // %bb.0:299; VBITS_GE_512-NEXT: ptrue p0.d, vl8300; VBITS_GE_512-NEXT: mov z0.d, #0x7fffffffffffffff301; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x0]302; VBITS_GE_512-NEXT: ld1d { z2.d }, p0/z, [x1]303; VBITS_GE_512-NEXT: bsl z1.d, z1.d, z2.d, z0.d304; VBITS_GE_512-NEXT: st1d { z1.d }, p0, [x0]305; VBITS_GE_512-NEXT: ret306 %a = load <8 x double>, ptr %ap307 %b = load <8 x double>, ptr %bp308 %r = call <8 x double> @llvm.copysign.v8f64(<8 x double> %a, <8 x double> %b)309 store <8 x double> %r, ptr %ap310 ret void311}312 313define void @test_copysign_v16f64_v16f64(ptr %ap, ptr %bp) vscale_range(8,0) #0 {314; CHECK-LABEL: test_copysign_v16f64_v16f64:315; CHECK: // %bb.0:316; CHECK-NEXT: ptrue p0.d, vl16317; CHECK-NEXT: mov z0.d, #0x7fffffffffffffff318; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]319; CHECK-NEXT: ld1d { z2.d }, p0/z, [x1]320; CHECK-NEXT: bsl z1.d, z1.d, z2.d, z0.d321; CHECK-NEXT: st1d { z1.d }, p0, [x0]322; CHECK-NEXT: ret323 %a = load <16 x double>, ptr %ap324 %b = load <16 x double>, ptr %bp325 %r = call <16 x double> @llvm.copysign.v16f64(<16 x double> %a, <16 x double> %b)326 store <16 x double> %r, ptr %ap327 ret void328}329 330define void @test_copysign_v32f64_v32f64(ptr %ap, ptr %bp) vscale_range(16,0) #0 {331; CHECK-LABEL: test_copysign_v32f64_v32f64:332; CHECK: // %bb.0:333; CHECK-NEXT: ptrue p0.d, vl32334; CHECK-NEXT: mov z0.d, #0x7fffffffffffffff335; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]336; CHECK-NEXT: ld1d { z2.d }, p0/z, [x1]337; CHECK-NEXT: bsl z1.d, z1.d, z2.d, z0.d338; CHECK-NEXT: st1d { z1.d }, p0, [x0]339; CHECK-NEXT: ret340 %a = load <32 x double>, ptr %ap341 %b = load <32 x double>, ptr %bp342 %r = call <32 x double> @llvm.copysign.v32f64(<32 x double> %a, <32 x double> %b)343 store <32 x double> %r, ptr %ap344 ret void345}346 347;============ v2f32348 349define void @test_copysign_v2f32_v2f64(ptr %ap, ptr %bp) vscale_range(2,0) #0 {350; CHECK-LABEL: test_copysign_v2f32_v2f64:351; CHECK: // %bb.0:352; CHECK-NEXT: ldr q0, [x1]353; CHECK-NEXT: mvni v1.2s, #128, lsl #24354; CHECK-NEXT: ldr d2, [x0]355; CHECK-NEXT: fcvtn v0.2s, v0.2d356; CHECK-NEXT: bit v0.8b, v2.8b, v1.8b357; CHECK-NEXT: str d0, [x0]358; CHECK-NEXT: ret359 %a = load <2 x float>, ptr %ap360 %b = load <2 x double>, ptr %bp361 %tmp0 = fptrunc <2 x double> %b to <2 x float>362 %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %tmp0)363 store <2 x float> %r, ptr %ap364 ret void365}366 367;============ v4f32368 369; SplitVecOp #1370define void @test_copysign_v4f32_v4f64(ptr %ap, ptr %bp) vscale_range(2,0) #0 {371; CHECK-LABEL: test_copysign_v4f32_v4f64:372; CHECK: // %bb.0:373; CHECK-NEXT: ptrue p0.d, vl4374; CHECK-NEXT: mvni v1.4s, #128, lsl #24375; CHECK-NEXT: ldr q2, [x0]376; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]377; CHECK-NEXT: ptrue p0.d378; CHECK-NEXT: fcvt z0.s, p0/m, z0.d379; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s380; CHECK-NEXT: bit v0.16b, v2.16b, v1.16b381; CHECK-NEXT: str q0, [x0]382; CHECK-NEXT: ret383 %a = load <4 x float>, ptr %ap384 %b = load <4 x double>, ptr %bp385 %tmp0 = fptrunc <4 x double> %b to <4 x float>386 %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %tmp0)387 store <4 x float> %r, ptr %ap388 ret void389}390 391;============ v2f64392 393define void @test_copysign_v2f64_v2f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {394; CHECK-LABEL: test_copysign_v2f64_v2f32:395; CHECK: // %bb.0:396; CHECK-NEXT: movi v0.2d, #0xffffffffffffffff397; CHECK-NEXT: ldr d1, [x1]398; CHECK-NEXT: ldr q2, [x0]399; CHECK-NEXT: fcvtl v1.2d, v1.2s400; CHECK-NEXT: fneg v0.2d, v0.2d401; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b402; CHECK-NEXT: str q0, [x0]403; CHECK-NEXT: ret404 %a = load <2 x double>, ptr %ap405 %b = load < 2 x float>, ptr %bp406 %tmp0 = fpext <2 x float> %b to <2 x double>407 %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %tmp0)408 store <2 x double> %r, ptr %ap409 ret void410}411 412;============ v4f64413 414; SplitVecRes mismatched415define void @test_copysign_v4f64_v4f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {416; CHECK-LABEL: test_copysign_v4f64_v4f32:417; CHECK: // %bb.0:418; CHECK-NEXT: ptrue p0.d, vl4419; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff420; CHECK-NEXT: ld1w { z0.d }, p0/z, [x1]421; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]422; CHECK-NEXT: fcvt z0.d, p0/m, z0.s423; CHECK-NEXT: bsl z2.d, z2.d, z0.d, z1.d424; CHECK-NEXT: st1d { z2.d }, p0, [x0]425; CHECK-NEXT: ret426 %a = load <4 x double>, ptr %ap427 %b = load <4 x float>, ptr %bp428 %tmp0 = fpext <4 x float> %b to <4 x double>429 %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %tmp0)430 store <4 x double> %r, ptr %ap431 ret void432}433 434;============ v4f16435 436define void @test_copysign_v4f16_v4f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {437; CHECK-LABEL: test_copysign_v4f16_v4f32:438; CHECK: // %bb.0:439; CHECK-NEXT: ldr q0, [x1]440; CHECK-NEXT: mvni v1.4h, #128, lsl #8441; CHECK-NEXT: ldr d2, [x0]442; CHECK-NEXT: fcvtn v0.4h, v0.4s443; CHECK-NEXT: bit v0.8b, v2.8b, v1.8b444; CHECK-NEXT: str d0, [x0]445; CHECK-NEXT: ret446 %a = load <4 x half>, ptr %ap447 %b = load <4 x float>, ptr %bp448 %tmp0 = fptrunc <4 x float> %b to <4 x half>449 %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0)450 store <4 x half> %r, ptr %ap451 ret void452}453 454define void @test_copysign_v4f16_v4f64(ptr %ap, ptr %bp) vscale_range(2,0) #0 {455; CHECK-LABEL: test_copysign_v4f16_v4f64:456; CHECK: // %bb.0:457; CHECK-NEXT: ptrue p0.d, vl4458; CHECK-NEXT: mvni v1.4h, #128, lsl #8459; CHECK-NEXT: ldr d2, [x0]460; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]461; CHECK-NEXT: ptrue p0.d462; CHECK-NEXT: fcvt z0.h, p0/m, z0.d463; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s464; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h465; CHECK-NEXT: bit v0.8b, v2.8b, v1.8b466; CHECK-NEXT: str d0, [x0]467; CHECK-NEXT: ret468 %a = load <4 x half>, ptr %ap469 %b = load <4 x double>, ptr %bp470 %tmp0 = fptrunc <4 x double> %b to <4 x half>471 %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0)472 store <4 x half> %r, ptr %ap473 ret void474}475 476declare <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b) #0477 478;============ v8f16479 480 481define void @test_copysign_v8f16_v8f32(ptr %ap, ptr %bp) vscale_range(2,0) #0 {482; CHECK-LABEL: test_copysign_v8f16_v8f32:483; CHECK: // %bb.0:484; CHECK-NEXT: ptrue p0.s, vl8485; CHECK-NEXT: mvni v1.8h, #128, lsl #8486; CHECK-NEXT: ldr q2, [x0]487; CHECK-NEXT: ld1w { z0.s }, p0/z, [x1]488; CHECK-NEXT: ptrue p0.s489; CHECK-NEXT: fcvt z0.h, p0/m, z0.s490; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h491; CHECK-NEXT: bit v0.16b, v2.16b, v1.16b492; CHECK-NEXT: str q0, [x0]493; CHECK-NEXT: ret494 %a = load <8 x half>, ptr %ap495 %b = load <8 x float>, ptr %bp496 %tmp0 = fptrunc <8 x float> %b to <8 x half>497 %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %tmp0)498 store <8 x half> %r, ptr %ap499 ret void500}501 502declare <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b) #0503declare <16 x half> @llvm.copysign.v16f16(<16 x half> %a, <16 x half> %b) #0504declare <32 x half> @llvm.copysign.v32f16(<32 x half> %a, <32 x half> %b) #0505declare <64 x half> @llvm.copysign.v64f16(<64 x half> %a, <64 x half> %b) #0506declare <128 x half> @llvm.copysign.v128f16(<128 x half> %a, <128 x half> %b) #0507 508declare <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b) #0509declare <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) #0510declare <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b) #0511declare <16 x float> @llvm.copysign.v16f32(<16 x float> %a, <16 x float> %b) #0512declare <32 x float> @llvm.copysign.v32f32(<32 x float> %a, <32 x float> %b) #0513declare <64 x float> @llvm.copysign.v64f32(<64 x float> %a, <64 x float> %b) #0514 515declare <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) #0516declare <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) #0517declare <8 x double> @llvm.copysign.v8f64(<8 x double> %a, <8 x double> %b) #0518declare <16 x double> @llvm.copysign.v16f64(<16 x double> %a, <16 x double> %b) #0519declare <32 x double> @llvm.copysign.v32f64(<32 x double> %a, <32 x double> %b) #0520 521attributes #0 = { "target-features"="+sve2" }522