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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3 4;5; MUL with SPLAT6;7define <vscale x 8 x i16> @mul_i16_imm(<vscale x 8 x i16> %a) {8; CHECK-LABEL: mul_i16_imm:9; CHECK: // %bb.0:10; CHECK-NEXT: mov z1.h, #255 // =0xff11; CHECK-NEXT: mul z0.h, z0.h, z1.h12; CHECK-NEXT: ret13 %res = mul <vscale x 8 x i16> %a, splat(i16 255)14 ret <vscale x 8 x i16> %res15}16 17define <vscale x 8 x i16> @mul_i16_imm_neg(<vscale x 8 x i16> %a) {18; CHECK-LABEL: mul_i16_imm_neg:19; CHECK: // %bb.0:20; CHECK-NEXT: mov w8, #-20021; CHECK-NEXT: mov z1.h, w822; CHECK-NEXT: mul z0.h, z0.h, z1.h23; CHECK-NEXT: ret24 %res = mul <vscale x 8 x i16> %a, splat(i16 -200)25 ret <vscale x 8 x i16> %res26}27 28define <vscale x 4 x i32> @mul_i32_imm(<vscale x 4 x i32> %a) {29; CHECK-LABEL: mul_i32_imm:30; CHECK: // %bb.0:31; CHECK-NEXT: mov z1.s, #255 // =0xff32; CHECK-NEXT: mul z0.s, z0.s, z1.s33; CHECK-NEXT: ret34 %res = mul <vscale x 4 x i32> %a, splat(i32 255)35 ret <vscale x 4 x i32> %res36}37 38define <vscale x 4 x i32> @mul_i32_imm_neg(<vscale x 4 x i32> %a) {39; CHECK-LABEL: mul_i32_imm_neg:40; CHECK: // %bb.0:41; CHECK-NEXT: mov w8, #-20042; CHECK-NEXT: mov z1.s, w843; CHECK-NEXT: mul z0.s, z0.s, z1.s44; CHECK-NEXT: ret45 %res = mul <vscale x 4 x i32> %a, splat(i32 -200)46 ret <vscale x 4 x i32> %res47}48 49define <vscale x 2 x i64> @mul_i64_imm(<vscale x 2 x i64> %a) {50; CHECK-LABEL: mul_i64_imm:51; CHECK: // %bb.0:52; CHECK-NEXT: mov z1.d, #255 // =0xff53; CHECK-NEXT: mul z0.d, z0.d, z1.d54; CHECK-NEXT: ret55 %res = mul <vscale x 2 x i64> %a, splat(i64 255)56 ret <vscale x 2 x i64> %res57}58 59define <vscale x 2 x i64> @mul_i64_imm_neg(<vscale x 2 x i64> %a) {60; CHECK-LABEL: mul_i64_imm_neg:61; CHECK: // %bb.0:62; CHECK-NEXT: mov x8, #-20063; CHECK-NEXT: mov z1.d, x864; CHECK-NEXT: mul z0.d, z0.d, z1.d65; CHECK-NEXT: ret66 %res = mul <vscale x 2 x i64> %a, splat(i64 -200)67 ret <vscale x 2 x i64> %res68}69 70;71; MUL (vector, unpredicated)72;73define <vscale x 16 x i8> @mul_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {74; CHECK-LABEL: mul_i8:75; CHECK: // %bb.0:76; CHECK-NEXT: mul z0.b, z0.b, z1.b77; CHECK-NEXT: ret78 %res = mul <vscale x 16 x i8> %a, %b79 ret <vscale x 16 x i8> %res80}81 82define <vscale x 8 x i16> @mul_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {83; CHECK-LABEL: mul_i16:84; CHECK: // %bb.0:85; CHECK-NEXT: mul z0.h, z0.h, z1.h86; CHECK-NEXT: ret87 %res = mul <vscale x 8 x i16> %a, %b88 ret <vscale x 8 x i16> %res89}90 91define <vscale x 4 x i32> @mul_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {92; CHECK-LABEL: mul_i32:93; CHECK: // %bb.0:94; CHECK-NEXT: mul z0.s, z0.s, z1.s95; CHECK-NEXT: ret96 %res = mul <vscale x 4 x i32> %a, %b97 ret <vscale x 4 x i32> %res98}99 100define <vscale x 2 x i64> @mul_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {101; CHECK-LABEL: mul_i64:102; CHECK: // %bb.0:103; CHECK-NEXT: mul z0.d, z0.d, z1.d104; CHECK-NEXT: ret105 %res = mul <vscale x 2 x i64> %a, %b106 ret <vscale x 2 x i64> %res107}108 109;110; SMULH (vector, unpredicated)111;112define <vscale x 16 x i8> @smulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {113; CHECK-LABEL: smulh_i8:114; CHECK: // %bb.0:115; CHECK-NEXT: smulh z0.b, z0.b, z1.b116; CHECK-NEXT: ret117 %sel = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)118 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.smulh.u.nxv16i8(<vscale x 16 x i1> %sel, <vscale x 16 x i8> %a,119 <vscale x 16 x i8> %b)120 ret <vscale x 16 x i8> %res121}122 123define <vscale x 8 x i16> @smulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {124; CHECK-LABEL: smulh_i16:125; CHECK: // %bb.0:126; CHECK-NEXT: smulh z0.h, z0.h, z1.h127; CHECK-NEXT: ret128 %sel = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)129 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.smulh.u.nxv8i16(<vscale x 8 x i1> %sel, <vscale x 8 x i16> %a,130 <vscale x 8 x i16> %b)131 ret <vscale x 8 x i16> %res132}133 134define <vscale x 4 x i32> @smulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {135; CHECK-LABEL: smulh_i32:136; CHECK: // %bb.0:137; CHECK-NEXT: smulh z0.s, z0.s, z1.s138; CHECK-NEXT: ret139 %sel = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)140 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.u.nxv4i32(<vscale x 4 x i1> %sel, <vscale x 4 x i32> %a,141 <vscale x 4 x i32> %b)142 ret <vscale x 4 x i32> %res143}144 145define <vscale x 2 x i64> @smulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {146; CHECK-LABEL: smulh_i64:147; CHECK: // %bb.0:148; CHECK-NEXT: smulh z0.d, z0.d, z1.d149; CHECK-NEXT: ret150 %sel = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)151 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smulh.u.nxv2i64(<vscale x 2 x i1> %sel, <vscale x 2 x i64> %a,152 <vscale x 2 x i64> %b)153 ret <vscale x 2 x i64> %res154}155 156;157; UMULH (vector, unpredicated)158;159define <vscale x 16 x i8> @umulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {160; CHECK-LABEL: umulh_i8:161; CHECK: // %bb.0:162; CHECK-NEXT: umulh z0.b, z0.b, z1.b163; CHECK-NEXT: ret164 %sel = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)165 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.umulh.u.nxv16i8(<vscale x 16 x i1> %sel, <vscale x 16 x i8> %a,166 <vscale x 16 x i8> %b)167 ret <vscale x 16 x i8> %res168}169 170define <vscale x 8 x i16> @umulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {171; CHECK-LABEL: umulh_i16:172; CHECK: // %bb.0:173; CHECK-NEXT: umulh z0.h, z0.h, z1.h174; CHECK-NEXT: ret175 %sel = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)176 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.umulh.u.nxv8i16(<vscale x 8 x i1> %sel, <vscale x 8 x i16> %a,177 <vscale x 8 x i16> %b)178 ret <vscale x 8 x i16> %res179}180 181define <vscale x 4 x i32> @umulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {182; CHECK-LABEL: umulh_i32:183; CHECK: // %bb.0:184; CHECK-NEXT: umulh z0.s, z0.s, z1.s185; CHECK-NEXT: ret186 %sel = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)187 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umulh.u.nxv4i32(<vscale x 4 x i1> %sel, <vscale x 4 x i32> %a,188 <vscale x 4 x i32> %b)189 ret <vscale x 4 x i32> %res190}191 192define <vscale x 2 x i64> @umulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {193; CHECK-LABEL: umulh_i64:194; CHECK: // %bb.0:195; CHECK-NEXT: umulh z0.d, z0.d, z1.d196; CHECK-NEXT: ret197 %sel = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)198 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umulh.u.nxv2i64(<vscale x 2 x i1> %sel, <vscale x 2 x i64> %a,199 <vscale x 2 x i64> %b)200 ret <vscale x 2 x i64> %res201}202 203;204; PMUL (vector, unpredicated)205;206define <vscale x 16 x i8> @pmul_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {207; CHECK-LABEL: pmul_i8:208; CHECK: // %bb.0:209; CHECK-NEXT: pmul z0.b, z0.b, z1.b210; CHECK-NEXT: ret211 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.pmul.nxv16i8(<vscale x 16 x i8> %a,212 <vscale x 16 x i8> %b)213 ret <vscale x 16 x i8> %res214}215 216;217; SQDMULH (vector, unpredicated)218;219define <vscale x 16 x i8> @sqdmulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {220; CHECK-LABEL: sqdmulh_i8:221; CHECK: // %bb.0:222; CHECK-NEXT: sqdmulh z0.b, z0.b, z1.b223; CHECK-NEXT: ret224 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.sqdmulh.nxv16i8(<vscale x 16 x i8> %a,225 <vscale x 16 x i8> %b)226 ret <vscale x 16 x i8> %res227}228 229define <vscale x 8 x i16> @sqdmulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {230; CHECK-LABEL: sqdmulh_i16:231; CHECK: // %bb.0:232; CHECK-NEXT: sqdmulh z0.h, z0.h, z1.h233; CHECK-NEXT: ret234 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmulh.nxv8i16(<vscale x 8 x i16> %a,235 <vscale x 8 x i16> %b)236 ret <vscale x 8 x i16> %res237}238 239define <vscale x 4 x i32> @sqdmulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {240; CHECK-LABEL: sqdmulh_i32:241; CHECK: // %bb.0:242; CHECK-NEXT: sqdmulh z0.s, z0.s, z1.s243; CHECK-NEXT: ret244 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmulh.nxv4i32(<vscale x 4 x i32> %a,245 <vscale x 4 x i32> %b)246 ret <vscale x 4 x i32> %res247}248 249define <vscale x 2 x i64> @sqdmulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {250; CHECK-LABEL: sqdmulh_i64:251; CHECK: // %bb.0:252; CHECK-NEXT: sqdmulh z0.d, z0.d, z1.d253; CHECK-NEXT: ret254 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmulh.nxv2i64(<vscale x 2 x i64> %a,255 <vscale x 2 x i64> %b)256 ret <vscale x 2 x i64> %res257}258 259;260; SQRDMULH (vector, unpredicated)261;262define <vscale x 16 x i8> @sqrdmulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {263; CHECK-LABEL: sqrdmulh_i8:264; CHECK: // %bb.0:265; CHECK-NEXT: sqrdmulh z0.b, z0.b, z1.b266; CHECK-NEXT: ret267 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmulh.nxv16i8(<vscale x 16 x i8> %a,268 <vscale x 16 x i8> %b)269 ret <vscale x 16 x i8> %res270}271 272define <vscale x 8 x i16> @sqrdmulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {273; CHECK-LABEL: sqrdmulh_i16:274; CHECK: // %bb.0:275; CHECK-NEXT: sqrdmulh z0.h, z0.h, z1.h276; CHECK-NEXT: ret277 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmulh.nxv8i16(<vscale x 8 x i16> %a,278 <vscale x 8 x i16> %b)279 ret <vscale x 8 x i16> %res280}281 282define <vscale x 4 x i32> @sqrdmulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {283; CHECK-LABEL: sqrdmulh_i32:284; CHECK: // %bb.0:285; CHECK-NEXT: sqrdmulh z0.s, z0.s, z1.s286; CHECK-NEXT: ret287 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmulh.nxv4i32(<vscale x 4 x i32> %a,288 <vscale x 4 x i32> %b)289 ret <vscale x 4 x i32> %res290}291 292define <vscale x 2 x i64> @sqrdmulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {293; CHECK-LABEL: sqrdmulh_i64:294; CHECK: // %bb.0:295; CHECK-NEXT: sqrdmulh z0.d, z0.d, z1.d296; CHECK-NEXT: ret297 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmulh.nxv2i64(<vscale x 2 x i64> %a,298 <vscale x 2 x i64> %b)299 ret <vscale x 2 x i64> %res300}301 302declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)303declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)304declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)305declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)306declare <vscale x 16 x i8> @llvm.aarch64.sve.smulh.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)307declare <vscale x 8 x i16> @llvm.aarch64.sve.smulh.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)308declare <vscale x 4 x i32> @llvm.aarch64.sve.smulh.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)309declare <vscale x 2 x i64> @llvm.aarch64.sve.smulh.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)310declare <vscale x 16 x i8> @llvm.aarch64.sve.umulh.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)311declare <vscale x 8 x i16> @llvm.aarch64.sve.umulh.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)312declare <vscale x 4 x i32> @llvm.aarch64.sve.umulh.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)313declare <vscale x 2 x i64> @llvm.aarch64.sve.umulh.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)314declare <vscale x 16 x i8> @llvm.aarch64.sve.pmul.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)315declare <vscale x 16 x i8> @llvm.aarch64.sve.sqdmulh.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)316declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmulh.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)317declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmulh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)318declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmulh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)319declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmulh.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)320declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmulh.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)321declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmulh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)322declare <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmulh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)323