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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s3 4;5; SMULH6;7 8define <vscale x 16 x i8> @smulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {9; CHECK-LABEL: smulh_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: smulh z0.b, z0.b, z1.b12; CHECK-NEXT: ret13 %1 = sext <vscale x 16 x i8> %a to <vscale x 16 x i16>14 %2 = sext <vscale x 16 x i8> %b to <vscale x 16 x i16>15 %mul = mul <vscale x 16 x i16> %1, %216 %shr = lshr <vscale x 16 x i16> %mul, splat(i16 8)17 %tr = trunc <vscale x 16 x i16> %shr to <vscale x 16 x i8>18 ret <vscale x 16 x i8> %tr19}20 21define <vscale x 8 x i16> @smulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {22; CHECK-LABEL: smulh_i16:23; CHECK: // %bb.0:24; CHECK-NEXT: smulh z0.h, z0.h, z1.h25; CHECK-NEXT: ret26 %1 = sext <vscale x 8 x i16> %a to <vscale x 8 x i32>27 %2 = sext <vscale x 8 x i16> %b to <vscale x 8 x i32>28 %mul = mul <vscale x 8 x i32> %1, %229 %shr = lshr <vscale x 8 x i32> %mul, splat(i32 16)30 %tr = trunc <vscale x 8 x i32> %shr to <vscale x 8 x i16>31 ret <vscale x 8 x i16> %tr32}33 34define <vscale x 4 x i32> @smulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {35; CHECK-LABEL: smulh_i32:36; CHECK: // %bb.0:37; CHECK-NEXT: smulh z0.s, z0.s, z1.s38; CHECK-NEXT: ret39 %1 = sext <vscale x 4 x i32> %a to <vscale x 4 x i64>40 %2 = sext <vscale x 4 x i32> %b to <vscale x 4 x i64>41 %mul = mul <vscale x 4 x i64> %1, %242 %shr = lshr <vscale x 4 x i64> %mul, splat(i64 32)43 %tr = trunc <vscale x 4 x i64> %shr to <vscale x 4 x i32>44 ret <vscale x 4 x i32> %tr45}46 47define <vscale x 2 x i64> @smulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {48; CHECK-LABEL: smulh_i64:49; CHECK: // %bb.0:50; CHECK-NEXT: smulh z0.d, z0.d, z1.d51; CHECK-NEXT: ret52 %1 = sext <vscale x 2 x i64> %a to <vscale x 2 x i128>53 %2 = sext <vscale x 2 x i64> %b to <vscale x 2 x i128>54 %mul = mul <vscale x 2 x i128> %1, %255 %shr = lshr <vscale x 2 x i128> %mul, splat(i128 64)56 %tr = trunc <vscale x 2 x i128> %shr to <vscale x 2 x i64>57 ret <vscale x 2 x i64> %tr58}59 60;61; UMULH62;63 64define <vscale x 16 x i8> @umulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {65; CHECK-LABEL: umulh_i8:66; CHECK: // %bb.0:67; CHECK-NEXT: umulh z0.b, z0.b, z1.b68; CHECK-NEXT: ret69 %1 = zext <vscale x 16 x i8> %a to <vscale x 16 x i16>70 %2 = zext <vscale x 16 x i8> %b to <vscale x 16 x i16>71 %mul = mul <vscale x 16 x i16> %1, %272 %shr = lshr <vscale x 16 x i16> %mul, splat(i16 8)73 %tr = trunc <vscale x 16 x i16> %shr to <vscale x 16 x i8>74 ret <vscale x 16 x i8> %tr75}76 77define <vscale x 8 x i16> @umulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {78; CHECK-LABEL: umulh_i16:79; CHECK: // %bb.0:80; CHECK-NEXT: umulh z0.h, z0.h, z1.h81; CHECK-NEXT: ret82 %1 = zext <vscale x 8 x i16> %a to <vscale x 8 x i32>83 %2 = zext <vscale x 8 x i16> %b to <vscale x 8 x i32>84 %mul = mul <vscale x 8 x i32> %1, %285 %shr = lshr <vscale x 8 x i32> %mul, splat(i32 16)86 %tr = trunc <vscale x 8 x i32> %shr to <vscale x 8 x i16>87 ret <vscale x 8 x i16> %tr88}89 90define <vscale x 4 x i32> @umulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {91; CHECK-LABEL: umulh_i32:92; CHECK: // %bb.0:93; CHECK-NEXT: umulh z0.s, z0.s, z1.s94; CHECK-NEXT: ret95 %1 = zext <vscale x 4 x i32> %a to <vscale x 4 x i64>96 %2 = zext <vscale x 4 x i32> %b to <vscale x 4 x i64>97 %mul = mul <vscale x 4 x i64> %1, %298 %shr = lshr <vscale x 4 x i64> %mul, splat(i64 32)99 %tr = trunc <vscale x 4 x i64> %shr to <vscale x 4 x i32>100 ret <vscale x 4 x i32> %tr101}102 103define <vscale x 2 x i64> @umulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {104; CHECK-LABEL: umulh_i64:105; CHECK: // %bb.0:106; CHECK-NEXT: umulh z0.d, z0.d, z1.d107; CHECK-NEXT: ret108 %1 = zext <vscale x 2 x i64> %a to <vscale x 2 x i128>109 %2 = zext <vscale x 2 x i64> %b to <vscale x 2 x i128>110 %mul = mul <vscale x 2 x i128> %1, %2111 %shr = lshr <vscale x 2 x i128> %mul, splat(i128 64)112 %tr = trunc <vscale x 2 x i128> %shr to <vscale x 2 x i64>113 ret <vscale x 2 x i64> %tr114}115 116attributes #0 = { "target-features"="+sve2" }117