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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6; ADDHNB7 8define <vscale x 16 x i8> @addhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {9; CHECK-LABEL: addhnb_h:10; CHECK: // %bb.0:11; CHECK-NEXT: addhnb z0.b, z0.h, z1.h12; CHECK-NEXT: ret13 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.addhnb.nxv8i16(<vscale x 8 x i16> %a,14 <vscale x 8 x i16> %b)15 ret <vscale x 16 x i8> %out16}17 18define <vscale x 8 x i16> @addhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {19; CHECK-LABEL: addhnb_s:20; CHECK: // %bb.0:21; CHECK-NEXT: addhnb z0.h, z0.s, z1.s22; CHECK-NEXT: ret23 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.addhnb.nxv4i32(<vscale x 4 x i32> %a,24 <vscale x 4 x i32> %b)25 ret <vscale x 8 x i16> %out26}27 28define <vscale x 4 x i32> @addhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {29; CHECK-LABEL: addhnb_d:30; CHECK: // %bb.0:31; CHECK-NEXT: addhnb z0.s, z0.d, z1.d32; CHECK-NEXT: ret33 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.addhnb.nxv2i64(<vscale x 2 x i64> %a,34 <vscale x 2 x i64> %b)35 ret <vscale x 4 x i32> %out36}37 38; ADDHNT39 40define <vscale x 16 x i8> @addhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {41; CHECK-LABEL: addhnt_h:42; CHECK: // %bb.0:43; CHECK-NEXT: addhnt z0.b, z1.h, z2.h44; CHECK-NEXT: ret45 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.addhnt.nxv8i16(<vscale x 16 x i8> %a,46 <vscale x 8 x i16> %b,47 <vscale x 8 x i16> %c)48 ret <vscale x 16 x i8> %out49}50 51define <vscale x 8 x i16> @addhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {52; CHECK-LABEL: addhnt_s:53; CHECK: // %bb.0:54; CHECK-NEXT: addhnt z0.h, z1.s, z2.s55; CHECK-NEXT: ret56 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.addhnt.nxv4i32(<vscale x 8 x i16> %a,57 <vscale x 4 x i32> %b,58 <vscale x 4 x i32> %c)59 ret <vscale x 8 x i16> %out60}61 62define <vscale x 4 x i32> @addhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {63; CHECK-LABEL: addhnt_d:64; CHECK: // %bb.0:65; CHECK-NEXT: addhnt z0.s, z1.d, z2.d66; CHECK-NEXT: ret67 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.addhnt.nxv2i64(<vscale x 4 x i32> %a,68 <vscale x 2 x i64> %b,69 <vscale x 2 x i64> %c)70 ret <vscale x 4 x i32> %out71}72 73; RADDHNB74 75define <vscale x 16 x i8> @raddhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {76; CHECK-LABEL: raddhnb_h:77; CHECK: // %bb.0:78; CHECK-NEXT: raddhnb z0.b, z0.h, z1.h79; CHECK-NEXT: ret80 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.raddhnb.nxv8i16(<vscale x 8 x i16> %a,81 <vscale x 8 x i16> %b)82 ret <vscale x 16 x i8> %out83}84 85define <vscale x 8 x i16> @raddhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {86; CHECK-LABEL: raddhnb_s:87; CHECK: // %bb.0:88; CHECK-NEXT: raddhnb z0.h, z0.s, z1.s89; CHECK-NEXT: ret90 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.raddhnb.nxv4i32(<vscale x 4 x i32> %a,91 <vscale x 4 x i32> %b)92 ret <vscale x 8 x i16> %out93}94 95define <vscale x 4 x i32> @raddhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {96; CHECK-LABEL: raddhnb_d:97; CHECK: // %bb.0:98; CHECK-NEXT: raddhnb z0.s, z0.d, z1.d99; CHECK-NEXT: ret100 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.raddhnb.nxv2i64(<vscale x 2 x i64> %a,101 <vscale x 2 x i64> %b)102 ret <vscale x 4 x i32> %out103}104 105; RADDHNT106 107define <vscale x 16 x i8> @raddhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {108; CHECK-LABEL: raddhnt_h:109; CHECK: // %bb.0:110; CHECK-NEXT: raddhnt z0.b, z1.h, z2.h111; CHECK-NEXT: ret112 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.raddhnt.nxv8i16(<vscale x 16 x i8> %a,113 <vscale x 8 x i16> %b,114 <vscale x 8 x i16> %c)115 ret <vscale x 16 x i8> %out116}117 118define <vscale x 8 x i16> @raddhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {119; CHECK-LABEL: raddhnt_s:120; CHECK: // %bb.0:121; CHECK-NEXT: raddhnt z0.h, z1.s, z2.s122; CHECK-NEXT: ret123 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.raddhnt.nxv4i32(<vscale x 8 x i16> %a,124 <vscale x 4 x i32> %b,125 <vscale x 4 x i32> %c)126 ret <vscale x 8 x i16> %out127}128 129define <vscale x 4 x i32> @raddhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {130; CHECK-LABEL: raddhnt_d:131; CHECK: // %bb.0:132; CHECK-NEXT: raddhnt z0.s, z1.d, z2.d133; CHECK-NEXT: ret134 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.raddhnt.nxv2i64(<vscale x 4 x i32> %a,135 <vscale x 2 x i64> %b,136 <vscale x 2 x i64> %c)137 ret <vscale x 4 x i32> %out138}139 140; RSUBHNB141 142define <vscale x 16 x i8> @rsubhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {143; CHECK-LABEL: rsubhnb_h:144; CHECK: // %bb.0:145; CHECK-NEXT: rsubhnb z0.b, z0.h, z1.h146; CHECK-NEXT: ret147 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnb.nxv8i16(<vscale x 8 x i16> %a,148 <vscale x 8 x i16> %b)149 ret <vscale x 16 x i8> %out150}151 152define <vscale x 8 x i16> @rsubhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {153; CHECK-LABEL: rsubhnb_s:154; CHECK: // %bb.0:155; CHECK-NEXT: rsubhnb z0.h, z0.s, z1.s156; CHECK-NEXT: ret157 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnb.nxv4i32(<vscale x 4 x i32> %a,158 <vscale x 4 x i32> %b)159 ret <vscale x 8 x i16> %out160}161 162define <vscale x 4 x i32> @rsubhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {163; CHECK-LABEL: rsubhnb_d:164; CHECK: // %bb.0:165; CHECK-NEXT: rsubhnb z0.s, z0.d, z1.d166; CHECK-NEXT: ret167 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnb.nxv2i64(<vscale x 2 x i64> %a,168 <vscale x 2 x i64> %b)169 ret <vscale x 4 x i32> %out170}171 172; RSUBHNT173 174define <vscale x 16 x i8> @rsubhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {175; CHECK-LABEL: rsubhnt_h:176; CHECK: // %bb.0:177; CHECK-NEXT: rsubhnt z0.b, z1.h, z2.h178; CHECK-NEXT: ret179 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnt.nxv8i16(<vscale x 16 x i8> %a,180 <vscale x 8 x i16> %b,181 <vscale x 8 x i16> %c)182 ret <vscale x 16 x i8> %out183}184 185define <vscale x 8 x i16> @rsubhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {186; CHECK-LABEL: rsubhnt_s:187; CHECK: // %bb.0:188; CHECK-NEXT: rsubhnt z0.h, z1.s, z2.s189; CHECK-NEXT: ret190 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnt.nxv4i32(<vscale x 8 x i16> %a,191 <vscale x 4 x i32> %b,192 <vscale x 4 x i32> %c)193 ret <vscale x 8 x i16> %out194}195 196define <vscale x 4 x i32> @rsubhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {197; CHECK-LABEL: rsubhnt_d:198; CHECK: // %bb.0:199; CHECK-NEXT: rsubhnt z0.s, z1.d, z2.d200; CHECK-NEXT: ret201 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnt.nxv2i64(<vscale x 4 x i32> %a,202 <vscale x 2 x i64> %b,203 <vscale x 2 x i64> %c)204 ret <vscale x 4 x i32> %out205}206 207; SUBHNB208 209define <vscale x 16 x i8> @subhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {210; CHECK-LABEL: subhnb_h:211; CHECK: // %bb.0:212; CHECK-NEXT: subhnb z0.b, z0.h, z1.h213; CHECK-NEXT: ret214 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.subhnb.nxv8i16(<vscale x 8 x i16> %a,215 <vscale x 8 x i16> %b)216 ret <vscale x 16 x i8> %out217}218 219define <vscale x 8 x i16> @subhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {220; CHECK-LABEL: subhnb_s:221; CHECK: // %bb.0:222; CHECK-NEXT: subhnb z0.h, z0.s, z1.s223; CHECK-NEXT: ret224 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subhnb.nxv4i32(<vscale x 4 x i32> %a,225 <vscale x 4 x i32> %b)226 ret <vscale x 8 x i16> %out227}228 229define <vscale x 4 x i32> @subhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {230; CHECK-LABEL: subhnb_d:231; CHECK: // %bb.0:232; CHECK-NEXT: subhnb z0.s, z0.d, z1.d233; CHECK-NEXT: ret234 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subhnb.nxv2i64(<vscale x 2 x i64> %a,235 <vscale x 2 x i64> %b)236 ret <vscale x 4 x i32> %out237}238 239; SUBHNT240 241define <vscale x 16 x i8> @subhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {242; CHECK-LABEL: subhnt_h:243; CHECK: // %bb.0:244; CHECK-NEXT: subhnt z0.b, z1.h, z2.h245; CHECK-NEXT: ret246 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.subhnt.nxv8i16(<vscale x 16 x i8> %a,247 <vscale x 8 x i16> %b,248 <vscale x 8 x i16> %c)249 ret <vscale x 16 x i8> %out250}251 252define <vscale x 8 x i16> @subhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {253; CHECK-LABEL: subhnt_s:254; CHECK: // %bb.0:255; CHECK-NEXT: subhnt z0.h, z1.s, z2.s256; CHECK-NEXT: ret257 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subhnt.nxv4i32(<vscale x 8 x i16> %a,258 <vscale x 4 x i32> %b,259 <vscale x 4 x i32> %c)260 ret <vscale x 8 x i16> %out261}262 263define <vscale x 4 x i32> @subhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {264; CHECK-LABEL: subhnt_d:265; CHECK: // %bb.0:266; CHECK-NEXT: subhnt z0.s, z1.d, z2.d267; CHECK-NEXT: ret268 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subhnt.nxv2i64(<vscale x 4 x i32> %a,269 <vscale x 2 x i64> %b,270 <vscale x 2 x i64> %c)271 ret <vscale x 4 x i32> %out272}273 274 275declare <vscale x 16 x i8> @llvm.aarch64.sve.addhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)276declare <vscale x 8 x i16> @llvm.aarch64.sve.addhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)277declare <vscale x 4 x i32> @llvm.aarch64.sve.addhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)278 279declare <vscale x 16 x i8> @llvm.aarch64.sve.addhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)280declare <vscale x 8 x i16> @llvm.aarch64.sve.addhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)281declare <vscale x 4 x i32> @llvm.aarch64.sve.addhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)282 283declare <vscale x 16 x i8> @llvm.aarch64.sve.raddhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)284declare <vscale x 8 x i16> @llvm.aarch64.sve.raddhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)285declare <vscale x 4 x i32> @llvm.aarch64.sve.raddhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)286 287declare <vscale x 16 x i8> @llvm.aarch64.sve.raddhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)288declare <vscale x 8 x i16> @llvm.aarch64.sve.raddhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)289declare <vscale x 4 x i32> @llvm.aarch64.sve.raddhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)290 291declare <vscale x 16 x i8> @llvm.aarch64.sve.subhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)292declare <vscale x 8 x i16> @llvm.aarch64.sve.subhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)293declare <vscale x 4 x i32> @llvm.aarch64.sve.subhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)294 295declare <vscale x 16 x i8> @llvm.aarch64.sve.subhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)296declare <vscale x 8 x i16> @llvm.aarch64.sve.subhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)297declare <vscale x 4 x i32> @llvm.aarch64.sve.subhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)298 299declare <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)300declare <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)301declare <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)302 303declare <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)304declare <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)305declare <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)306