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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6;7; SHRNB8;9 10define <vscale x 16 x i8> @shrnb_h(<vscale x 8 x i16> %a) {11; CHECK-LABEL: shrnb_h:12; CHECK: // %bb.0:13; CHECK-NEXT: shrnb z0.b, z0.h, #814; CHECK-NEXT: ret15 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.shrnb.nxv8i16(<vscale x 8 x i16> %a,16 i32 8)17 ret <vscale x 16 x i8> %out18}19 20define <vscale x 8 x i16> @shrnb_s(<vscale x 4 x i32> %a) {21; CHECK-LABEL: shrnb_s:22; CHECK: // %bb.0:23; CHECK-NEXT: shrnb z0.h, z0.s, #1624; CHECK-NEXT: ret25 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.shrnb.nxv4i32(<vscale x 4 x i32> %a,26 i32 16)27 ret <vscale x 8 x i16> %out28}29 30define <vscale x 4 x i32> @shrnb_d(<vscale x 2 x i64> %a) {31; CHECK-LABEL: shrnb_d:32; CHECK: // %bb.0:33; CHECK-NEXT: shrnb z0.s, z0.d, #3234; CHECK-NEXT: ret35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.shrnb.nxv2i64(<vscale x 2 x i64> %a,36 i32 32)37 ret <vscale x 4 x i32> %out38}39 40;41; RSHRNB42;43 44define <vscale x 16 x i8> @rshrnb_h(<vscale x 8 x i16> %a) {45; CHECK-LABEL: rshrnb_h:46; CHECK: // %bb.0:47; CHECK-NEXT: rshrnb z0.b, z0.h, #248; CHECK-NEXT: ret49 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rshrnb.nxv8i16(<vscale x 8 x i16> %a,50 i32 2)51 ret <vscale x 16 x i8> %out52}53 54define <vscale x 8 x i16> @rshrnb_s(<vscale x 4 x i32> %a) {55; CHECK-LABEL: rshrnb_s:56; CHECK: // %bb.0:57; CHECK-NEXT: rshrnb z0.h, z0.s, #258; CHECK-NEXT: ret59 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rshrnb.nxv4i32(<vscale x 4 x i32> %a,60 i32 2)61 ret <vscale x 8 x i16> %out62}63 64define <vscale x 4 x i32> @rshrnb_d(<vscale x 2 x i64> %a) {65; CHECK-LABEL: rshrnb_d:66; CHECK: // %bb.0:67; CHECK-NEXT: rshrnb z0.s, z0.d, #268; CHECK-NEXT: ret69 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rshrnb.nxv2i64(<vscale x 2 x i64> %a,70 i32 2)71 ret <vscale x 4 x i32> %out72}73 74;75; UQSHRNB76;77 78define <vscale x 16 x i8> @uqshrnb_h(<vscale x 8 x i16> %a) {79; CHECK-LABEL: uqshrnb_h:80; CHECK: // %bb.0:81; CHECK-NEXT: uqshrnb z0.b, z0.h, #182; CHECK-NEXT: ret83 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshrnb.nxv8i16(<vscale x 8 x i16> %a,84 i32 1)85 ret <vscale x 16 x i8> %out86}87 88define <vscale x 8 x i16> @uqshrnb_s(<vscale x 4 x i32> %a) {89; CHECK-LABEL: uqshrnb_s:90; CHECK: // %bb.0:91; CHECK-NEXT: uqshrnb z0.h, z0.s, #192; CHECK-NEXT: ret93 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshrnb.nxv4i32(<vscale x 4 x i32> %a,94 i32 1)95 ret <vscale x 8 x i16> %out96}97 98define <vscale x 4 x i32> @uqshrnb_d(<vscale x 2 x i64> %a) {99; CHECK-LABEL: uqshrnb_d:100; CHECK: // %bb.0:101; CHECK-NEXT: uqshrnb z0.s, z0.d, #1102; CHECK-NEXT: ret103 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqshrnb.nxv2i64(<vscale x 2 x i64> %a,104 i32 1)105 ret <vscale x 4 x i32> %out106}107 108;109; SQSHRNB110;111 112define <vscale x 16 x i8> @sqshrnb_h(<vscale x 8 x i16> %a) {113; CHECK-LABEL: sqshrnb_h:114; CHECK: // %bb.0:115; CHECK-NEXT: sqshrnb z0.b, z0.h, #1116; CHECK-NEXT: ret117 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshrnb.nxv8i16(<vscale x 8 x i16> %a,118 i32 1)119 ret <vscale x 16 x i8> %out120}121 122define <vscale x 8 x i16> @sqshrnb_s(<vscale x 4 x i32> %a) {123; CHECK-LABEL: sqshrnb_s:124; CHECK: // %bb.0:125; CHECK-NEXT: sqshrnb z0.h, z0.s, #1126; CHECK-NEXT: ret127 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshrnb.nxv4i32(<vscale x 4 x i32> %a,128 i32 1)129 ret <vscale x 8 x i16> %out130}131 132define <vscale x 4 x i32> @sqshrnb_d(<vscale x 2 x i64> %a) {133; CHECK-LABEL: sqshrnb_d:134; CHECK: // %bb.0:135; CHECK-NEXT: sqshrnb z0.s, z0.d, #1136; CHECK-NEXT: ret137 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshrnb.nxv2i64(<vscale x 2 x i64> %a,138 i32 1)139 ret <vscale x 4 x i32> %out140}141 142;143; SQSHRUNB144;145 146define <vscale x 16 x i8> @sqshrunb_h(<vscale x 8 x i16> %a) {147; CHECK-LABEL: sqshrunb_h:148; CHECK: // %bb.0:149; CHECK-NEXT: sqshrunb z0.b, z0.h, #7150; CHECK-NEXT: ret151 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshrunb.nxv8i16(<vscale x 8 x i16> %a,152 i32 7)153 ret <vscale x 16 x i8> %out154}155 156define <vscale x 8 x i16> @sqshrunb_s(<vscale x 4 x i32> %a) {157; CHECK-LABEL: sqshrunb_s:158; CHECK: // %bb.0:159; CHECK-NEXT: sqshrunb z0.h, z0.s, #15160; CHECK-NEXT: ret161 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshrunb.nxv4i32(<vscale x 4 x i32> %a,162 i32 15)163 ret <vscale x 8 x i16> %out164}165 166define <vscale x 4 x i32> @sqshrunb_d(<vscale x 2 x i64> %a) {167; CHECK-LABEL: sqshrunb_d:168; CHECK: // %bb.0:169; CHECK-NEXT: sqshrunb z0.s, z0.d, #31170; CHECK-NEXT: ret171 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshrunb.nxv2i64(<vscale x 2 x i64> %a,172 i32 31)173 ret <vscale x 4 x i32> %out174}175 176;177; UQRSHRNB178;179 180define <vscale x 16 x i8> @uqrshrnb_h(<vscale x 8 x i16> %a) {181; CHECK-LABEL: uqrshrnb_h:182; CHECK: // %bb.0:183; CHECK-NEXT: uqrshrnb z0.b, z0.h, #2184; CHECK-NEXT: ret185 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrnb.nxv8i16(<vscale x 8 x i16> %a,186 i32 2)187 ret <vscale x 16 x i8> %out188}189 190define <vscale x 8 x i16> @uqrshrnb_s(<vscale x 4 x i32> %a) {191; CHECK-LABEL: uqrshrnb_s:192; CHECK: // %bb.0:193; CHECK-NEXT: uqrshrnb z0.h, z0.s, #2194; CHECK-NEXT: ret195 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrnb.nxv4i32(<vscale x 4 x i32> %a,196 i32 2)197 ret <vscale x 8 x i16> %out198}199 200define <vscale x 4 x i32> @uqrshrnb_d(<vscale x 2 x i64> %a) {201; CHECK-LABEL: uqrshrnb_d:202; CHECK: // %bb.0:203; CHECK-NEXT: uqrshrnb z0.s, z0.d, #2204; CHECK-NEXT: ret205 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshrnb.nxv2i64(<vscale x 2 x i64> %a,206 i32 2)207 ret <vscale x 4 x i32> %out208}209 210;211; SQRSHRNB212;213 214define <vscale x 16 x i8> @sqrshrnb_h(<vscale x 8 x i16> %a) {215; CHECK-LABEL: sqrshrnb_h:216; CHECK: // %bb.0:217; CHECK-NEXT: sqrshrnb z0.b, z0.h, #2218; CHECK-NEXT: ret219 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrnb.nxv8i16(<vscale x 8 x i16> %a,220 i32 2)221 ret <vscale x 16 x i8> %out222}223 224define <vscale x 8 x i16> @sqrshrnb_s(<vscale x 4 x i32> %a) {225; CHECK-LABEL: sqrshrnb_s:226; CHECK: // %bb.0:227; CHECK-NEXT: sqrshrnb z0.h, z0.s, #2228; CHECK-NEXT: ret229 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrnb.nxv4i32(<vscale x 4 x i32> %a,230 i32 2)231 ret <vscale x 8 x i16> %out232}233 234define <vscale x 4 x i32> @sqrshrnb_d(<vscale x 2 x i64> %a) {235; CHECK-LABEL: sqrshrnb_d:236; CHECK: // %bb.0:237; CHECK-NEXT: sqrshrnb z0.s, z0.d, #2238; CHECK-NEXT: ret239 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrnb.nxv2i64(<vscale x 2 x i64> %a,240 i32 2)241 ret <vscale x 4 x i32> %out242}243 244;245; SQRSHRUNB246;247 248define <vscale x 16 x i8> @sqrshrunb_h(<vscale x 8 x i16> %a) {249; CHECK-LABEL: sqrshrunb_h:250; CHECK: // %bb.0:251; CHECK-NEXT: sqrshrunb z0.b, z0.h, #6252; CHECK-NEXT: ret253 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrunb.nxv8i16(<vscale x 8 x i16> %a,254 i32 6)255 ret <vscale x 16 x i8> %out256}257 258define <vscale x 8 x i16> @sqrshrunb_s(<vscale x 4 x i32> %a) {259; CHECK-LABEL: sqrshrunb_s:260; CHECK: // %bb.0:261; CHECK-NEXT: sqrshrunb z0.h, z0.s, #14262; CHECK-NEXT: ret263 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrunb.nxv4i32(<vscale x 4 x i32> %a,264 i32 14)265 ret <vscale x 8 x i16> %out266}267 268define <vscale x 4 x i32> @sqrshrunb_d(<vscale x 2 x i64> %a) {269; CHECK-LABEL: sqrshrunb_d:270; CHECK: // %bb.0:271; CHECK-NEXT: sqrshrunb z0.s, z0.d, #30272; CHECK-NEXT: ret273 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrunb.nxv2i64(<vscale x 2 x i64> %a,274 i32 30)275 ret <vscale x 4 x i32> %out276}277 278;279; SHRNT280;281 282define <vscale x 16 x i8> @shrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {283; CHECK-LABEL: shrnt_h:284; CHECK: // %bb.0:285; CHECK-NEXT: shrnt z0.b, z1.h, #3286; CHECK-NEXT: ret287 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.shrnt.nxv8i16(<vscale x 16 x i8> %a,288 <vscale x 8 x i16> %b,289 i32 3)290 ret <vscale x 16 x i8> %out291}292 293define <vscale x 8 x i16> @shrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {294; CHECK-LABEL: shrnt_s:295; CHECK: // %bb.0:296; CHECK-NEXT: shrnt z0.h, z1.s, #3297; CHECK-NEXT: ret298 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.shrnt.nxv4i32(<vscale x 8 x i16> %a,299 <vscale x 4 x i32> %b,300 i32 3)301 ret <vscale x 8 x i16> %out302}303 304define <vscale x 4 x i32> @shrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {305; CHECK-LABEL: shrnt_d:306; CHECK: // %bb.0:307; CHECK-NEXT: shrnt z0.s, z1.d, #3308; CHECK-NEXT: ret309 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.shrnt.nxv2i64(<vscale x 4 x i32> %a,310 <vscale x 2 x i64> %b,311 i32 3)312 ret <vscale x 4 x i32> %out313}314 315;316; RSHRNT317;318 319define <vscale x 16 x i8> @rshrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {320; CHECK-LABEL: rshrnt_h:321; CHECK: // %bb.0:322; CHECK-NEXT: rshrnt z0.b, z1.h, #1323; CHECK-NEXT: ret324 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rshrnt.nxv8i16(<vscale x 16 x i8> %a,325 <vscale x 8 x i16> %b,326 i32 1)327 ret <vscale x 16 x i8> %out328}329 330define <vscale x 8 x i16> @rshrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {331; CHECK-LABEL: rshrnt_s:332; CHECK: // %bb.0:333; CHECK-NEXT: rshrnt z0.h, z1.s, #5334; CHECK-NEXT: ret335 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rshrnt.nxv4i32(<vscale x 8 x i16> %a,336 <vscale x 4 x i32> %b,337 i32 5)338 ret <vscale x 8 x i16> %out339}340 341define <vscale x 4 x i32> @rshrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {342; CHECK-LABEL: rshrnt_d:343; CHECK: // %bb.0:344; CHECK-NEXT: rshrnt z0.s, z1.d, #5345; CHECK-NEXT: ret346 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rshrnt.nxv2i64(<vscale x 4 x i32> %a,347 <vscale x 2 x i64> %b,348 i32 5)349 ret <vscale x 4 x i32> %out350}351 352;353; UQSHRNT354;355 356define <vscale x 16 x i8> @uqshrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {357; CHECK-LABEL: uqshrnt_h:358; CHECK: // %bb.0:359; CHECK-NEXT: uqshrnt z0.b, z1.h, #5360; CHECK-NEXT: ret361 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshrnt.nxv8i16(<vscale x 16 x i8> %a,362 <vscale x 8 x i16> %b,363 i32 5)364 ret <vscale x 16 x i8> %out365}366 367define <vscale x 8 x i16> @uqshrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {368; CHECK-LABEL: uqshrnt_s:369; CHECK: // %bb.0:370; CHECK-NEXT: uqshrnt z0.h, z1.s, #13371; CHECK-NEXT: ret372 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshrnt.nxv4i32(<vscale x 8 x i16> %a,373 <vscale x 4 x i32> %b,374 i32 13)375 ret <vscale x 8 x i16> %out376}377 378define <vscale x 4 x i32> @uqshrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {379; CHECK-LABEL: uqshrnt_d:380; CHECK: // %bb.0:381; CHECK-NEXT: uqshrnt z0.s, z1.d, #29382; CHECK-NEXT: ret383 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqshrnt.nxv2i64(<vscale x 4 x i32> %a,384 <vscale x 2 x i64> %b,385 i32 29)386 ret <vscale x 4 x i32> %out387}388 389;390; SQSHRNT391;392 393define <vscale x 16 x i8> @sqshrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {394; CHECK-LABEL: sqshrnt_h:395; CHECK: // %bb.0:396; CHECK-NEXT: sqshrnt z0.b, z1.h, #5397; CHECK-NEXT: ret398 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshrnt.nxv8i16(<vscale x 16 x i8> %a,399 <vscale x 8 x i16> %b,400 i32 5)401 ret <vscale x 16 x i8> %out402}403 404define <vscale x 8 x i16> @sqshrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {405; CHECK-LABEL: sqshrnt_s:406; CHECK: // %bb.0:407; CHECK-NEXT: sqshrnt z0.h, z1.s, #13408; CHECK-NEXT: ret409 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshrnt.nxv4i32(<vscale x 8 x i16> %a,410 <vscale x 4 x i32> %b,411 i32 13)412 ret <vscale x 8 x i16> %out413}414 415define <vscale x 4 x i32> @sqshrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {416; CHECK-LABEL: sqshrnt_d:417; CHECK: // %bb.0:418; CHECK-NEXT: sqshrnt z0.s, z1.d, #29419; CHECK-NEXT: ret420 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshrnt.nxv2i64(<vscale x 4 x i32> %a,421 <vscale x 2 x i64> %b,422 i32 29)423 ret <vscale x 4 x i32> %out424}425 426;427; SQSHRUNT428;429 430define <vscale x 16 x i8> @sqshrunt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {431; CHECK-LABEL: sqshrunt_h:432; CHECK: // %bb.0:433; CHECK-NEXT: sqshrunt z0.b, z1.h, #4434; CHECK-NEXT: ret435 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshrunt.nxv8i16(<vscale x 16 x i8> %a,436 <vscale x 8 x i16> %b,437 i32 4)438 ret <vscale x 16 x i8> %out439}440 441define <vscale x 8 x i16> @sqshrunt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {442; CHECK-LABEL: sqshrunt_s:443; CHECK: // %bb.0:444; CHECK-NEXT: sqshrunt z0.h, z1.s, #4445; CHECK-NEXT: ret446 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshrunt.nxv4i32(<vscale x 8 x i16> %a,447 <vscale x 4 x i32> %b,448 i32 4)449 ret <vscale x 8 x i16> %out450}451 452define <vscale x 4 x i32> @sqshrunt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {453; CHECK-LABEL: sqshrunt_d:454; CHECK: // %bb.0:455; CHECK-NEXT: sqshrunt z0.s, z1.d, #4456; CHECK-NEXT: ret457 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshrunt.nxv2i64(<vscale x 4 x i32> %a,458 <vscale x 2 x i64> %b,459 i32 4)460 ret <vscale x 4 x i32> %out461}462 463;464; UQRSHRNT465;466 467define <vscale x 16 x i8> @uqrshrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {468; CHECK-LABEL: uqrshrnt_h:469; CHECK: // %bb.0:470; CHECK-NEXT: uqrshrnt z0.b, z1.h, #8471; CHECK-NEXT: ret472 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrnt.nxv8i16(<vscale x 16 x i8> %a,473 <vscale x 8 x i16> %b,474 i32 8)475 ret <vscale x 16 x i8> %out476}477 478define <vscale x 8 x i16> @uqrshrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {479; CHECK-LABEL: uqrshrnt_s:480; CHECK: // %bb.0:481; CHECK-NEXT: uqrshrnt z0.h, z1.s, #12482; CHECK-NEXT: ret483 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrnt.nxv4i32(<vscale x 8 x i16> %a,484 <vscale x 4 x i32> %b,485 i32 12)486 ret <vscale x 8 x i16> %out487}488 489define <vscale x 4 x i32> @uqrshrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {490; CHECK-LABEL: uqrshrnt_d:491; CHECK: // %bb.0:492; CHECK-NEXT: uqrshrnt z0.s, z1.d, #28493; CHECK-NEXT: ret494 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshrnt.nxv2i64(<vscale x 4 x i32> %a,495 <vscale x 2 x i64> %b,496 i32 28)497 ret <vscale x 4 x i32> %out498}499 500;501; SQRSHRNT502;503 504define <vscale x 16 x i8> @sqrshrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {505; CHECK-LABEL: sqrshrnt_h:506; CHECK: // %bb.0:507; CHECK-NEXT: sqrshrnt z0.b, z1.h, #8508; CHECK-NEXT: ret509 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrnt.nxv8i16(<vscale x 16 x i8> %a,510 <vscale x 8 x i16> %b,511 i32 8)512 ret <vscale x 16 x i8> %out513}514 515define <vscale x 8 x i16> @sqrshrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {516; CHECK-LABEL: sqrshrnt_s:517; CHECK: // %bb.0:518; CHECK-NEXT: sqrshrnt z0.h, z1.s, #12519; CHECK-NEXT: ret520 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrnt.nxv4i32(<vscale x 8 x i16> %a,521 <vscale x 4 x i32> %b,522 i32 12)523 ret <vscale x 8 x i16> %out524}525 526define <vscale x 4 x i32> @sqrshrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {527; CHECK-LABEL: sqrshrnt_d:528; CHECK: // %bb.0:529; CHECK-NEXT: sqrshrnt z0.s, z1.d, #28530; CHECK-NEXT: ret531 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrnt.nxv2i64(<vscale x 4 x i32> %a,532 <vscale x 2 x i64> %b,533 i32 28)534 ret <vscale x 4 x i32> %out535}536 537;538; SQRSHRUNT539;540 541define <vscale x 16 x i8> @sqrshrunt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {542; CHECK-LABEL: sqrshrunt_h:543; CHECK: // %bb.0:544; CHECK-NEXT: sqrshrunt z0.b, z1.h, #1545; CHECK-NEXT: ret546 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrunt.nxv8i16(<vscale x 16 x i8> %a,547 <vscale x 8 x i16> %b,548 i32 1)549 ret <vscale x 16 x i8> %out550}551 552define <vscale x 8 x i16> @sqrshrunt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {553; CHECK-LABEL: sqrshrunt_s:554; CHECK: // %bb.0:555; CHECK-NEXT: sqrshrunt z0.h, z1.s, #5556; CHECK-NEXT: ret557 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrunt.nxv4i32(<vscale x 8 x i16> %a,558 <vscale x 4 x i32> %b,559 i32 5)560 ret <vscale x 8 x i16> %out561}562 563define <vscale x 4 x i32> @sqrshrunt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {564; CHECK-LABEL: sqrshrunt_d:565; CHECK: // %bb.0:566; CHECK-NEXT: sqrshrunt z0.s, z1.d, #5567; CHECK-NEXT: ret568 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrunt.nxv2i64(<vscale x 4 x i32> %a,569 <vscale x 2 x i64> %b,570 i32 5)571 ret <vscale x 4 x i32> %out572}573 574declare <vscale x 16 x i8> @llvm.aarch64.sve.shrnb.nxv8i16(<vscale x 8 x i16>, i32)575declare <vscale x 8 x i16> @llvm.aarch64.sve.shrnb.nxv4i32(<vscale x 4 x i32>, i32)576declare <vscale x 4 x i32> @llvm.aarch64.sve.shrnb.nxv2i64(<vscale x 2 x i64>, i32)577 578declare <vscale x 16 x i8> @llvm.aarch64.sve.rshrnb.nxv8i16(<vscale x 8 x i16>, i32)579declare <vscale x 8 x i16> @llvm.aarch64.sve.rshrnb.nxv4i32(<vscale x 4 x i32>, i32)580declare <vscale x 4 x i32> @llvm.aarch64.sve.rshrnb.nxv2i64(<vscale x 2 x i64>, i32)581 582declare <vscale x 16 x i8> @llvm.aarch64.sve.uqshrnb.nxv8i16(<vscale x 8 x i16>, i32)583declare <vscale x 8 x i16> @llvm.aarch64.sve.uqshrnb.nxv4i32(<vscale x 4 x i32>, i32)584declare <vscale x 4 x i32> @llvm.aarch64.sve.uqshrnb.nxv2i64(<vscale x 2 x i64>, i32)585 586declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshrnb.nxv8i16(<vscale x 8 x i16>, i32)587declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshrnb.nxv4i32(<vscale x 4 x i32>, i32)588declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshrnb.nxv2i64(<vscale x 2 x i64>, i32)589 590declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrnb.nxv8i16(<vscale x 8 x i16>, i32)591declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrnb.nxv4i32(<vscale x 4 x i32>, i32)592declare <vscale x 4 x i32> @llvm.aarch64.sve.uqrshrnb.nxv2i64(<vscale x 2 x i64>, i32)593 594declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrnb.nxv8i16(<vscale x 8 x i16>, i32)595declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrnb.nxv4i32(<vscale x 4 x i32>, i32)596declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrnb.nxv2i64(<vscale x 2 x i64>, i32)597 598declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshrunb.nxv8i16(<vscale x 8 x i16>, i32)599declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshrunb.nxv4i32(<vscale x 4 x i32>, i32)600declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshrunb.nxv2i64(<vscale x 2 x i64>, i32)601 602declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrunb.nxv8i16(<vscale x 8 x i16>, i32)603declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrunb.nxv4i32(<vscale x 4 x i32>, i32)604declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrunb.nxv2i64(<vscale x 2 x i64>, i32)605 606declare <vscale x 16 x i8> @llvm.aarch64.sve.shrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)607declare <vscale x 8 x i16> @llvm.aarch64.sve.shrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)608declare <vscale x 4 x i32> @llvm.aarch64.sve.shrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)609 610declare <vscale x 16 x i8> @llvm.aarch64.sve.rshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)611declare <vscale x 8 x i16> @llvm.aarch64.sve.rshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)612declare <vscale x 4 x i32> @llvm.aarch64.sve.rshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)613 614declare <vscale x 16 x i8> @llvm.aarch64.sve.uqshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)615declare <vscale x 8 x i16> @llvm.aarch64.sve.uqshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)616declare <vscale x 4 x i32> @llvm.aarch64.sve.uqshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)617 618declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)619declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)620declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)621 622declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshrunt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)623declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshrunt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)624declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshrunt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)625 626declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)627declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)628declare <vscale x 4 x i32> @llvm.aarch64.sve.uqrshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)629 630declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)631declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)632declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)633 634declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrunt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)635declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrunt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)636declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrunt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)637