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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-bitperm < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sve-bitperm < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+ssve-bitperm < %s | FileCheck %s5; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+ssve-bitperm -force-streaming < %s | FileCheck %s6 7;8; BDEP9;10 11define <vscale x 16 x i8> @bdep_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {12; CHECK-LABEL: bdep_nxv16i8:13; CHECK: // %bb.0:14; CHECK-NEXT: bdep z0.b, z0.b, z1.b15; CHECK-NEXT: ret16 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bdep.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)17 ret <vscale x 16 x i8> %out18}19 20define <vscale x 8 x i16> @bdep_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {21; CHECK-LABEL: bdep_nxv8i16:22; CHECK: // %bb.0:23; CHECK-NEXT: bdep z0.h, z0.h, z1.h24; CHECK-NEXT: ret25 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bdep.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)26 ret <vscale x 8 x i16> %out27}28 29define <vscale x 4 x i32> @bdep_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {30; CHECK-LABEL: bdep_nxv4i32:31; CHECK: // %bb.0:32; CHECK-NEXT: bdep z0.s, z0.s, z1.s33; CHECK-NEXT: ret34 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bdep.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)35 ret <vscale x 4 x i32> %out36}37 38define <vscale x 2 x i64> @bdep_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {39; CHECK-LABEL: bdep_nxv2i64:40; CHECK: // %bb.0:41; CHECK-NEXT: bdep z0.d, z0.d, z1.d42; CHECK-NEXT: ret43 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bdep.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)44 ret <vscale x 2 x i64> %out45}46 47;48; BEXT49;50 51define <vscale x 16 x i8> @bext_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {52; CHECK-LABEL: bext_nxv16i8:53; CHECK: // %bb.0:54; CHECK-NEXT: bext z0.b, z0.b, z1.b55; CHECK-NEXT: ret56 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bext.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)57 ret <vscale x 16 x i8> %out58}59 60define <vscale x 8 x i16> @bext_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {61; CHECK-LABEL: bext_nxv8i16:62; CHECK: // %bb.0:63; CHECK-NEXT: bext z0.h, z0.h, z1.h64; CHECK-NEXT: ret65 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bext.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)66 ret <vscale x 8 x i16> %out67}68 69define <vscale x 4 x i32> @bext_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {70; CHECK-LABEL: bext_nxv4i32:71; CHECK: // %bb.0:72; CHECK-NEXT: bext z0.s, z0.s, z1.s73; CHECK-NEXT: ret74 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bext.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)75 ret <vscale x 4 x i32> %out76}77 78define <vscale x 2 x i64> @bext_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {79; CHECK-LABEL: bext_nxv2i64:80; CHECK: // %bb.0:81; CHECK-NEXT: bext z0.d, z0.d, z1.d82; CHECK-NEXT: ret83 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bext.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)84 ret <vscale x 2 x i64> %out85}86 87;88; BGRP89;90 91define <vscale x 16 x i8> @bgrp_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {92; CHECK-LABEL: bgrp_nxv16i8:93; CHECK: // %bb.0:94; CHECK-NEXT: bgrp z0.b, z0.b, z1.b95; CHECK-NEXT: ret96 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bgrp.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)97 ret <vscale x 16 x i8> %out98}99 100define <vscale x 8 x i16> @bgrp_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {101; CHECK-LABEL: bgrp_nxv8i16:102; CHECK: // %bb.0:103; CHECK-NEXT: bgrp z0.h, z0.h, z1.h104; CHECK-NEXT: ret105 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bgrp.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)106 ret <vscale x 8 x i16> %out107}108 109define <vscale x 4 x i32> @bgrp_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {110; CHECK-LABEL: bgrp_nxv4i32:111; CHECK: // %bb.0:112; CHECK-NEXT: bgrp z0.s, z0.s, z1.s113; CHECK-NEXT: ret114 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bgrp.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)115 ret <vscale x 4 x i32> %out116}117 118define <vscale x 2 x i64> @bgrp_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {119; CHECK-LABEL: bgrp_nxv2i64:120; CHECK: // %bb.0:121; CHECK-NEXT: bgrp z0.d, z0.d, z1.d122; CHECK-NEXT: ret123 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bgrp.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)124 ret <vscale x 2 x i64> %out125}126 127declare <vscale x 16 x i8> @llvm.aarch64.sve.bdep.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)128declare <vscale x 8 x i16> @llvm.aarch64.sve.bdep.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)129declare <vscale x 4 x i32> @llvm.aarch64.sve.bdep.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)130declare <vscale x 2 x i64> @llvm.aarch64.sve.bdep.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)131 132declare <vscale x 16 x i8> @llvm.aarch64.sve.bext.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)133declare <vscale x 8 x i16> @llvm.aarch64.sve.bext.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)134declare <vscale x 4 x i32> @llvm.aarch64.sve.bext.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)135declare <vscale x 2 x i64> @llvm.aarch64.sve.bext.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)136 137declare <vscale x 16 x i8> @llvm.aarch64.sve.bgrp.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)138declare <vscale x 8 x i16> @llvm.aarch64.sve.bgrp.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)139declare <vscale x 4 x i32> @llvm.aarch64.sve.bgrp.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)140declare <vscale x 2 x i64> @llvm.aarch64.sve.bgrp.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)141