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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6;7; CDOT8;9 10define <vscale x 4 x i32> @cdot_s(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {11; CHECK-LABEL: cdot_s:12; CHECK: // %bb.0:13; CHECK-NEXT: cdot z0.s, z1.b, z2.b, #014; CHECK-NEXT: ret15 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32> %a,16 <vscale x 16 x i8> %b,17 <vscale x 16 x i8> %c,18 i32 0)19 ret <vscale x 4 x i32> %out20}21 22define <vscale x 2 x i64> @cdot_d(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {23; CHECK-LABEL: cdot_d:24; CHECK: // %bb.0:25; CHECK-NEXT: cdot z0.d, z1.h, z2.h, #9026; CHECK-NEXT: ret27 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64> %a,28 <vscale x 8 x i16> %b,29 <vscale x 8 x i16> %c,30 i32 90)31 ret <vscale x 2 x i64> %out32}33 34;35; CDOT(indexed)36;37 38define <vscale x 4 x i32> @cdot_s_idx(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {39; CHECK-LABEL: cdot_s_idx:40; CHECK: // %bb.0:41; CHECK-NEXT: cdot z0.s, z1.b, z2.b[0], #18042; CHECK-NEXT: ret43 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.lane.nxv4i32(<vscale x 4 x i32> %a,44 <vscale x 16 x i8> %b,45 <vscale x 16 x i8> %c,46 i32 0, i32 180)47 ret <vscale x 4 x i32> %out48}49 50define <vscale x 2 x i64> @cdot_d_idx(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {51; CHECK-LABEL: cdot_d_idx:52; CHECK: // %bb.0:53; CHECK-NEXT: cdot z0.d, z1.h, z2.h[1], #27054; CHECK-NEXT: ret55 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.lane.nxv2i64(<vscale x 2 x i64> %a,56 <vscale x 8 x i16> %b,57 <vscale x 8 x i16> %c,58 i32 1, i32 270)59 ret <vscale x 2 x i64> %out60}61 62declare <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)63declare <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)64declare <vscale x 4 x i32> @llvm.aarch64.sve.cdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32, i32)65declare <vscale x 2 x i64> @llvm.aarch64.sve.cdot.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32, i32)66