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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6;7; WHILERW8;9 10define <vscale x 16 x i1> @whilerw_i8(ptr %a, ptr %b) {11; CHECK-LABEL: whilerw_i8:12; CHECK: // %bb.0:13; CHECK-NEXT: whilerw p0.b, x0, x114; CHECK-NEXT: ret15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilerw.b.nx16i1(ptr %a, ptr %b)16 ret <vscale x 16 x i1> %out17}18 19define <vscale x 8 x i1> @whilerw_i16(ptr %a, ptr %b) {20; CHECK-LABEL: whilerw_i16:21; CHECK: // %bb.0:22; CHECK-NEXT: whilerw p0.h, x0, x123; CHECK-NEXT: ret24 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1(ptr %a, ptr %b)25 ret <vscale x 8 x i1> %out26}27 28define <vscale x 4 x i1> @whilerw_i32(ptr %a, ptr %b) {29; CHECK-LABEL: whilerw_i32:30; CHECK: // %bb.0:31; CHECK-NEXT: whilerw p0.s, x0, x132; CHECK-NEXT: ret33 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilerw.s.nx4i1(ptr %a, ptr %b)34 ret <vscale x 4 x i1> %out35}36 37define <vscale x 2 x i1> @whilerw_i64(ptr %a, ptr %b) {38; CHECK-LABEL: whilerw_i64:39; CHECK: // %bb.0:40; CHECK-NEXT: whilerw p0.d, x0, x141; CHECK-NEXT: ret42 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilerw.d.nx2i1(ptr %a, ptr %b)43 ret <vscale x 2 x i1> %out44}45 46define <vscale x 8 x i1> @whilerw_bfloat(ptr %a, ptr %b) {47; CHECK-LABEL: whilerw_bfloat:48; CHECK: // %bb.0:49; CHECK-NEXT: whilerw p0.h, x0, x150; CHECK-NEXT: ret51 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1.bf16.bf16(ptr %a, ptr %b)52 ret <vscale x 8 x i1> %out53}54 55define <vscale x 8 x i1> @whilerw_half(ptr %a, ptr %b) {56; CHECK-LABEL: whilerw_half:57; CHECK: // %bb.0:58; CHECK-NEXT: whilerw p0.h, x0, x159; CHECK-NEXT: ret60 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1.f16.f16(ptr %a, ptr %b)61 ret <vscale x 8 x i1> %out62}63 64define <vscale x 4 x i1> @whilerw_float(ptr %a, ptr %b) {65; CHECK-LABEL: whilerw_float:66; CHECK: // %bb.0:67; CHECK-NEXT: whilerw p0.s, x0, x168; CHECK-NEXT: ret69 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilerw.s.nx4i1.f32.f32(ptr %a, ptr %b)70 ret <vscale x 4 x i1> %out71}72 73define <vscale x 2 x i1> @whilerw_double(ptr %a, ptr %b) {74; CHECK-LABEL: whilerw_double:75; CHECK: // %bb.0:76; CHECK-NEXT: whilerw p0.d, x0, x177; CHECK-NEXT: ret78 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilerw.d.nx2i1.f64.f64(ptr %a, ptr %b)79 ret <vscale x 2 x i1> %out80}81 82;83; WHILEWR84;85 86define <vscale x 16 x i1> @whilewr_i8(ptr %a, ptr %b) {87; CHECK-LABEL: whilewr_i8:88; CHECK: // %bb.0:89; CHECK-NEXT: whilewr p0.b, x0, x190; CHECK-NEXT: ret91 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilewr.b.nx16i1(ptr %a, ptr %b)92 ret <vscale x 16 x i1> %out93}94 95define <vscale x 8 x i1> @whilewr_i16(ptr %a, ptr %b) {96; CHECK-LABEL: whilewr_i16:97; CHECK: // %bb.0:98; CHECK-NEXT: whilewr p0.h, x0, x199; CHECK-NEXT: ret100 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1(ptr %a, ptr %b)101 ret <vscale x 8 x i1> %out102}103 104define <vscale x 4 x i1> @whilewr_i32(ptr %a, ptr %b) {105; CHECK-LABEL: whilewr_i32:106; CHECK: // %bb.0:107; CHECK-NEXT: whilewr p0.s, x0, x1108; CHECK-NEXT: ret109 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilewr.s.nx4i1(ptr %a, ptr %b)110 ret <vscale x 4 x i1> %out111}112 113define <vscale x 2 x i1> @whilewr_i64(ptr %a, ptr %b) {114; CHECK-LABEL: whilewr_i64:115; CHECK: // %bb.0:116; CHECK-NEXT: whilewr p0.d, x0, x1117; CHECK-NEXT: ret118 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilewr.d.nx2i1(ptr %a, ptr %b)119 ret <vscale x 2 x i1> %out120}121 122define <vscale x 8 x i1> @whilewr_bfloat(ptr %a, ptr %b) {123; CHECK-LABEL: whilewr_bfloat:124; CHECK: // %bb.0:125; CHECK-NEXT: whilewr p0.h, x0, x1126; CHECK-NEXT: ret127 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1.bf16.bf16(ptr %a, ptr %b)128 ret <vscale x 8 x i1> %out129}130 131define <vscale x 8 x i1> @whilewr_half(ptr %a, ptr %b) {132; CHECK-LABEL: whilewr_half:133; CHECK: // %bb.0:134; CHECK-NEXT: whilewr p0.h, x0, x1135; CHECK-NEXT: ret136 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1.f16.f16(ptr %a, ptr %b)137 ret <vscale x 8 x i1> %out138}139 140define <vscale x 4 x i1> @whilewr_float(ptr %a, ptr %b) {141; CHECK-LABEL: whilewr_float:142; CHECK: // %bb.0:143; CHECK-NEXT: whilewr p0.s, x0, x1144; CHECK-NEXT: ret145 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilewr.s.nx4i1.f32.f32(ptr %a, ptr %b)146 ret <vscale x 4 x i1> %out147}148 149define <vscale x 2 x i1> @whilewr_double(ptr %a, ptr %b) {150; CHECK-LABEL: whilewr_double:151; CHECK: // %bb.0:152; CHECK-NEXT: whilewr p0.d, x0, x1153; CHECK-NEXT: ret154 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilewr.d.nx2i1.f64.f64(ptr %a, ptr %b)155 ret <vscale x 2 x i1> %out156}157 158declare <vscale x 16 x i1> @llvm.aarch64.sve.whilerw.b.nx16i1(ptr %a, ptr %b)159declare <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1(ptr %a, ptr %b)160declare <vscale x 4 x i1> @llvm.aarch64.sve.whilerw.s.nx4i1(ptr %a, ptr %b)161declare <vscale x 2 x i1> @llvm.aarch64.sve.whilerw.d.nx2i1(ptr %a, ptr %b)162 163declare <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1.bf16.bf16(ptr %a, ptr %b)164declare <vscale x 8 x i1> @llvm.aarch64.sve.whilerw.h.nx8i1.f16.f16(ptr %a, ptr %b)165declare <vscale x 4 x i1> @llvm.aarch64.sve.whilerw.s.nx4i1.f32.f32(ptr %a, ptr %b)166declare <vscale x 2 x i1> @llvm.aarch64.sve.whilerw.d.nx2i1.f64.f64(ptr %a, ptr %b)167 168declare <vscale x 16 x i1> @llvm.aarch64.sve.whilewr.b.nx16i1(ptr %a, ptr %b)169declare <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1(ptr %a, ptr %b)170declare <vscale x 4 x i1> @llvm.aarch64.sve.whilewr.s.nx4i1(ptr %a, ptr %b)171declare <vscale x 2 x i1> @llvm.aarch64.sve.whilewr.d.nx2i1(ptr %a, ptr %b)172 173declare <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1.bf16.bf16(ptr %a, ptr %b)174declare <vscale x 8 x i1> @llvm.aarch64.sve.whilewr.h.nx8i1.f16.f16(ptr %a, ptr %b)175declare <vscale x 4 x i1> @llvm.aarch64.sve.whilewr.s.nx4i1.f32.f32(ptr %a, ptr %b)176declare <vscale x 2 x i1> @llvm.aarch64.sve.whilewr.d.nx2i1.f64.f64(ptr %a, ptr %b)177