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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-aes < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sve-aes < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+ssve-aes < %s | FileCheck %s5; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+ssve-aes -force-streaming < %s | FileCheck %s6 7;8; AESD9;10 11define <vscale x 16 x i8> @aesd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {12; CHECK-LABEL: aesd_i8:13; CHECK: // %bb.0:14; CHECK-NEXT: aesd z0.b, z0.b, z1.b15; CHECK-NEXT: ret16 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> %a,17 <vscale x 16 x i8> %b)18 ret <vscale x 16 x i8> %out19}20 21define <vscale x 16 x i8> @aesd_i8_commuted(<vscale x 16 x i8> %a,22; CHECK-LABEL: aesd_i8_commuted:23; CHECK: // %bb.0:24; CHECK-NEXT: aesd z0.b, z0.b, z1.b25; CHECK-NEXT: ret26 <vscale x 16 x i8> %b) {27 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> %b,28 <vscale x 16 x i8> %a)29 ret <vscale x 16 x i8> %out30}31 32;33; AESIMC34;35 36define <vscale x 16 x i8> @aesimc_i8(<vscale x 16 x i8> %a) {37; CHECK-LABEL: aesimc_i8:38; CHECK: // %bb.0:39; CHECK-NEXT: aesimc z0.b, z0.b40; CHECK-NEXT: ret41 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesimc(<vscale x 16 x i8> %a)42 ret <vscale x 16 x i8> %out43}44 45;46; AESE47;48 49define <vscale x 16 x i8> @aese_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {50; CHECK-LABEL: aese_i8:51; CHECK: // %bb.0:52; CHECK-NEXT: aese z0.b, z0.b, z1.b53; CHECK-NEXT: ret54 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> %a,55 <vscale x 16 x i8> %b)56 ret <vscale x 16 x i8> %out57}58 59define <vscale x 16 x i8> @aese_i8_commuted(<vscale x 16 x i8> %a,60; CHECK-LABEL: aese_i8_commuted:61; CHECK: // %bb.0:62; CHECK-NEXT: aese z0.b, z0.b, z1.b63; CHECK-NEXT: ret64 <vscale x 16 x i8> %b) {65 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> %b,66 <vscale x 16 x i8> %a)67 ret <vscale x 16 x i8> %out68}69 70;71; AESMC72;73 74define <vscale x 16 x i8> @aesmc_i8(<vscale x 16 x i8> %a) {75; CHECK-LABEL: aesmc_i8:76; CHECK: // %bb.0:77; CHECK-NEXT: aesmc z0.b, z0.b78; CHECK-NEXT: ret79 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesmc(<vscale x 16 x i8> %a)80 ret <vscale x 16 x i8> %out81}82 83declare <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8>, <vscale x 16 x i8>)84declare <vscale x 16 x i8> @llvm.aarch64.sve.aesimc(<vscale x 16 x i8>)85declare <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8>, <vscale x 16 x i8>)86declare <vscale x 16 x i8> @llvm.aarch64.sve.aesmc(<vscale x 16 x i8>)87