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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mattr=+sve,+sme2 < %s | FileCheck %s4; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s5 6target triple = "aarch64-linux"7 8define <vscale x 8 x half> @famin_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {9; CHECK-LABEL: famin_f16:10; CHECK: // %bb.0:11; CHECK-NEXT: famin z0.h, p0/m, z0.h, z1.h12; CHECK-NEXT: ret13 %r = call <vscale x 8 x half> @llvm.aarch64.sve.famin.nxv8f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b)14 ret <vscale x 8 x half> %r15}16 17define <vscale x 4 x float> @famin_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {18; CHECK-LABEL: famin_f32:19; CHECK: // %bb.0:20; CHECK-NEXT: famin z0.s, p0/m, z0.s, z1.s21; CHECK-NEXT: ret22 %r = call <vscale x 4 x float> @llvm.aarch64.sve.famin.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b)23 ret <vscale x 4 x float> %r24}25 26define <vscale x 2 x double> @famin_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {27; CHECK-LABEL: famin_f64:28; CHECK: // %bb.0:29; CHECK-NEXT: famin z0.d, p0/m, z0.d, z1.d30; CHECK-NEXT: ret31 %r = call <vscale x 2 x double> @llvm.aarch64.sve.famin.nxv2f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b)32 ret <vscale x 2 x double> %r33}34 35define <vscale x 8 x half> @famin_u_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {36; CHECK-LABEL: famin_u_f16:37; CHECK: // %bb.0:38; CHECK-NEXT: famin z0.h, p0/m, z0.h, z1.h39; CHECK-NEXT: ret40 %r = call <vscale x 8 x half> @llvm.aarch64.sve.famin.u.nxv8f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %b, <vscale x 8 x half> %a)41 ret <vscale x 8 x half> %r42}43 44define <vscale x 4 x float> @famin_u_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {45; CHECK-LABEL: famin_u_f32:46; CHECK: // %bb.0:47; CHECK-NEXT: famin z0.s, p0/m, z0.s, z1.s48; CHECK-NEXT: ret49 %r = call <vscale x 4 x float> @llvm.aarch64.sve.famin.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %b, <vscale x 4 x float> %a)50 ret <vscale x 4 x float> %r51}52 53define <vscale x 2 x double> @famin_u_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {54; CHECK-LABEL: famin_u_f64:55; CHECK: // %bb.0:56; CHECK-NEXT: famin z0.d, p0/m, z0.d, z1.d57; CHECK-NEXT: ret58 %r = call <vscale x 2 x double> @llvm.aarch64.sve.famin.u.nxv2f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %b, <vscale x 2 x double> %a)59 ret <vscale x 2 x double> %r60}61 62define <vscale x 8 x half> @famax_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {63; CHECK-LABEL: famax_f16:64; CHECK: // %bb.0:65; CHECK-NEXT: famax z0.h, p0/m, z0.h, z1.h66; CHECK-NEXT: ret67 %r = call <vscale x 8 x half> @llvm.aarch64.sve.famax.nxv8f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b)68 ret <vscale x 8 x half> %r69}70 71define <vscale x 4 x float> @famax_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {72; CHECK-LABEL: famax_f32:73; CHECK: // %bb.0:74; CHECK-NEXT: famax z0.s, p0/m, z0.s, z1.s75; CHECK-NEXT: ret76 %r = call <vscale x 4 x float> @llvm.aarch64.sve.famax.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b)77 ret <vscale x 4 x float> %r78}79 80define <vscale x 2 x double> @famax_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {81; CHECK-LABEL: famax_f64:82; CHECK: // %bb.0:83; CHECK-NEXT: famax z0.d, p0/m, z0.d, z1.d84; CHECK-NEXT: ret85 %r = call <vscale x 2 x double> @llvm.aarch64.sve.famax.nxv2f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b)86 ret <vscale x 2 x double> %r87}88 89define <vscale x 8 x half> @famax_u_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {90; CHECK-LABEL: famax_u_f16:91; CHECK: // %bb.0:92; CHECK-NEXT: famax z0.h, p0/m, z0.h, z1.h93; CHECK-NEXT: ret94 %r = call <vscale x 8 x half> @llvm.aarch64.sve.famax.u.nxv8f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %b, <vscale x 8 x half> %a)95 ret <vscale x 8 x half> %r96}97 98define <vscale x 4 x float> @famax_u_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {99; CHECK-LABEL: famax_u_f32:100; CHECK: // %bb.0:101; CHECK-NEXT: famax z0.s, p0/m, z0.s, z1.s102; CHECK-NEXT: ret103 %r = call <vscale x 4 x float> @llvm.aarch64.sve.famax.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %b, <vscale x 4 x float> %a)104 ret <vscale x 4 x float> %r105}106 107define <vscale x 2 x double> @famax_u_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {108; CHECK-LABEL: famax_u_f64:109; CHECK: // %bb.0:110; CHECK-NEXT: famax z0.d, p0/m, z0.d, z1.d111; CHECK-NEXT: ret112 %r = call <vscale x 2 x double> @llvm.aarch64.sve.famax.u.nxv2f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %b, <vscale x 2 x double> %a)113 ret <vscale x 2 x double> %r114}115 116attributes #0 = { nounwind "target-features" = "+faminmax" }117