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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6;7; FMLALB (Vectors)8;9 10define <vscale x 4 x float> @fmlalb_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {11; CHECK-LABEL: fmlalb_h:12; CHECK: // %bb.0:13; CHECK-NEXT: fmlalb z0.s, z1.h, z2.h14; CHECK-NEXT: ret15 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.nxv4f32(<vscale x 4 x float> %a,16 <vscale x 8 x half> %b,17 <vscale x 8 x half> %c)18 ret <vscale x 4 x float> %out19}20 21;22; FMLALB (Indexed)23;24 25define <vscale x 4 x float> @fmlalb_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {26; CHECK-LABEL: fmlalb_lane_h:27; CHECK: // %bb.0:28; CHECK-NEXT: fmlalb z0.s, z1.h, z2.h[0]29; CHECK-NEXT: ret30 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.lane.nxv4f32(<vscale x 4 x float> %a,31 <vscale x 8 x half> %b,32 <vscale x 8 x half> %c,33 i32 0)34 ret <vscale x 4 x float> %out35}36 37;38; FMLALT (Vectors)39;40 41define <vscale x 4 x float> @fmlalt_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {42; CHECK-LABEL: fmlalt_h:43; CHECK: // %bb.0:44; CHECK-NEXT: fmlalt z0.s, z1.h, z2.h45; CHECK-NEXT: ret46 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.nxv4f32(<vscale x 4 x float> %a,47 <vscale x 8 x half> %b,48 <vscale x 8 x half> %c)49 ret <vscale x 4 x float> %out50}51 52;53; FMLALT (Indexed)54;55 56define <vscale x 4 x float> @fmlalt_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {57; CHECK-LABEL: fmlalt_lane_h:58; CHECK: // %bb.0:59; CHECK-NEXT: fmlalt z0.s, z1.h, z2.h[1]60; CHECK-NEXT: ret61 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.lane.nxv4f32(<vscale x 4 x float> %a,62 <vscale x 8 x half> %b,63 <vscale x 8 x half> %c,64 i32 1)65 ret <vscale x 4 x float> %out66}67 68;69; FMLSLB (Vectors)70;71 72define <vscale x 4 x float> @fmlslb_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {73; CHECK-LABEL: fmlslb_h:74; CHECK: // %bb.0:75; CHECK-NEXT: fmlslb z0.s, z1.h, z2.h76; CHECK-NEXT: ret77 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.nxv4f32(<vscale x 4 x float> %a,78 <vscale x 8 x half> %b,79 <vscale x 8 x half> %c)80 ret <vscale x 4 x float> %out81}82 83;84; FMLSLB (Indexed)85;86 87define <vscale x 4 x float> @fmlslb_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {88; CHECK-LABEL: fmlslb_lane_h:89; CHECK: // %bb.0:90; CHECK-NEXT: fmlslb z0.s, z1.h, z2.h[2]91; CHECK-NEXT: ret92 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.lane.nxv4f32(<vscale x 4 x float> %a,93 <vscale x 8 x half> %b,94 <vscale x 8 x half> %c,95 i32 2)96 ret <vscale x 4 x float> %out97}98 99;100; FMLSLT (Vectors)101;102 103define <vscale x 4 x float> @fmlslt_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {104; CHECK-LABEL: fmlslt_h:105; CHECK: // %bb.0:106; CHECK-NEXT: fmlslt z0.s, z1.h, z2.h107; CHECK-NEXT: ret108 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.nxv4f32(<vscale x 4 x float> %a,109 <vscale x 8 x half> %b,110 <vscale x 8 x half> %c)111 ret <vscale x 4 x float> %out112}113 114;115; FMLSLT (Indexed)116;117 118define <vscale x 4 x float> @fmlslt_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {119; CHECK-LABEL: fmlslt_lane_h:120; CHECK: // %bb.0:121; CHECK-NEXT: fmlslt z0.s, z1.h, z2.h[3]122; CHECK-NEXT: ret123 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.lane.nxv4f32(<vscale x 4 x float> %a,124 <vscale x 8 x half> %b,125 <vscale x 8 x half> %c,126 i32 3)127 ret <vscale x 4 x float> %out128}129 130declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)131declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)132declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)133declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)134 135declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)136declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)137declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)138declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)139