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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6;7; MUL8;9 10define <vscale x 2 x i64> @mul_lane_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {11; CHECK-LABEL: mul_lane_d:12; CHECK: // %bb.0:13; CHECK-NEXT: mul z0.d, z0.d, z1.d[1]14; CHECK-NEXT: ret15 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.lane.nxv2i64(<vscale x 2 x i64> %a,16 <vscale x 2 x i64> %b,17 i32 1)18 ret <vscale x 2 x i64> %out19}20 21define <vscale x 4 x i32> @mul_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {22; CHECK-LABEL: mul_lane_s:23; CHECK: // %bb.0:24; CHECK-NEXT: mul z0.s, z0.s, z1.s[1]25; CHECK-NEXT: ret26 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.lane.nxv4i32(<vscale x 4 x i32> %a,27 <vscale x 4 x i32> %b,28 i32 1)29 ret <vscale x 4 x i32> %out30}31 32define <vscale x 8 x i16> @mul_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {33; CHECK-LABEL: mul_lane_h:34; CHECK: // %bb.0:35; CHECK-NEXT: mul z0.h, z0.h, z1.h[1]36; CHECK-NEXT: ret37 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.lane.nxv8i16(<vscale x 8 x i16> %a,38 <vscale x 8 x i16> %b,39 i32 1)40 ret <vscale x 8 x i16> %out41}42 43;44; MLA45;46 47define <vscale x 2 x i64> @mla_lane_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {48; CHECK-LABEL: mla_lane_d:49; CHECK: // %bb.0:50; CHECK-NEXT: mla z0.d, z1.d, z2.d[1]51; CHECK-NEXT: ret52 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.lane.nxv2i64(<vscale x 2 x i64> %a,53 <vscale x 2 x i64> %b,54 <vscale x 2 x i64> %c,55 i32 1)56 ret <vscale x 2 x i64> %out57}58 59define <vscale x 4 x i32> @mla_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {60; CHECK-LABEL: mla_lane_s:61; CHECK: // %bb.0:62; CHECK-NEXT: mla z0.s, z1.s, z2.s[1]63; CHECK-NEXT: ret64 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.lane.nxv4i32(<vscale x 4 x i32> %a,65 <vscale x 4 x i32> %b,66 <vscale x 4 x i32> %c,67 i32 1)68 ret <vscale x 4 x i32> %out69}70 71define <vscale x 8 x i16> @mla_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {72; CHECK-LABEL: mla_lane_h:73; CHECK: // %bb.0:74; CHECK-NEXT: mla z0.h, z1.h, z2.h[1]75; CHECK-NEXT: ret76 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.lane.nxv8i16(<vscale x 8 x i16> %a,77 <vscale x 8 x i16> %b,78 <vscale x 8 x i16> %c,79 i32 1)80 ret <vscale x 8 x i16> %out81}82 83;84; MLS85;86 87define <vscale x 2 x i64> @mls_lane_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {88; CHECK-LABEL: mls_lane_d:89; CHECK: // %bb.0:90; CHECK-NEXT: mls z0.d, z1.d, z2.d[1]91; CHECK-NEXT: ret92 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.lane.nxv2i64(<vscale x 2 x i64> %a,93 <vscale x 2 x i64> %b,94 <vscale x 2 x i64> %c,95 i32 1)96 ret <vscale x 2 x i64> %out97}98 99define <vscale x 4 x i32> @mls_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {100; CHECK-LABEL: mls_lane_s:101; CHECK: // %bb.0:102; CHECK-NEXT: mls z0.s, z1.s, z2.s[1]103; CHECK-NEXT: ret104 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.lane.nxv4i32(<vscale x 4 x i32> %a,105 <vscale x 4 x i32> %b,106 <vscale x 4 x i32> %c,107 i32 1)108 ret <vscale x 4 x i32> %out109}110 111define <vscale x 8 x i16> @mls_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {112; CHECK-LABEL: mls_lane_h:113; CHECK: // %bb.0:114; CHECK-NEXT: mls z0.h, z1.h, z2.h[1]115; CHECK-NEXT: ret116 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.lane.nxv8i16(<vscale x 8 x i16> %a,117 <vscale x 8 x i16> %b,118 <vscale x 8 x i16> %c,119 i32 1)120 ret <vscale x 8 x i16> %out121}122 123declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)124declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)125declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)126declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)127declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)128declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)129declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)130declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)131declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)132