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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6;7; ADDP8;9 10define <vscale x 16 x i8> @addp_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {11; CHECK-LABEL: addp_i8:12; CHECK: // %bb.0:13; CHECK-NEXT: addp z0.b, p0/m, z0.b, z1.b14; CHECK-NEXT: ret15 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.addp.nxv16i8(<vscale x 16 x i1> %pg,16 <vscale x 16 x i8> %a,17 <vscale x 16 x i8> %b)18 ret <vscale x 16 x i8> %out19}20 21define <vscale x 8 x i16> @addp_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {22; CHECK-LABEL: addp_i16:23; CHECK: // %bb.0:24; CHECK-NEXT: addp z0.h, p0/m, z0.h, z1.h25; CHECK-NEXT: ret26 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.addp.nxv8i16(<vscale x 8 x i1> %pg,27 <vscale x 8 x i16> %a,28 <vscale x 8 x i16> %b)29 ret <vscale x 8 x i16> %out30}31 32define <vscale x 4 x i32> @addp_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {33; CHECK-LABEL: addp_i32:34; CHECK: // %bb.0:35; CHECK-NEXT: addp z0.s, p0/m, z0.s, z1.s36; CHECK-NEXT: ret37 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.addp.nxv4i32(<vscale x 4 x i1> %pg,38 <vscale x 4 x i32> %a,39 <vscale x 4 x i32> %b)40 ret <vscale x 4 x i32> %out41}42 43define <vscale x 2 x i64> @addp_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {44; CHECK-LABEL: addp_i64:45; CHECK: // %bb.0:46; CHECK-NEXT: addp z0.d, p0/m, z0.d, z1.d47; CHECK-NEXT: ret48 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.addp.nxv2i64(<vscale x 2 x i1> %pg,49 <vscale x 2 x i64> %a,50 <vscale x 2 x i64> %b)51 ret <vscale x 2 x i64> %out52}53 54;55; FADDP56;57 58define <vscale x 8 x half> @faddp_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {59; CHECK-LABEL: faddp_f16:60; CHECK: // %bb.0:61; CHECK-NEXT: faddp z0.h, p0/m, z0.h, z1.h62; CHECK-NEXT: ret63 %out = call <vscale x 8 x half> @llvm.aarch64.sve.faddp.nxv8f16(<vscale x 8 x i1> %pg,64 <vscale x 8 x half> %a,65 <vscale x 8 x half> %b)66 ret <vscale x 8 x half> %out67}68 69define <vscale x 4 x float> @faddp_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {70; CHECK-LABEL: faddp_f32:71; CHECK: // %bb.0:72; CHECK-NEXT: faddp z0.s, p0/m, z0.s, z1.s73; CHECK-NEXT: ret74 %out = call <vscale x 4 x float> @llvm.aarch64.sve.faddp.nxv4f32(<vscale x 4 x i1> %pg,75 <vscale x 4 x float> %a,76 <vscale x 4 x float> %b)77 ret <vscale x 4 x float> %out78}79 80define <vscale x 2 x double> @faddp_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {81; CHECK-LABEL: faddp_f64:82; CHECK: // %bb.0:83; CHECK-NEXT: faddp z0.d, p0/m, z0.d, z1.d84; CHECK-NEXT: ret85 %out = call <vscale x 2 x double> @llvm.aarch64.sve.faddp.nxv2f64(<vscale x 2 x i1> %pg,86 <vscale x 2 x double> %a,87 <vscale x 2 x double> %b)88 ret <vscale x 2 x double> %out89}90 91;92; FMAXP93;94 95define <vscale x 8 x half> @fmaxp_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {96; CHECK-LABEL: fmaxp_f16:97; CHECK: // %bb.0:98; CHECK-NEXT: fmaxp z0.h, p0/m, z0.h, z1.h99; CHECK-NEXT: ret100 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxp.nxv8f16(<vscale x 8 x i1> %pg,101 <vscale x 8 x half> %a,102 <vscale x 8 x half> %b)103 ret <vscale x 8 x half> %out104}105 106define <vscale x 4 x float> @fmaxp_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {107; CHECK-LABEL: fmaxp_f32:108; CHECK: // %bb.0:109; CHECK-NEXT: fmaxp z0.s, p0/m, z0.s, z1.s110; CHECK-NEXT: ret111 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxp.nxv4f32(<vscale x 4 x i1> %pg,112 <vscale x 4 x float> %a,113 <vscale x 4 x float> %b)114 ret <vscale x 4 x float> %out115}116 117define <vscale x 2 x double> @fmaxp_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {118; CHECK-LABEL: fmaxp_f64:119; CHECK: // %bb.0:120; CHECK-NEXT: fmaxp z0.d, p0/m, z0.d, z1.d121; CHECK-NEXT: ret122 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxp.nxv2f64(<vscale x 2 x i1> %pg,123 <vscale x 2 x double> %a,124 <vscale x 2 x double> %b)125 ret <vscale x 2 x double> %out126}127 128;129; FMAXNMP130;131 132define <vscale x 8 x half> @fmaxnmp_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {133; CHECK-LABEL: fmaxnmp_f16:134; CHECK: // %bb.0:135; CHECK-NEXT: fmaxnmp z0.h, p0/m, z0.h, z1.h136; CHECK-NEXT: ret137 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnmp.nxv8f16(<vscale x 8 x i1> %pg,138 <vscale x 8 x half> %a,139 <vscale x 8 x half> %b)140 ret <vscale x 8 x half> %out141}142 143define <vscale x 4 x float> @fmaxnmp_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {144; CHECK-LABEL: fmaxnmp_f32:145; CHECK: // %bb.0:146; CHECK-NEXT: fmaxnmp z0.s, p0/m, z0.s, z1.s147; CHECK-NEXT: ret148 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnmp.nxv4f32(<vscale x 4 x i1> %pg,149 <vscale x 4 x float> %a,150 <vscale x 4 x float> %b)151 ret <vscale x 4 x float> %out152}153 154define <vscale x 2 x double> @fmaxnmp_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {155; CHECK-LABEL: fmaxnmp_f64:156; CHECK: // %bb.0:157; CHECK-NEXT: fmaxnmp z0.d, p0/m, z0.d, z1.d158; CHECK-NEXT: ret159 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnmp.nxv2f64(<vscale x 2 x i1> %pg,160 <vscale x 2 x double> %a,161 <vscale x 2 x double> %b)162 ret <vscale x 2 x double> %out163}164 165;166; FMINP167;168 169define <vscale x 8 x half> @fminp_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {170; CHECK-LABEL: fminp_f16:171; CHECK: // %bb.0:172; CHECK-NEXT: fminp z0.h, p0/m, z0.h, z1.h173; CHECK-NEXT: ret174 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fminp.nxv8f16(<vscale x 8 x i1> %pg,175 <vscale x 8 x half> %a,176 <vscale x 8 x half> %b)177 ret <vscale x 8 x half> %out178}179 180define <vscale x 4 x float> @fminp_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {181; CHECK-LABEL: fminp_f32:182; CHECK: // %bb.0:183; CHECK-NEXT: fminp z0.s, p0/m, z0.s, z1.s184; CHECK-NEXT: ret185 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fminp.nxv4f32(<vscale x 4 x i1> %pg,186 <vscale x 4 x float> %a,187 <vscale x 4 x float> %b)188 ret <vscale x 4 x float> %out189}190 191define <vscale x 2 x double> @fminp_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {192; CHECK-LABEL: fminp_f64:193; CHECK: // %bb.0:194; CHECK-NEXT: fminp z0.d, p0/m, z0.d, z1.d195; CHECK-NEXT: ret196 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fminp.nxv2f64(<vscale x 2 x i1> %pg,197 <vscale x 2 x double> %a,198 <vscale x 2 x double> %b)199 ret <vscale x 2 x double> %out200}201 202;203; FMINNMP204;205 206define <vscale x 8 x half> @fminnmp_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {207; CHECK-LABEL: fminnmp_f16:208; CHECK: // %bb.0:209; CHECK-NEXT: fminnmp z0.h, p0/m, z0.h, z1.h210; CHECK-NEXT: ret211 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fminnmp.nxv8f16(<vscale x 8 x i1> %pg,212 <vscale x 8 x half> %a,213 <vscale x 8 x half> %b)214 ret <vscale x 8 x half> %out215}216 217define <vscale x 4 x float> @fminnmp_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {218; CHECK-LABEL: fminnmp_f32:219; CHECK: // %bb.0:220; CHECK-NEXT: fminnmp z0.s, p0/m, z0.s, z1.s221; CHECK-NEXT: ret222 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fminnmp.nxv4f32(<vscale x 4 x i1> %pg,223 <vscale x 4 x float> %a,224 <vscale x 4 x float> %b)225 ret <vscale x 4 x float> %out226}227 228define <vscale x 2 x double> @fminnmp_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {229; CHECK-LABEL: fminnmp_f64:230; CHECK: // %bb.0:231; CHECK-NEXT: fminnmp z0.d, p0/m, z0.d, z1.d232; CHECK-NEXT: ret233 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fminnmp.nxv2f64(<vscale x 2 x i1> %pg,234 <vscale x 2 x double> %a,235 <vscale x 2 x double> %b)236 ret <vscale x 2 x double> %out237}238 239;240; SMAXP241;242 243define <vscale x 16 x i8> @smaxp_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {244; CHECK-LABEL: smaxp_i8:245; CHECK: // %bb.0:246; CHECK-NEXT: smaxp z0.b, p0/m, z0.b, z1.b247; CHECK-NEXT: ret248 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smaxp.nxv16i8(<vscale x 16 x i1> %pg,249 <vscale x 16 x i8> %a,250 <vscale x 16 x i8> %b)251 ret <vscale x 16 x i8> %out252}253 254define <vscale x 8 x i16> @smaxp_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {255; CHECK-LABEL: smaxp_i16:256; CHECK: // %bb.0:257; CHECK-NEXT: smaxp z0.h, p0/m, z0.h, z1.h258; CHECK-NEXT: ret259 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smaxp.nxv8i16(<vscale x 8 x i1> %pg,260 <vscale x 8 x i16> %a,261 <vscale x 8 x i16> %b)262 ret <vscale x 8 x i16> %out263}264 265define <vscale x 4 x i32> @smaxp_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {266; CHECK-LABEL: smaxp_i32:267; CHECK: // %bb.0:268; CHECK-NEXT: smaxp z0.s, p0/m, z0.s, z1.s269; CHECK-NEXT: ret270 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smaxp.nxv4i32(<vscale x 4 x i1> %pg,271 <vscale x 4 x i32> %a,272 <vscale x 4 x i32> %b)273 ret <vscale x 4 x i32> %out274}275 276define <vscale x 2 x i64> @smaxp_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {277; CHECK-LABEL: smaxp_i64:278; CHECK: // %bb.0:279; CHECK-NEXT: smaxp z0.d, p0/m, z0.d, z1.d280; CHECK-NEXT: ret281 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smaxp.nxv2i64(<vscale x 2 x i1> %pg,282 <vscale x 2 x i64> %a,283 <vscale x 2 x i64> %b)284 ret <vscale x 2 x i64> %out285}286 287;288; SMINP289;290 291define <vscale x 16 x i8> @sminp_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {292; CHECK-LABEL: sminp_i8:293; CHECK: // %bb.0:294; CHECK-NEXT: sminp z0.b, p0/m, z0.b, z1.b295; CHECK-NEXT: ret296 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sminp.nxv16i8(<vscale x 16 x i1> %pg,297 <vscale x 16 x i8> %a,298 <vscale x 16 x i8> %b)299 ret <vscale x 16 x i8> %out300}301 302define <vscale x 8 x i16> @sminp_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {303; CHECK-LABEL: sminp_i16:304; CHECK: // %bb.0:305; CHECK-NEXT: sminp z0.h, p0/m, z0.h, z1.h306; CHECK-NEXT: ret307 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sminp.nxv8i16(<vscale x 8 x i1> %pg,308 <vscale x 8 x i16> %a,309 <vscale x 8 x i16> %b)310 ret <vscale x 8 x i16> %out311}312 313define <vscale x 4 x i32> @sminp_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {314; CHECK-LABEL: sminp_i32:315; CHECK: // %bb.0:316; CHECK-NEXT: sminp z0.s, p0/m, z0.s, z1.s317; CHECK-NEXT: ret318 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sminp.nxv4i32(<vscale x 4 x i1> %pg,319 <vscale x 4 x i32> %a,320 <vscale x 4 x i32> %b)321 ret <vscale x 4 x i32> %out322}323 324define <vscale x 2 x i64> @sminp_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {325; CHECK-LABEL: sminp_i64:326; CHECK: // %bb.0:327; CHECK-NEXT: sminp z0.d, p0/m, z0.d, z1.d328; CHECK-NEXT: ret329 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sminp.nxv2i64(<vscale x 2 x i1> %pg,330 <vscale x 2 x i64> %a,331 <vscale x 2 x i64> %b)332 ret <vscale x 2 x i64> %out333}334 335;336; UMINP337;338 339define <vscale x 16 x i8> @uminp_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {340; CHECK-LABEL: uminp_i8:341; CHECK: // %bb.0:342; CHECK-NEXT: uminp z0.b, p0/m, z0.b, z1.b343; CHECK-NEXT: ret344 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uminp.nxv16i8(<vscale x 16 x i1> %pg,345 <vscale x 16 x i8> %a,346 <vscale x 16 x i8> %b)347 ret <vscale x 16 x i8> %out348}349 350define <vscale x 8 x i16> @uminp_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {351; CHECK-LABEL: uminp_i16:352; CHECK: // %bb.0:353; CHECK-NEXT: uminp z0.h, p0/m, z0.h, z1.h354; CHECK-NEXT: ret355 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uminp.nxv8i16(<vscale x 8 x i1> %pg,356 <vscale x 8 x i16> %a,357 <vscale x 8 x i16> %b)358 ret <vscale x 8 x i16> %out359}360 361define <vscale x 4 x i32> @uminp_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {362; CHECK-LABEL: uminp_i32:363; CHECK: // %bb.0:364; CHECK-NEXT: uminp z0.s, p0/m, z0.s, z1.s365; CHECK-NEXT: ret366 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uminp.nxv4i32(<vscale x 4 x i1> %pg,367 <vscale x 4 x i32> %a,368 <vscale x 4 x i32> %b)369 ret <vscale x 4 x i32> %out370}371 372define <vscale x 2 x i64> @uminp_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {373; CHECK-LABEL: uminp_i64:374; CHECK: // %bb.0:375; CHECK-NEXT: uminp z0.d, p0/m, z0.d, z1.d376; CHECK-NEXT: ret377 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uminp.nxv2i64(<vscale x 2 x i1> %pg,378 <vscale x 2 x i64> %a,379 <vscale x 2 x i64> %b)380 ret <vscale x 2 x i64> %out381}382 383;384; UMAXP385;386 387define <vscale x 16 x i8> @umaxp_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {388; CHECK-LABEL: umaxp_i8:389; CHECK: // %bb.0:390; CHECK-NEXT: umaxp z0.b, p0/m, z0.b, z1.b391; CHECK-NEXT: ret392 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umaxp.nxv16i8(<vscale x 16 x i1> %pg,393 <vscale x 16 x i8> %a,394 <vscale x 16 x i8> %b)395 ret <vscale x 16 x i8> %out396}397 398define <vscale x 8 x i16> @umaxp_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {399; CHECK-LABEL: umaxp_i16:400; CHECK: // %bb.0:401; CHECK-NEXT: umaxp z0.h, p0/m, z0.h, z1.h402; CHECK-NEXT: ret403 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umaxp.nxv8i16(<vscale x 8 x i1> %pg,404 <vscale x 8 x i16> %a,405 <vscale x 8 x i16> %b)406 ret <vscale x 8 x i16> %out407}408 409define <vscale x 4 x i32> @umaxp_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {410; CHECK-LABEL: umaxp_i32:411; CHECK: // %bb.0:412; CHECK-NEXT: umaxp z0.s, p0/m, z0.s, z1.s413; CHECK-NEXT: ret414 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umaxp.nxv4i32(<vscale x 4 x i1> %pg,415 <vscale x 4 x i32> %a,416 <vscale x 4 x i32> %b)417 ret <vscale x 4 x i32> %out418}419 420define <vscale x 2 x i64> @umaxp_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {421; CHECK-LABEL: umaxp_i64:422; CHECK: // %bb.0:423; CHECK-NEXT: umaxp z0.d, p0/m, z0.d, z1.d424; CHECK-NEXT: ret425 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umaxp.nxv2i64(<vscale x 2 x i1> %pg,426 <vscale x 2 x i64> %a,427 <vscale x 2 x i64> %b)428 ret <vscale x 2 x i64> %out429}430 431declare <vscale x 16 x i8> @llvm.aarch64.sve.addp.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)432declare <vscale x 8 x i16> @llvm.aarch64.sve.addp.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)433declare <vscale x 4 x i32> @llvm.aarch64.sve.addp.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)434declare <vscale x 2 x i64> @llvm.aarch64.sve.addp.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)435 436declare <vscale x 8 x half> @llvm.aarch64.sve.faddp.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)437declare <vscale x 4 x float> @llvm.aarch64.sve.faddp.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)438declare <vscale x 2 x double> @llvm.aarch64.sve.faddp.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)439 440declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxp.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)441declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxp.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)442declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxp.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)443 444declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnmp.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)445declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnmp.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)446declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnmp.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)447 448declare <vscale x 8 x half> @llvm.aarch64.sve.fminp.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)449declare <vscale x 4 x float> @llvm.aarch64.sve.fminp.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)450declare <vscale x 2 x double> @llvm.aarch64.sve.fminp.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)451 452declare <vscale x 8 x half> @llvm.aarch64.sve.fminnmp.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)453declare <vscale x 4 x float> @llvm.aarch64.sve.fminnmp.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)454declare <vscale x 2 x double> @llvm.aarch64.sve.fminnmp.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)455 456declare <vscale x 16 x i8> @llvm.aarch64.sve.smaxp.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)457declare <vscale x 8 x i16> @llvm.aarch64.sve.smaxp.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)458declare <vscale x 4 x i32> @llvm.aarch64.sve.smaxp.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)459declare <vscale x 2 x i64> @llvm.aarch64.sve.smaxp.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)460 461declare <vscale x 16 x i8> @llvm.aarch64.sve.sminp.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)462declare <vscale x 8 x i16> @llvm.aarch64.sve.sminp.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)463declare <vscale x 4 x i32> @llvm.aarch64.sve.sminp.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)464declare <vscale x 2 x i64> @llvm.aarch64.sve.sminp.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)465 466declare <vscale x 16 x i8> @llvm.aarch64.sve.umaxp.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)467declare <vscale x 8 x i16> @llvm.aarch64.sve.umaxp.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)468declare <vscale x 4 x i32> @llvm.aarch64.sve.umaxp.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)469declare <vscale x 2 x i64> @llvm.aarch64.sve.umaxp.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)470 471declare <vscale x 16 x i8> @llvm.aarch64.sve.uminp.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)472declare <vscale x 8 x i16> @llvm.aarch64.sve.uminp.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)473declare <vscale x 4 x i32> @llvm.aarch64.sve.uminp.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)474declare <vscale x 2 x i64> @llvm.aarch64.sve.uminp.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)475