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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3 4;5; TBL26;7 8define <vscale x 16 x i8> @tbl2_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %unused, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {9; CHECK-LABEL: tbl2_b:10; CHECK: // %bb.0:11; CHECK-NEXT: // kill: def $z2 killed $z2 def $z1_z212; CHECK-NEXT: mov z1.d, z0.d13; CHECK-NEXT: tbl z0.b, { z1.b, z2.b }, z3.b14; CHECK-NEXT: ret15 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl2.nxv16i8(<vscale x 16 x i8> %a,16 <vscale x 16 x i8> %b,17 <vscale x 16 x i8> %c)18 ret <vscale x 16 x i8> %out19}20 21define <vscale x 8 x i16> @tbl2_h(<vscale x 8 x i16> %a, <vscale x 16 x i8> %unused, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {22; CHECK-LABEL: tbl2_h:23; CHECK: // %bb.0:24; CHECK-NEXT: // kill: def $z2 killed $z2 def $z1_z225; CHECK-NEXT: mov z1.d, z0.d26; CHECK-NEXT: tbl z0.h, { z1.h, z2.h }, z3.h27; CHECK-NEXT: ret28 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl2.nxv8i16(<vscale x 8 x i16> %a,29 <vscale x 8 x i16> %b,30 <vscale x 8 x i16> %c)31 ret <vscale x 8 x i16> %out32}33 34define <vscale x 4 x i32> @tbl2_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %unused, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {35; CHECK-LABEL: tbl2_s:36; CHECK: // %bb.0:37; CHECK-NEXT: // kill: def $z2 killed $z2 def $z1_z238; CHECK-NEXT: mov z1.d, z0.d39; CHECK-NEXT: tbl z0.s, { z1.s, z2.s }, z3.s40; CHECK-NEXT: ret41 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl2.nxv4i32(<vscale x 4 x i32> %a,42 <vscale x 4 x i32> %b,43 <vscale x 4 x i32> %c)44 ret <vscale x 4 x i32> %out45}46 47define <vscale x 2 x i64> @tbl2_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %unused, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {48; CHECK-LABEL: tbl2_d:49; CHECK: // %bb.0:50; CHECK-NEXT: // kill: def $z2 killed $z2 def $z1_z251; CHECK-NEXT: mov z1.d, z0.d52; CHECK-NEXT: tbl z0.d, { z1.d, z2.d }, z3.d53; CHECK-NEXT: ret54 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl2.nxv2i64(<vscale x 2 x i64> %a,55 <vscale x 2 x i64> %b,56 <vscale x 2 x i64> %c)57 ret <vscale x 2 x i64> %out58}59 60define <vscale x 8 x half> @tbl2_fh(<vscale x 8 x half> %a, <vscale x 8 x half> %unused, <vscale x 8 x half> %b, <vscale x 8 x i16> %c) {61; CHECK-LABEL: tbl2_fh:62; CHECK: // %bb.0:63; CHECK-NEXT: // kill: def $z2 killed $z2 def $z1_z264; CHECK-NEXT: mov z1.d, z0.d65; CHECK-NEXT: tbl z0.h, { z1.h, z2.h }, z3.h66; CHECK-NEXT: ret67 %out = call <vscale x 8 x half> @llvm.aarch64.sve.tbl2.nxv8f16(<vscale x 8 x half> %a,68 <vscale x 8 x half> %b,69 <vscale x 8 x i16> %c)70 ret <vscale x 8 x half> %out71}72 73define <vscale x 8 x bfloat> @tbl2_bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %unused, <vscale x 8 x bfloat> %b, <vscale x 8 x i16> %c) #0 {74; CHECK-LABEL: tbl2_bf16:75; CHECK: // %bb.0:76; CHECK-NEXT: // kill: def $z2 killed $z2 def $z1_z277; CHECK-NEXT: mov z1.d, z0.d78; CHECK-NEXT: tbl z0.h, { z1.h, z2.h }, z3.h79; CHECK-NEXT: ret80 %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl2.nxv8bf16(<vscale x 8 x bfloat> %a,81 <vscale x 8 x bfloat> %b,82 <vscale x 8 x i16> %c)83 ret <vscale x 8 x bfloat> %out84}85 86define <vscale x 4 x float> @tbl2_fs(<vscale x 4 x float> %a, <vscale x 4 x float> %unused, <vscale x 4 x float> %b, <vscale x 4 x i32> %c) {87; CHECK-LABEL: tbl2_fs:88; CHECK: // %bb.0:89; CHECK-NEXT: // kill: def $z2 killed $z2 def $z1_z290; CHECK-NEXT: mov z1.d, z0.d91; CHECK-NEXT: tbl z0.s, { z1.s, z2.s }, z3.s92; CHECK-NEXT: ret93 %out = call <vscale x 4 x float> @llvm.aarch64.sve.tbl2.nxv4f32(<vscale x 4 x float> %a,94 <vscale x 4 x float> %b,95 <vscale x 4 x i32> %c)96 ret <vscale x 4 x float> %out97}98 99define <vscale x 2 x double> @tbl2_fd(<vscale x 2 x double> %a, <vscale x 2 x double> %unused, <vscale x 2 x double> %b, <vscale x 2 x i64> %c) {100; CHECK-LABEL: tbl2_fd:101; CHECK: // %bb.0:102; CHECK-NEXT: // kill: def $z2 killed $z2 def $z1_z2103; CHECK-NEXT: mov z1.d, z0.d104; CHECK-NEXT: tbl z0.d, { z1.d, z2.d }, z3.d105; CHECK-NEXT: ret106 %out = call <vscale x 2 x double> @llvm.aarch64.sve.tbl2.nxv2f64(<vscale x 2 x double> %a,107 <vscale x 2 x double> %b,108 <vscale x 2 x i64> %c)109 ret <vscale x 2 x double> %out110}111 112;113; TBX114;115 116define <vscale x 16 x i8> @tbx_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {117; CHECK-LABEL: tbx_b:118; CHECK: // %bb.0:119; CHECK-NEXT: tbx z0.b, z1.b, z2.b120; CHECK-NEXT: ret121 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.tbx.nxv16i8(<vscale x 16 x i8> %a,122 <vscale x 16 x i8> %b,123 <vscale x 16 x i8> %c)124 ret <vscale x 16 x i8> %out125}126 127define <vscale x 8 x i16> @tbx_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {128; CHECK-LABEL: tbx_h:129; CHECK: // %bb.0:130; CHECK-NEXT: tbx z0.h, z1.h, z2.h131; CHECK-NEXT: ret132 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.tbx.nxv8i16(<vscale x 8 x i16> %a,133 <vscale x 8 x i16> %b,134 <vscale x 8 x i16> %c)135 ret <vscale x 8 x i16> %out136}137 138define <vscale x 8 x half> @ftbx_h(<vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x i16> %c) {139; CHECK-LABEL: ftbx_h:140; CHECK: // %bb.0:141; CHECK-NEXT: tbx z0.h, z1.h, z2.h142; CHECK-NEXT: ret143 %out = call <vscale x 8 x half> @llvm.aarch64.sve.tbx.nxv8f16(<vscale x 8 x half> %a,144 <vscale x 8 x half> %b,145 <vscale x 8 x i16> %c)146 ret <vscale x 8 x half> %out147}148 149define <vscale x 8 x bfloat> @ftbx_h_bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x i16> %c) #0 {150; CHECK-LABEL: ftbx_h_bf16:151; CHECK: // %bb.0:152; CHECK-NEXT: tbx z0.h, z1.h, z2.h153; CHECK-NEXT: ret154 %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tbx.nxv8bf16(<vscale x 8 x bfloat> %a,155 <vscale x 8 x bfloat> %b,156 <vscale x 8 x i16> %c)157 ret <vscale x 8 x bfloat> %out158}159 160define <vscale x 4 x i32> @tbx_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {161; CHECK-LABEL: tbx_s:162; CHECK: // %bb.0:163; CHECK-NEXT: tbx z0.s, z1.s, z2.s164; CHECK-NEXT: ret165 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.tbx.nxv4i32(<vscale x 4 x i32> %a,166 <vscale x 4 x i32> %b,167 <vscale x 4 x i32> %c)168 ret <vscale x 4 x i32> %out169}170 171define <vscale x 4 x float> @ftbx_s(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x i32> %c) {172; CHECK-LABEL: ftbx_s:173; CHECK: // %bb.0:174; CHECK-NEXT: tbx z0.s, z1.s, z2.s175; CHECK-NEXT: ret176 %out = call <vscale x 4 x float> @llvm.aarch64.sve.tbx.nxv4f32(<vscale x 4 x float> %a,177 <vscale x 4 x float> %b,178 <vscale x 4 x i32> %c)179 ret <vscale x 4 x float> %out180}181 182define <vscale x 2 x i64> @tbx_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {183; CHECK-LABEL: tbx_d:184; CHECK: // %bb.0:185; CHECK-NEXT: tbx z0.d, z1.d, z2.d186; CHECK-NEXT: ret187 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.tbx.nxv2i64(<vscale x 2 x i64> %a,188 <vscale x 2 x i64> %b,189 <vscale x 2 x i64> %c)190 ret <vscale x 2 x i64> %out191}192 193define <vscale x 2 x double> @ftbx_d(<vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x i64> %c) {194; CHECK-LABEL: ftbx_d:195; CHECK: // %bb.0:196; CHECK-NEXT: tbx z0.d, z1.d, z2.d197; CHECK-NEXT: ret198 %out = call <vscale x 2 x double> @llvm.aarch64.sve.tbx.nxv2f64(<vscale x 2 x double> %a,199 <vscale x 2 x double> %b,200 <vscale x 2 x i64> %c)201 ret <vscale x 2 x double> %out202}203 204declare <vscale x 16 x i8> @llvm.aarch64.sve.tbl2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)205declare <vscale x 8 x i16> @llvm.aarch64.sve.tbl2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)206declare <vscale x 4 x i32> @llvm.aarch64.sve.tbl2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)207declare <vscale x 2 x i64> @llvm.aarch64.sve.tbl2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)208 209declare <vscale x 8 x half> @llvm.aarch64.sve.tbl2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>)210declare <vscale x 4 x float> @llvm.aarch64.sve.tbl2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i32>)211declare <vscale x 2 x double> @llvm.aarch64.sve.tbl2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i64>)212 213declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>)214 215declare <vscale x 16 x i8> @llvm.aarch64.sve.tbx.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)216declare <vscale x 8 x i16> @llvm.aarch64.sve.tbx.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)217declare <vscale x 4 x i32> @llvm.aarch64.sve.tbx.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)218declare <vscale x 2 x i64> @llvm.aarch64.sve.tbx.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)219 220declare <vscale x 8 x half> @llvm.aarch64.sve.tbx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>)221declare <vscale x 4 x float> @llvm.aarch64.sve.tbx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i32>)222declare <vscale x 2 x double> @llvm.aarch64.sve.tbx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i64>)223 224declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tbx.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>)225 226; +bf16 is required for the bfloat version.227attributes #0 = { "target-features"="+sve2,+bf16" }228