94 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,sme -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming -verify-machineinstrs < %s | FileCheck %s5 6define <vscale x 16 x i1> @psel_b(<vscale x 16 x i1> %p1, <vscale x 16 x i1> %p2, i32 %idx) {7; CHECK-LABEL: psel_b:8; CHECK: // %bb.0:9; CHECK-NEXT: mov w12, w010; CHECK-NEXT: psel p0, p0, p1.b[w12, 0]11; CHECK-NEXT: ret12 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> %p1, <vscale x 16 x i1> %p2, i32 %idx)13 ret <vscale x 16 x i1> %res14}15 16define <vscale x 16 x i1> @psel_b_imm(<vscale x 16 x i1> %p1, <vscale x 16 x i1> %p2, i32 %idx) {17; CHECK-LABEL: psel_b_imm:18; CHECK: // %bb.0:19; CHECK-NEXT: mov w12, w020; CHECK-NEXT: psel p0, p0, p1.b[w12, 15]21; CHECK-NEXT: ret22 %add = add i32 %idx, 1523 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> %p1, <vscale x 16 x i1> %p2, i32 %add)24 ret <vscale x 16 x i1> %res25}26 27define <vscale x 16 x i1> @psel_h(<vscale x 16 x i1> %p1, <vscale x 8 x i1> %p2, i32 %idx) {28; CHECK-LABEL: psel_h:29; CHECK: // %bb.0:30; CHECK-NEXT: mov w12, w031; CHECK-NEXT: psel p0, p0, p1.h[w12, 0]32; CHECK-NEXT: ret33 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> %p1, <vscale x 8 x i1> %p2, i32 %idx)34 ret <vscale x 16 x i1> %res35}36 37define <vscale x 16 x i1> @psel_h_imm(<vscale x 16 x i1> %p1, <vscale x 8 x i1> %p2, i32 %idx) {38; CHECK-LABEL: psel_h_imm:39; CHECK: // %bb.0:40; CHECK-NEXT: mov w12, w041; CHECK-NEXT: psel p0, p0, p1.h[w12, 7]42; CHECK-NEXT: ret43 %add = add i32 %idx, 744 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> %p1, <vscale x 8 x i1> %p2, i32 %add)45 ret <vscale x 16 x i1> %res46}47 48define <vscale x 16 x i1> @psel_s(<vscale x 16 x i1> %p1, <vscale x 4 x i1> %p2, i32 %idx) {49; CHECK-LABEL: psel_s:50; CHECK: // %bb.0:51; CHECK-NEXT: mov w12, w052; CHECK-NEXT: psel p0, p0, p1.s[w12, 0]53; CHECK-NEXT: ret54 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> %p1, <vscale x 4 x i1> %p2, i32 %idx)55 ret <vscale x 16 x i1> %res56}57 58define <vscale x 16 x i1> @psel_s_imm(<vscale x 16 x i1> %p1, <vscale x 4 x i1> %p2, i32 %idx) {59; CHECK-LABEL: psel_s_imm:60; CHECK: // %bb.0:61; CHECK-NEXT: mov w12, w062; CHECK-NEXT: psel p0, p0, p1.s[w12, 3]63; CHECK-NEXT: ret64 %add = add i32 %idx, 365 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> %p1, <vscale x 4 x i1> %p2, i32 %add)66 ret <vscale x 16 x i1> %res67}68 69define <vscale x 16 x i1> @psel_d(<vscale x 16 x i1> %p1, <vscale x 2 x i1> %p2, i32 %idx) {70; CHECK-LABEL: psel_d:71; CHECK: // %bb.0:72; CHECK-NEXT: mov w12, w073; CHECK-NEXT: psel p0, p0, p1.d[w12, 0]74; CHECK-NEXT: ret75 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> %p1, <vscale x 2 x i1> %p2, i32 %idx)76 ret <vscale x 16 x i1> %res77}78 79define <vscale x 16 x i1> @psel_d_imm(<vscale x 16 x i1> %p1, <vscale x 2 x i1> %p2, i32 %idx) {80; CHECK-LABEL: psel_d_imm:81; CHECK: // %bb.0:82; CHECK-NEXT: mov w12, w083; CHECK-NEXT: psel p0, p0, p1.d[w12, 1]84; CHECK-NEXT: ret85 %add = add i32 %idx, 186 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> %p1, <vscale x 2 x i1> %p2, i32 %add)87 ret <vscale x 16 x i1> %res88}89 90declare <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, i32)91declare <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1>, <vscale x 8 x i1>, i32)92declare <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i32)93declare <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1>, <vscale x 2 x i1>, i32)94