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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6;7; SQXTNB8;9 10define <vscale x 16 x i8> @sqxtnb_h(<vscale x 8 x i16> %a) {11; CHECK-LABEL: sqxtnb_h:12; CHECK: // %bb.0:13; CHECK-NEXT: sqxtnb z0.b, z0.h14; CHECK-NEXT: ret15 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnb.nxv8i16(<vscale x 8 x i16> %a)16 ret <vscale x 16 x i8> %out17}18 19define <vscale x 8 x i16> @sqxtnb_s(<vscale x 4 x i32> %a) {20; CHECK-LABEL: sqxtnb_s:21; CHECK: // %bb.0:22; CHECK-NEXT: sqxtnb z0.h, z0.s23; CHECK-NEXT: ret24 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnb.nxv4i32(<vscale x 4 x i32> %a)25 ret <vscale x 8 x i16> %out26}27 28define <vscale x 4 x i32> @sqxtnb_d(<vscale x 2 x i64> %a) {29; CHECK-LABEL: sqxtnb_d:30; CHECK: // %bb.0:31; CHECK-NEXT: sqxtnb z0.s, z0.d32; CHECK-NEXT: ret33 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnb.nxv2i64(<vscale x 2 x i64> %a)34 ret <vscale x 4 x i32> %out35}36 37;38; UQXTNB39;40 41define <vscale x 16 x i8> @uqxtnb_h(<vscale x 8 x i16> %a) {42; CHECK-LABEL: uqxtnb_h:43; CHECK: // %bb.0:44; CHECK-NEXT: uqxtnb z0.b, z0.h45; CHECK-NEXT: ret46 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnb.nxv8i16(<vscale x 8 x i16> %a)47 ret <vscale x 16 x i8> %out48}49 50define <vscale x 8 x i16> @uqxtnb_s(<vscale x 4 x i32> %a) {51; CHECK-LABEL: uqxtnb_s:52; CHECK: // %bb.0:53; CHECK-NEXT: uqxtnb z0.h, z0.s54; CHECK-NEXT: ret55 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnb.nxv4i32(<vscale x 4 x i32> %a)56 ret <vscale x 8 x i16> %out57}58 59define <vscale x 4 x i32> @uqxtnb_d(<vscale x 2 x i64> %a) {60; CHECK-LABEL: uqxtnb_d:61; CHECK: // %bb.0:62; CHECK-NEXT: uqxtnb z0.s, z0.d63; CHECK-NEXT: ret64 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnb.nxv2i64(<vscale x 2 x i64> %a)65 ret <vscale x 4 x i32> %out66}67 68;69; SQXTUNB70;71 72define <vscale x 16 x i8> @sqxtunb_h(<vscale x 8 x i16> %a) {73; CHECK-LABEL: sqxtunb_h:74; CHECK: // %bb.0:75; CHECK-NEXT: sqxtunb z0.b, z0.h76; CHECK-NEXT: ret77 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunb.nxv8i16(<vscale x 8 x i16> %a)78 ret <vscale x 16 x i8> %out79}80 81define <vscale x 8 x i16> @sqxtunb_s(<vscale x 4 x i32> %a) {82; CHECK-LABEL: sqxtunb_s:83; CHECK: // %bb.0:84; CHECK-NEXT: sqxtunb z0.h, z0.s85; CHECK-NEXT: ret86 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunb.nxv4i32(<vscale x 4 x i32> %a)87 ret <vscale x 8 x i16> %out88}89 90define <vscale x 4 x i32> @sqxtunb_d(<vscale x 2 x i64> %a) {91; CHECK-LABEL: sqxtunb_d:92; CHECK: // %bb.0:93; CHECK-NEXT: sqxtunb z0.s, z0.d94; CHECK-NEXT: ret95 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunb.nxv2i64(<vscale x 2 x i64> %a)96 ret <vscale x 4 x i32> %out97}98 99;100; SQXTNT101;102 103define <vscale x 16 x i8> @sqxtnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {104; CHECK-LABEL: sqxtnt_h:105; CHECK: // %bb.0:106; CHECK-NEXT: sqxtnt z0.b, z1.h107; CHECK-NEXT: ret108 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnt.nxv8i16(<vscale x 16 x i8> %a,109 <vscale x 8 x i16> %b)110 ret <vscale x 16 x i8> %out111}112 113define <vscale x 8 x i16> @sqxtnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {114; CHECK-LABEL: sqxtnt_s:115; CHECK: // %bb.0:116; CHECK-NEXT: sqxtnt z0.h, z1.s117; CHECK-NEXT: ret118 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnt.nxv4i32(<vscale x 8 x i16> %a,119 <vscale x 4 x i32> %b)120 ret <vscale x 8 x i16> %out121}122 123define <vscale x 4 x i32> @sqxtnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {124; CHECK-LABEL: sqxtnt_d:125; CHECK: // %bb.0:126; CHECK-NEXT: sqxtnt z0.s, z1.d127; CHECK-NEXT: ret128 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnt.nxv2i64(<vscale x 4 x i32> %a,129 <vscale x 2 x i64> %b)130 ret <vscale x 4 x i32> %out131}132 133;134; UQXTNT135;136 137define <vscale x 16 x i8> @uqxtnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {138; CHECK-LABEL: uqxtnt_h:139; CHECK: // %bb.0:140; CHECK-NEXT: uqxtnt z0.b, z1.h141; CHECK-NEXT: ret142 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnt.nxv8i16(<vscale x 16 x i8> %a,143 <vscale x 8 x i16> %b)144 ret <vscale x 16 x i8> %out145}146 147define <vscale x 8 x i16> @uqxtnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {148; CHECK-LABEL: uqxtnt_s:149; CHECK: // %bb.0:150; CHECK-NEXT: uqxtnt z0.h, z1.s151; CHECK-NEXT: ret152 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnt.nxv4i32(<vscale x 8 x i16> %a,153 <vscale x 4 x i32> %b)154 ret <vscale x 8 x i16> %out155}156 157define <vscale x 4 x i32> @uqxtnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {158; CHECK-LABEL: uqxtnt_d:159; CHECK: // %bb.0:160; CHECK-NEXT: uqxtnt z0.s, z1.d161; CHECK-NEXT: ret162 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnt.nxv2i64(<vscale x 4 x i32> %a,163 <vscale x 2 x i64> %b)164 ret <vscale x 4 x i32> %out165}166 167;168; SQXTUNT169;170 171define <vscale x 16 x i8> @sqxtunt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {172; CHECK-LABEL: sqxtunt_h:173; CHECK: // %bb.0:174; CHECK-NEXT: sqxtunt z0.b, z1.h175; CHECK-NEXT: ret176 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunt.nxv8i16(<vscale x 16 x i8> %a,177 <vscale x 8 x i16> %b)178 ret <vscale x 16 x i8> %out179}180 181define <vscale x 8 x i16> @sqxtunt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {182; CHECK-LABEL: sqxtunt_s:183; CHECK: // %bb.0:184; CHECK-NEXT: sqxtunt z0.h, z1.s185; CHECK-NEXT: ret186 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunt.nxv4i32(<vscale x 8 x i16> %a,187 <vscale x 4 x i32> %b)188 ret <vscale x 8 x i16> %out189}190 191define <vscale x 4 x i32> @sqxtunt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {192; CHECK-LABEL: sqxtunt_d:193; CHECK: // %bb.0:194; CHECK-NEXT: sqxtunt z0.s, z1.d195; CHECK-NEXT: ret196 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunt.nxv2i64(<vscale x 4 x i32> %a,197 <vscale x 2 x i64> %b)198 ret <vscale x 4 x i32> %out199}200 201declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnb.nxv8i16(<vscale x 8 x i16>)202declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnb.nxv4i32(<vscale x 4 x i32>)203declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnb.nxv2i64(<vscale x 2 x i64>)204 205declare <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnb.nxv8i16(<vscale x 8 x i16>)206declare <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnb.nxv4i32(<vscale x 4 x i32>)207declare <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnb.nxv2i64(<vscale x 2 x i64>)208 209declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunb.nxv8i16(<vscale x 8 x i16>)210declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunb.nxv4i32(<vscale x 4 x i32>)211declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunb.nxv2i64(<vscale x 2 x i64>)212 213declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)214declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)215declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)216 217declare <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)218declare <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)219declare <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)220 221declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)222declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)223declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)224