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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6;7; CADD8;9 10define <vscale x 16 x i8> @cadd_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {11; CHECK-LABEL: cadd_b:12; CHECK: // %bb.0:13; CHECK-NEXT: cadd z0.b, z0.b, z1.b, #9014; CHECK-NEXT: ret15 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.cadd.x.nxv16i8(<vscale x 16 x i8> %a,16 <vscale x 16 x i8> %b,17 i32 90)18 ret <vscale x 16 x i8> %out19}20 21define <vscale x 8 x i16> @cadd_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {22; CHECK-LABEL: cadd_h:23; CHECK: // %bb.0:24; CHECK-NEXT: cadd z0.h, z0.h, z1.h, #9025; CHECK-NEXT: ret26 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.cadd.x.nxv8i16(<vscale x 8 x i16> %a,27 <vscale x 8 x i16> %b,28 i32 90)29 ret <vscale x 8 x i16> %out30}31 32define <vscale x 4 x i32> @cadd_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {33; CHECK-LABEL: cadd_s:34; CHECK: // %bb.0:35; CHECK-NEXT: cadd z0.s, z0.s, z1.s, #27036; CHECK-NEXT: ret37 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.cadd.x.nxv4i32(<vscale x 4 x i32> %a,38 <vscale x 4 x i32> %b,39 i32 270)40 ret <vscale x 4 x i32> %out41}42 43define <vscale x 2 x i64> @cadd_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {44; CHECK-LABEL: cadd_d:45; CHECK: // %bb.0:46; CHECK-NEXT: cadd z0.d, z0.d, z1.d, #27047; CHECK-NEXT: ret48 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.cadd.x.nxv2i64(<vscale x 2 x i64> %a,49 <vscale x 2 x i64> %b,50 i32 270)51 ret <vscale x 2 x i64> %out52}53 54;55; SQCADD56;57 58define <vscale x 16 x i8> @sqcadd_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {59; CHECK-LABEL: sqcadd_b:60; CHECK: // %bb.0:61; CHECK-NEXT: sqcadd z0.b, z0.b, z1.b, #9062; CHECK-NEXT: ret63 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqcadd.x.nxv16i8(<vscale x 16 x i8> %a,64 <vscale x 16 x i8> %b,65 i32 90)66 ret <vscale x 16 x i8> %out67}68 69define <vscale x 8 x i16> @sqcadd_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {70; CHECK-LABEL: sqcadd_h:71; CHECK: // %bb.0:72; CHECK-NEXT: sqcadd z0.h, z0.h, z1.h, #9073; CHECK-NEXT: ret74 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcadd.x.nxv8i16(<vscale x 8 x i16> %a,75 <vscale x 8 x i16> %b,76 i32 90)77 ret <vscale x 8 x i16> %out78}79 80define <vscale x 4 x i32> @sqcadd_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {81; CHECK-LABEL: sqcadd_s:82; CHECK: // %bb.0:83; CHECK-NEXT: sqcadd z0.s, z0.s, z1.s, #27084; CHECK-NEXT: ret85 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqcadd.x.nxv4i32(<vscale x 4 x i32> %a,86 <vscale x 4 x i32> %b,87 i32 270)88 ret <vscale x 4 x i32> %out89}90 91define <vscale x 2 x i64> @sqcadd_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {92; CHECK-LABEL: sqcadd_d:93; CHECK: // %bb.0:94; CHECK-NEXT: sqcadd z0.d, z0.d, z1.d, #27095; CHECK-NEXT: ret96 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqcadd.x.nxv2i64(<vscale x 2 x i64> %a,97 <vscale x 2 x i64> %b,98 i32 270)99 ret <vscale x 2 x i64> %out100}101 102;103; CMLA104;105 106define <vscale x 16 x i8> @cmla_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {107; CHECK-LABEL: cmla_b:108; CHECK: // %bb.0:109; CHECK-NEXT: cmla z0.b, z1.b, z2.b, #90110; CHECK-NEXT: ret111 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> %a,112 <vscale x 16 x i8> %b,113 <vscale x 16 x i8> %c,114 i32 90)115 ret <vscale x 16 x i8> %out116}117 118define <vscale x 8 x i16> @cmla_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {119; CHECK-LABEL: cmla_h:120; CHECK: // %bb.0:121; CHECK-NEXT: cmla z0.h, z1.h, z2.h, #180122; CHECK-NEXT: ret123 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> %a,124 <vscale x 8 x i16> %b,125 <vscale x 8 x i16> %c,126 i32 180)127 ret <vscale x 8 x i16> %out128}129 130define <vscale x 4 x i32> @cmla_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {131; CHECK-LABEL: cmla_s:132; CHECK: // %bb.0:133; CHECK-NEXT: cmla z0.s, z1.s, z2.s, #270134; CHECK-NEXT: ret135 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> %a,136 <vscale x 4 x i32> %b,137 <vscale x 4 x i32> %c,138 i32 270)139 ret <vscale x 4 x i32> %out140}141 142define <vscale x 2 x i64> @cmla_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {143; CHECK-LABEL: cmla_d:144; CHECK: // %bb.0:145; CHECK-NEXT: cmla z0.d, z1.d, z2.d, #0146; CHECK-NEXT: ret147 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> %a,148 <vscale x 2 x i64> %b,149 <vscale x 2 x i64> %c,150 i32 0)151 ret <vscale x 2 x i64> %out152}153 154;155; CMLA_LANE156;157 158define <vscale x 8 x i16> @cmla_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {159; CHECK-LABEL: cmla_lane_h:160; CHECK: // %bb.0:161; CHECK-NEXT: cmla z0.h, z1.h, z2.h[1], #180162; CHECK-NEXT: ret163 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.lane.x.nxv8i16(<vscale x 8 x i16> %a,164 <vscale x 8 x i16> %b,165 <vscale x 8 x i16> %c,166 i32 1,167 i32 180)168 ret <vscale x 8 x i16> %out169}170 171define <vscale x 4 x i32> @cmla_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {172; CHECK-LABEL: cmla_lane_s:173; CHECK: // %bb.0:174; CHECK-NEXT: cmla z0.s, z1.s, z2.s[0], #270175; CHECK-NEXT: ret176 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.lane.x.nxv4i32(<vscale x 4 x i32> %a,177 <vscale x 4 x i32> %b,178 <vscale x 4 x i32> %c,179 i32 0,180 i32 270)181 ret <vscale x 4 x i32> %out182}183 184;185; QRDCMLAH186;187 188define <vscale x 16 x i8> @sqrdcmlah_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {189; CHECK-LABEL: sqrdcmlah_b:190; CHECK: // %bb.0:191; CHECK-NEXT: sqrdcmlah z0.b, z1.b, z2.b, #0192; CHECK-NEXT: ret193 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8(<vscale x 16 x i8> %a,194 <vscale x 16 x i8> %b,195 <vscale x 16 x i8> %c,196 i32 0)197 ret <vscale x 16 x i8> %out198}199 200define <vscale x 8 x i16> @sqrdcmlah_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {201; CHECK-LABEL: sqrdcmlah_h:202; CHECK: // %bb.0:203; CHECK-NEXT: sqrdcmlah z0.h, z1.h, z2.h, #90204; CHECK-NEXT: ret205 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16(<vscale x 8 x i16> %a,206 <vscale x 8 x i16> %b,207 <vscale x 8 x i16> %c,208 i32 90)209 ret <vscale x 8 x i16> %out210}211 212define <vscale x 4 x i32> @sqrdcmlah_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {213; CHECK-LABEL: sqrdcmlah_s:214; CHECK: // %bb.0:215; CHECK-NEXT: sqrdcmlah z0.s, z1.s, z2.s, #180216; CHECK-NEXT: ret217 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32(<vscale x 4 x i32> %a,218 <vscale x 4 x i32> %b,219 <vscale x 4 x i32> %c,220 i32 180)221 ret <vscale x 4 x i32> %out222}223 224define <vscale x 2 x i64> @sqrdcmlah_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {225; CHECK-LABEL: sqrdcmlah_d:226; CHECK: // %bb.0:227; CHECK-NEXT: sqrdcmlah z0.d, z1.d, z2.d, #270228; CHECK-NEXT: ret229 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64(<vscale x 2 x i64> %a,230 <vscale x 2 x i64> %b,231 <vscale x 2 x i64> %c,232 i32 270)233 ret <vscale x 2 x i64> %out234}235 236;237; QRDCMLAH_LANE238;239 240define <vscale x 8 x i16> @sqrdcmlah_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {241; CHECK-LABEL: sqrdcmlah_lane_h:242; CHECK: // %bb.0:243; CHECK-NEXT: sqrdcmlah z0.h, z1.h, z2.h[1], #90244; CHECK-NEXT: ret245 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16(<vscale x 8 x i16> %a,246 <vscale x 8 x i16> %b,247 <vscale x 8 x i16> %c,248 i32 1,249 i32 90)250 ret <vscale x 8 x i16> %out251}252 253define <vscale x 4 x i32> @sqrdcmlah_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {254; CHECK-LABEL: sqrdcmlah_lane_s:255; CHECK: // %bb.0:256; CHECK-NEXT: sqrdcmlah z0.s, z1.s, z2.s[0], #180257; CHECK-NEXT: ret258 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32(<vscale x 4 x i32> %a,259 <vscale x 4 x i32> %b,260 <vscale x 4 x i32> %c,261 i32 0,262 i32 180)263 ret <vscale x 4 x i32> %out264}265 266declare <vscale x 16 x i8> @llvm.aarch64.sve.cadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)267declare <vscale x 8 x i16> @llvm.aarch64.sve.cadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)268declare <vscale x 4 x i32> @llvm.aarch64.sve.cadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)269declare <vscale x 2 x i64> @llvm.aarch64.sve.cadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)270 271declare <vscale x 16 x i8> @llvm.aarch64.sve.sqcadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)272declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)273declare <vscale x 4 x i32> @llvm.aarch64.sve.sqcadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)274declare <vscale x 2 x i64> @llvm.aarch64.sve.sqcadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)275 276declare <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)277declare <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)278declare <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)279declare <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)280 281declare <vscale x 8 x i16> @llvm.aarch64.sve.cmla.lane.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32, i32)282declare <vscale x 4 x i32> @llvm.aarch64.sve.cmla.lane.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32, i32)283 284declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrdcmlah.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)285declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)286declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)287declare <vscale x 2 x i64> @llvm.aarch64.sve.sqrdcmlah.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)288 289declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32, i32)290declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrdcmlah.lane.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32, i32)291