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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3 4;5; SQSUB6;7 8define <vscale x 16 x i8> @sqsub_i8_u(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {9; CHECK-LABEL: sqsub_i8_u:10; CHECK: // %bb.0:11; CHECK-NEXT: sqsub z0.b, z0.b, z1.b12; CHECK-NEXT: ret13 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.u.nxv16i8(<vscale x 16 x i1> %pg,14 <vscale x 16 x i8> %a,15 <vscale x 16 x i8> %b)16 ret <vscale x 16 x i8> %out17}18 19define <vscale x 8 x i16> @sqsub_i16_u(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {20; CHECK-LABEL: sqsub_i16_u:21; CHECK: // %bb.0:22; CHECK-NEXT: sqsub z0.h, z0.h, z1.h23; CHECK-NEXT: ret24 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.u.nxv8i16(<vscale x 8 x i1> %pg,25 <vscale x 8 x i16> %a,26 <vscale x 8 x i16> %b)27 ret <vscale x 8 x i16> %out28}29 30define <vscale x 4 x i32> @sqsub_i32_u(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {31; CHECK-LABEL: sqsub_i32_u:32; CHECK: // %bb.0:33; CHECK-NEXT: sqsub z0.s, z0.s, z1.s34; CHECK-NEXT: ret35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.u.nxv4i32(<vscale x 4 x i1> %pg,36 <vscale x 4 x i32> %a,37 <vscale x 4 x i32> %b)38 ret <vscale x 4 x i32> %out39}40 41define <vscale x 2 x i64> @sqsub_i64_u(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {42; CHECK-LABEL: sqsub_i64_u:43; CHECK: // %bb.0:44; CHECK-NEXT: sqsub z0.d, z0.d, z1.d45; CHECK-NEXT: ret46 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.u.nxv2i64(<vscale x 2 x i1> %pg,47 <vscale x 2 x i64> %a,48 <vscale x 2 x i64> %b)49 ret <vscale x 2 x i64> %out50}51 52;53; UQSUB54;55 56define <vscale x 16 x i8> @uqsub_i8_u(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {57; CHECK-LABEL: uqsub_i8_u:58; CHECK: // %bb.0:59; CHECK-NEXT: uqsub z0.b, z0.b, z1.b60; CHECK-NEXT: ret61 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.u.nxv16i8(<vscale x 16 x i1> %pg,62 <vscale x 16 x i8> %a,63 <vscale x 16 x i8> %b)64 ret <vscale x 16 x i8> %out65}66 67define <vscale x 8 x i16> @uqsub_i16_u(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {68; CHECK-LABEL: uqsub_i16_u:69; CHECK: // %bb.0:70; CHECK-NEXT: uqsub z0.h, z0.h, z1.h71; CHECK-NEXT: ret72 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.u.nxv8i16(<vscale x 8 x i1> %pg,73 <vscale x 8 x i16> %a,74 <vscale x 8 x i16> %b)75 ret <vscale x 8 x i16> %out76}77 78define <vscale x 4 x i32> @uqsub_i32_u(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {79; CHECK-LABEL: uqsub_i32_u:80; CHECK: // %bb.0:81; CHECK-NEXT: uqsub z0.s, z0.s, z1.s82; CHECK-NEXT: ret83 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.u.nxv4i32(<vscale x 4 x i1> %pg,84 <vscale x 4 x i32> %a,85 <vscale x 4 x i32> %b)86 ret <vscale x 4 x i32> %out87}88 89define <vscale x 2 x i64> @uqsub_i64_u(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {90; CHECK-LABEL: uqsub_i64_u:91; CHECK: // %bb.0:92; CHECK-NEXT: uqsub z0.d, z0.d, z1.d93; CHECK-NEXT: ret94 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.u.nxv2i64(<vscale x 2 x i1> %pg,95 <vscale x 2 x i64> %a,96 <vscale x 2 x i64> %b)97 ret <vscale x 2 x i64> %out98}99 100declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)101declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)102declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)103declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)104 105declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)106declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)107declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)108declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)109